1281713 九、發明說明： 此美國非臨時專利申請案根據35 U.S.c. §119主張於 003年5月27日中4的南韓專利中請案第細3號之 優先權，其全部内容已藉由引用之方式併入本文。 【發明所屬之技術領域】 本發明係有關-種用於钱刻—半導體晶圓之—邊緣的晶 圓邊緣蝕刻裝置及方法。 【先前技術】 執行晶圓邊緣蝕刻係用於移除位於一晶圓周邊區域中的 薄膜層。該晶圓周邊區域常常稱為一邊緣珠粒。之所以對 晶圓邊緣珠粒進行蝕刻，係因為在製造程序過程中，位於 邊緣上的薄膜層會造成晶片缺陷，並會減少產量。藉由一 濕式或乾式蝕刻法可將薄膜層從該邊緣移除。由於晶片尺 度的縮小’對邊緣進行蝕刻已變得更加重要。 存在用以蝕刻位於邊緣珠粒的該等薄膜層之傳統裝置。 然而在傳統裝置中，藉由此類裝置產生的電漿係甚微弱， 以致不能蝕刻位於邊緣珠粒的薄膜層。此問題的一解決方 式係增加電源· :。•然而增加電源可能使晶圓彎曲。 【發明内容】 在範例性具體實施例中，本發明係針對一種用於蝕刻一 半導體晶圓之一邊緣的裝置，該裝置包括一底部電極，其 係配置於該半導體晶圓下方並作為一平臺來支撐該半導體 晶圓。 在範例性具體貫施例中’本發明係針對一種餘刻一半導 93376.doc 1281713 體晶圓之方法’該方法包括：將—半導體晶圓插入一室内. 增加該室内之壓力；在進一步增加該壓力日寺，向該室供應 至少-蝕刻劑氣體；向該室供應電源並在半導體晶圓之邊 緣珠粒或背㈣刻該半導體晶圓；停止電源錢刻劑氣體 供應Hit風氣體對該室進行通風；以及將通風氣體 從該室清除。 在範例性具體實施例中，本發明係針對—種㈣一半導 體晶圓之方法，該方法包括··於該半導體晶圓下方配置一 ，部電極’其係料-平臺來切半導體晶圓；在半導體 曰曰0之邊緣珠粒或背面_該半導體晶圓；以及在半導體 晶圓與—絕緣板之間保持—從〇 2至約i 〇醜的間隙。 在範例性具體實施财，本發日㈣針對—種㈣一半導 體晶圓之方法，該方法包括·· 、成千V體晶圓上方配置包 :突出部分的-絕緣板；在半導體晶圓之邊緣珠粒或背 持該半㈣晶圓；以及在半導體晶圓與絕緣板之間保 待一從0.2至約1·〇 mm的間隙。 雕=例性具體實施例中，本發明係針對—種㈣一半導 之方法該方法包括：於該半夢體晶圓下方配置一 =極喜該底部電極包括複數個開放溝槽；以及 月豆日日囡之邊緣珠粒或背面蝕刻該半導體晶圓。 在範例性具體實施例中，本二種 絕緣板包括：-主體，其_ =龍緣板，该 分，田、、巴緣材枓製成；以及-突出部 刀其包括一傾斜表面與一峭壁表面。 【實施方式】 93376.doc 1281713 根據以下詳細描述並參考附圖會更加全面理解本發明， 此等描述及附圖僅用於說明之目㈤，因❿並不限制本發明。 圖1說明依據本發明之一項範例性具體實施例的一裝置 10〇。裝置1〇〇包括：一上部電極10、一底部電極及平臺2〇、 一邊緣電極30、以及絕緣板40、—RF電源供應5〇、一隔離 器及/或絕緣體60、一中心噴嘴70以及一程序噴嘴⑽。在圖 1所示裝置100中，上部電極10及邊緣電極3〇係陽極，而底 邛琶極2 0係陰極。然而在本發明的其他範例性具體實施例 中，母一此等電極可以相反。如圖！所示，底部電極支撐 晶圓1，而上部電極1〇與邊緣電極3〇在晶圓1的邊緣及/或背 面相互產生笔漿。a曰圓1之遠邊緣位置的一姓刻部分a係所 而餘刻應發生之處。由於RF電源係由RF電源線5〇透過晶圓 1來提供，故一下部電源會產生充分適當的電漿來蝕刻晶圓 1上的溥膜層。下部電源之一範例係5 〇 〇 W。若該rf電源係 車父南（其係一般用於一正常半導體餘刻器中），則會在邊緣珠 粒位置造成孤。 圖2更詳細地說明圖1之裝置1 〇 〇的一範例性部分。特定言 之，圖2更詳細:地說明上部電極1 〇、底部電極2〇、邊緣電極 30、絕緣板40以及晶圓1。如圖2所示，絕緣板40與晶圓1 係藉由一可變距離Η隔開。如圖2所示，絕緣板40可包括一 突出部分41。在一項範例性具體實施例中，突出部分41具 有一傾斜或其他輪廓，其引導處理氣體，從而在钱刻程序 中防止或實質上防止處理氣體流入至晶圓中心區域。雖然 圖2之突出部分41具有一特定形狀，但應注意，此形狀僅係 93376.doc 1281713 範例，且也可在蝕刻程序中使用其他能將處理氣體適當地 引導出晶圓1之中心區域的其他形狀。 圖3更詳細地說明圖2之範例性突出部分41。如圖所示， 突出部分41包括一傾斜部分43及一惰壁45。崎壁45與上部 電極10形成一間隙44。可對突出部分41與上部電極1〇之間 的間隙44進行控制，以控制晶圓}的已蝕刻區域。在一項範 例性具體貫施例中，儘管不需要如此，但間隙44係均勻的 或貫質上均勻的。在其他範例性具體實施例中，可對峭壁 45的形狀進行設計，以提高峭壁45及/或絕緣板仞的耐用 性。 圖4 A說明本發明之一項範例性具體實施例中之圖1的底 部電極及平臺20。如圖4A所示，該底部電極2〇包括一或多 個溝槽3卜—或多個溝槽31可減少或防止晶圓1從底部電極 及平臺20處滑落。如圖4A所示，—或多個溝槽㈣顯示為 自底部電極20之中心輻射的直線。在其他範例性具體實施 例中，溝槽31可為曲線。在本發明之其他範例性具體實施 例中，4等直線及/或曲線溝槽3 i可自除底部電極如之中心 以外的位置輻:射。在本發明之範例性具體實施例中，溝槽 3 1形成一開放圖案，盘一本+ Μ闰安丄 门 ^ /、封閉圖案如一圓形、矩形、三角 形等相對。在本發明之範例性具體實施例中，底部電:及 平臺可包括-或多個螺栓孔33及/或—或多個升 35 〇 圖4Β顯示本發明之一 1 0及絕緣板40的示意圖 項範例性具體實施例中之上部電極 ，以及圖4C顯示本發明之一項範例 93376.doc 1281713 體属麵例中之底部電極及平臺2〇與邊緣電極3〇的 圖。 立圖4B顯示其中分散有程序氣體及/或惰性氣體的一上部 =分。如圖4B所示，上部電極1〇可包括程序氣體乃的一或 夕個來源，以及惰性氣體76的一或多個來源，並伴隨有一 上邛电極支撐74a。亦如圖4B所示，絕緣板4〇可包括一或多 们補充氣體出口 79c及一或多個補充絕緣板79d。 在本發明之範例性具體實施例中，上部電極1〇包括一或 多個螺拴孔74c、79b，用以將絕緣板4〇連接至上部電極1〇。 在本發明之其他範例性具體實施例中，絕緣板4〇包括一或 多個螺栓孔79a，用以將絕緣板4〇連接至一或多個補充絕緣 板 79d。 S 4C σ兒明叙載晶圓1的一下部部分。如圖4c所示，可在 底部電極20與邊緣電極30之間利用一第一絕緣體料（其可 為一圓環狀）與一第二絕緣體85(其可為一圓柱板狀）。 圖5說明本發明之一項範例性具體實施例中底部電極及 平堂20、隔離器及/或絕緣體6〇、晶圓i以及邊緣電極川之 間的關係。·>· 圖6說明依據本發明之另一項範例性具體實施例的一裝 置200。如圖6所示，裝置2〇〇包括：一上部電極11〇、底部 電極及平臺120、一第一邊緣電極13〇、一第二邊緣電極 140、一絕緣體150、一rF電源供應16〇以及一接地終端丨川。 如圖6所示，底部電極及平臺12〇支撐晶圓1，而上部電極 110、第一邊緣電極130與第二邊緣電極14〇在晶圓1的邊緣 93376.doc -10- 1281713 珠粒及/或背面相互產生電漿。如上述，並結合圖丨所示具 體實施例，上部電極110、底部電極及平臺12〇、第一電極 130以及第二電極14〇可各為一陽極或一陰極。 在範例性具體實施例中，第一邊緣電極13〇及/或第二邊 緣電極⑽為圓環狀電極’其聚焦電漿於晶圓1之邊緣珠粒 及/或背面。 在圖6所不範例性具體實施例中，由於rf電源係透過晶圓 1來供應，故可使用一下部電源來產生充足的電漿，用以蝕 刻晶圓1上的薄膜層。下部電源之一範例為5⑽瓦。如上述， 一傳統2000瓦RF電源可能在邊緣珠粒位置造成弧。 應注意，圖2與4中所示絕緣板的各種範例性具體實施例 及/或圖4與5中所示底部電極2〇的各種範例性具體實施例 也可應用於圖6所示範例性具體實施例之中。 圖7說明依據本發明之另一項範例性具體實施例的一裝 置3 〇〇。如圖所示，裝置30〇包括：一底部電極及平臺220、 邊、’表包極240、一絕緣體250以及一 RF電源供應280。如圖 7所不，底部電極及平臺22〇支撐晶圓i。亦如圖7所示，邊 緣電極240為一，圓環狀邊緣電極，其在晶圓1之邊緣珠粒及/ 或背面相互產生電漿。 應注意’圖2與3中所示絕緣板的各種範例性具體實施例 及/或圖4與5中所示底部電極20的各種範例性具體實施例 也可、纟σ合圖7所不範例性具體實施例來使用。圖8說明依據 本叙明的一範例性方法。在步驟S10中，將晶圓1裝載於一 室内。在步驟S20中，減少該室内的壓力。在步驟S30中， 93376.doc 1281713 在增加壓力日夺，向言亥室供應至少一蝕刻/氣體。纟步驟㈣ 中’亦向該室提供電源’用以在半導體晶圓之邊緣珠粒或 背面蝕刻該半導體晶圓。在步驟S3〇結束後，停止供應該至 少一蝕刻氣體及端部電源，以及在步驟S4〇中，向該室供應 一排氣氣體。在步驟S50中，將該排氣氣體從室内清除，以 及在步驟S60中，將晶圓從室内卸載。 圖9說明經過諸如圖8之範例性程序之一蝕刻程序後的晶 圓1的一誇大的範例。圖1〇Α與1〇B分別說明依據本發明之 一項範例性具體實施例所產生晶圓丨的單元區域及邊緣區 域。如圖10A所示，晶圓i包括：一矽基板31〇、一淺溝渠隔 離（shallow trench isolation ; STI)層 320、一 絕緣層 330、一 鎢（W)層340、一第一/第二氮化物層35〇及一氧化物層36〇。 如圖所示，圖10A說明一晶圓i的單元區域，其包括具有作 用區域311與被動區域312的矽基板3 10。該單元區域亦包括 藉由淺溝渠絕緣（STI) 320形成的溝渠。該單元區域也可進 一步包括一多晶石夕層325。 絕緣層330可以係厚度為3000至8000 A的硼摻雜磷矽酸 鹽玻璃（boron-doped phosphosilicate glass ; BPSG)或四乙基 原矽酸鹽（tetraethylorthosilicate ; TE0S)。鎢（W)層 340可採 用WF6氣體形成，並可具有300至1〇〇〇 A的一厚度。第一與 第二氮化物層330、350可分別具有1500至3500人、以及150 至750 A的一厚度，並採用SiH4+NH3氣體形成。氧化物層360 可採用SiH4+02氣體形成，並具有1〇〇〇至5000 A的一厚度。 應注意，上述厚度與材料僅為範例，且熟習技術人士瞭 93376.doc -12- 1281713 解，也可使用其他厚度與材料。 圖π說明可用於依據本發明之範例性具體實施例來蝕刻 一晶圓的範例性程序條件。如圖u所示，可在一二步驟程 序中70成對餘刻室的準備。第一步驟：增壓；第二準備步 驟·進一步增壓並供應一或多種蝕刻氣體。在蝕刻步驟中： 保持壓力；保持蝕刻氣體供應；並供應RF電源。在第一準 備步驟中，可將壓力增加至丨托。在第二準備步驟中，可將 壓力增加至1.5托，且該等蝕刻氣體可包括氬氣及/4CF心氣 體，其供氣範圍為（例如）氬氣：2〇至2〇〇 sccm ; 氣體： 100至250 s，ccm。在一項範例性具體實施例的蝕刻步驟中， 將RF電源增加至500瓦，壓力保持在丨.5托，並將蝕刻氣體 的流速保持為與第二準備步驟恆定。 一旦晶圓1已經蝕刻，即可對蝕刻室通風，此亦以一二步 ^之方式進行。在第_步驟中，冑開電源，使壓力恢復正 常亚供應-通風氣體，例如A氣體。在一項範例性具體 實施例中，該清除氣體的流速為1()至2⑻s_。在第二通 風步驟中，仍供應通風氣體，並且亦供應一清除氣體。在 y項範例性具:體實施例中，該清除氣體為一惰性氣體，並 、（m )1200 sccm的速率供應。在一項範例性具體實施例 α ^由於σ亥氣體可能會在晶圓1的中心部分造成 :’故在進行邊緣蝕刻處理過程中，諸如惰性氣體的此氣 肢不會流過圖1所示的中心噴嘴7〇。 ”心U上述私源、氣體、壓力及流速均為範例，且孰 習技術人士瞭解’也可使用其他類型或數值。還應注意/，、、 93376.doc -13- 1281713 上述準備、蝕刻以及通風步驟均為範例，並且熟習技術人 士瞭解，此等步驟可以更多或更少步驟形成。 在本發明的範例性具體實施例中，還應注意，由於諸如 ^丨生氣體的該氣體可能會在晶圓丨的中心部分造成弧，故在 進仃邊緣蝕刻程序過程中，此氣體不會流過中心噴嘴川。 圖12A至C說明顯示一晶圓上各種氧化物蝕刻速率之間 的關係的試驗結果，其顯示··僅該晶圓的一邊緣部分受到 蝕刻，而該晶圓的一中心部分並未受到蝕刻。可獲得圖Μ 至c之結果的該等條件包括··一 5〇〇w RF電源、一 is托壓 =、一氬氣與CF4氣體的程序氣體，其中氬氣以7〇 sccm的 抓速供應，而CF4氣體以15〇 sccm的流速供應，以及一 i $ mm間隙。圖12A至C說明在相同或類似程序料下具有相 同或類似蝕刻速率的不同材料層。因此，不同材料層可在 一程序步驟中移除而無需改變或實質上改變程序條件。相 對於其中採用不同化學品來移除不同材料層的傳統濕式方 法而g ’此係一優點。 圖13說明在本發明的一項範例性具體實施例中，該絕緣 板與該上部電極之間的間隙44&軸）相對從一晶圓之一中心 至該晶圓之端點的長度L(y軸）的曲線圖。如圖η所示，[加 上A寻於晶圓！的半徑。例如，圖13中的第一點指示··一厶* mm的姓刻部分八係採用一直徑2〇〇麵的晶圓（半經1⑽讓 的晶圓）與一 1.0 mm的間隙44來產生。從圖13中可以看出， 隨著間隙44增加，L會減少（但a會相應增加）。 圖14為半導體基板之長度（乂軸）相對作為許多不同η值 93376.doc < 14- 1281713 (@所示其位於0 · 3與1 0 · 0之間）的姓刻速率（y轴）的曲線 圖。如圖所不，絕緣板40與晶圓1之間的距離11與絕緣板4〇 的峭壁45與上部電極1〇之間的間隙44之間有一正相關。在 圖14之範例性曲線圖中，採用了一 16 mm的間隙44，且該 欲蝕刻之層為一氧化物。 圖14說明用於數個不同η值的資料，其中一些會顯示較好 的性能⑼如^^^⑼騎米卜當然依據本 發明的具體實施例也可使用從03毫米至1〇〇毫米的距離 Η。 圖15祝明用於依據本發明之一項範例性具體實施例來處 理一晶圓之邊緣的一電漿處理裝置的斷面圖。如圖所示， 該電漿處理裝置可包括：_請、一室㈣、—彈性部件 71a、-晶圓入口/出口72、一清除氣體入口、一上部電極 W、上部電極1〇的-支樓74a、一幹體7仆、一程序氣體來 源75、一程序氣體線路75a、一惰性氣體來源％、一惰性氣 體線路鳩、上部電極1〇的一板77(其可上下移動）、用於上 告P電極10之才反77的一古# ^ 。 支撐77a、用於上部電極10之板77的一 驅動為78、—絕緣板4()、_補充絕緣板他、—補充氣體出 口 ：C、一晶圓卜一底部電極及平臺20、一第一絕緣體84、 第、巴、、彖體85、-邊緣電極3〇、一升降銷88(用以在該底 部電極及平臺20上接納並梦恭曰 一 衣載日日圓1)、一擋板9〇(用以均勻1281713 IX. INSTRUCTIONS: This US non-provisional patent application is based on 35 USc § 119 and claims the priority of the third Korean Patent Application No. 3 of May 27, 003, the entire contents of which have been cited. The way is incorporated herein. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer edge etching apparatus and method for the edge of a semiconductor wafer. [Prior Art] Wafer edge etching is performed to remove a thin film layer located in a peripheral region of a wafer. The peripheral area of the wafer is often referred to as an edge bead. The reason why the wafer edge beads are etched is because the film layer on the edge causes wafer defects during the manufacturing process and reduces throughput. The film layer can be removed from the edge by a wet or dry etch. It has become more important to etch the edges due to the reduction in wafer size. There are conventional devices for etching the film layers located at the edge beads. However, in conventional devices, the plasma generated by such devices is so weak that the film layer located at the edge beads cannot be etched. A solution to this problem is to increase the power supply: :. • However, increasing the power supply may bend the wafer. SUMMARY OF THE INVENTION In an exemplary embodiment, the present invention is directed to an apparatus for etching an edge of a semiconductor wafer, the apparatus including a bottom electrode disposed under the semiconductor wafer and serving as a platform To support the semiconductor wafer. In an exemplary embodiment, 'the present invention is directed to a method of engraving a half-guided 93376.doc 1281713 body wafer'. The method includes: inserting a semiconductor wafer into a chamber. Increasing the pressure in the chamber; further increasing The pressure sun temple supplies at least an etchant gas to the chamber; supplies power to the chamber and beads or backs the semiconductor wafer at the edge of the semiconductor wafer; stops the power source gas supply to the Hit wind gas Ventilation of the chamber; and removal of ventilation gases from the chamber. In an exemplary embodiment, the present invention is directed to a method for a semiconductor wafer, the method comprising: arranging a portion of the semiconductor wafer under the semiconductor wafer to cut the semiconductor wafer; At the edge of the semiconductor 珠0 beads or backside _ the semiconductor wafer; and between the semiconductor wafer and the insulating board - from 〇 2 to about 〇 ugly gap. In an exemplary implementation, the method of the fourth (four)-semiconductor wafer is performed on the present invention. The method includes: a plurality of wafers above the wafer package: a protruding portion of the insulating plate; and a semiconductor wafer Edge beads or back holding the half (four) wafer; and maintaining a gap from 0.2 to about 1 mm between the semiconductor wafer and the insulating plate. In the exemplary embodiment, the present invention is directed to a method of (four) half-conducting. The method includes: configuring a bottom electrode under the semi-dream wafer to include a plurality of open trenches; and a moon bean The semiconductor wafer is etched on the edge of the bead or backside. In an exemplary embodiment, the two insulating plates comprise: a body, a _=long edge plate, the minute, the field, and the bar material; and the protrusion knife includes an inclined surface and a The surface of the cliff. The present invention will be more fully understood from the following detailed description and appended claims. Figure 1 illustrates a device 10A in accordance with an exemplary embodiment of the present invention. The device 1A includes: an upper electrode 10, a bottom electrode and a platform 2A, an edge electrode 30, and an insulating plate 40, an RF power supply 5A, an isolator and/or an insulator 60, a central nozzle 70, and A program nozzle (10). In the apparatus 100 of Fig. 1, the upper electrode 10 and the edge electrode 3 are anodes, and the bottom drain 20 is a cathode. However, in other exemplary embodiments of the invention, the mother-like electrodes may be reversed. As shown! As shown, the bottom electrode supports the wafer 1, and the upper electrode 1〇 and the edge electrode 3〇 generate a paste on each other at the edge and/or the back of the wafer 1. A 曰 The far edge of the circle 1 is the part of the engraved part a and the rest should occur. Since the RF power source is supplied from the RF power line 5 through the wafer 1, the lower power source generates sufficient appropriate plasma to etch the tantalum layer on the wafer 1. An example of a lower power supply is 5 〇 〇 W. If the rf power supply is used by the parent (which is typically used in a normal semiconductor remandator), it will be orphaned at the edge bead position. Figure 2 illustrates an exemplary portion of the apparatus 1 图 of Figure 1 in more detail. Specifically, Fig. 2 illustrates the upper electrode 1 〇, the bottom electrode 2 〇, the edge electrode 30, the insulating plate 40, and the wafer 1 in more detail. As shown in FIG. 2, the insulating plate 40 and the wafer 1 are separated by a variable distance Η. As shown in Fig. 2, the insulating plate 40 may include a protruding portion 41. In an exemplary embodiment, the projection 41 has a slope or other profile that directs the process gas to prevent or substantially prevent process gas from flowing into the center region of the wafer during the engraving process. Although the protruding portion 41 of FIG. 2 has a specific shape, it should be noted that this shape is only an example of 93376.doc 1281713, and other processing regions capable of properly guiding the processing gas out of the central region of the wafer 1 may be used in the etching process. Other shapes. Figure 3 illustrates the exemplary projection 41 of Figure 2 in more detail. As shown, the protruding portion 41 includes an inclined portion 43 and an inert wall 45. The wall 45 forms a gap 44 with the upper electrode 10. The gap 44 between the protruding portion 41 and the upper electrode 1A can be controlled to control the etched area of the wafer}. In an exemplary embodiment, although not required, the gap 44 is uniform or uniform in quality. In other exemplary embodiments, the shape of the cliff 45 can be designed to increase the durability of the cliff 45 and/or the insulating panel. Figure 4A illustrates the bottom electrode and platform 20 of Figure 1 in an exemplary embodiment of the invention. As shown in Figure 4A, the bottom electrode 2A includes one or more trenches 3 - or a plurality of trenches 31 to reduce or prevent the wafer 1 from slipping off the bottom electrode and the platform 20. As shown in Fig. 4A, - or a plurality of grooves (4) are shown as straight lines radiated from the center of the bottom electrode 20. In other exemplary embodiments, the grooves 31 can be curved. In other exemplary embodiments of the present invention, the four-line and/or curved grooves 3 i may be radiated from a position other than the center of the bottom electrode. In an exemplary embodiment of the present invention, the trenches 3 1 form an open pattern, the discs are + Μ闰 丄 ^, and the closed patterns are opposite, such as a circle, a rectangle, a triangle, and the like. In an exemplary embodiment of the invention, the bottom electricity: and the platform may include - or a plurality of bolt holes 33 and/or - or a plurality of liters 35 〇 FIG. 4A shows a schematic view of one of the present invention 10 and the insulating plate 40. The upper electrode of the exemplary embodiment, and FIG. 4C shows a bottom electrode of the exemplary embodiment 93376.doc 1281713 and a map of the land 2 〇 and the edge electrode 3 。. Figure 4B shows an upper portion of the program gas and/or inert gas dispersed therein. As shown in Fig. 4B, the upper electrode 1A may include one or more sources of the process gas, and one or more sources of the inert gas 76, accompanied by an upper electrode support 74a. As also shown in Fig. 4B, the insulating plate 4A may include one or more supplementary gas outlets 79c and one or more supplementary insulating plates 79d. In an exemplary embodiment of the invention, the upper electrode 1A includes one or more threaded holes 74c, 79b for connecting the insulating plate 4 to the upper electrode 1''. In other exemplary embodiments of the invention, the insulating plate 4 includes one or more bolt holes 79a for connecting the insulating plate 4 to one or more supplementary insulating plates 79d. S 4C σ 儿明 describes the lower part of the wafer 1 . As shown in Fig. 4c, a first insulator (which may be an annular shape) and a second insulator 85 (which may be a cylindrical plate) may be used between the bottom electrode 20 and the edge electrode 30. Figure 5 illustrates the relationship between the bottom electrode and the flat 20, the isolator and/or the insulator 6A, the wafer i, and the edge electrode in an exemplary embodiment of the present invention. > Figure 6 illustrates a device 200 in accordance with another exemplary embodiment of the present invention. As shown in FIG. 6, the device 2 includes an upper electrode 11A, a bottom electrode and a platform 120, a first edge electrode 13A, a second edge electrode 140, an insulator 150, an rF power supply 16A, and A grounding terminal 丨川. As shown in FIG. 6, the bottom electrode and the substrate 12A support the wafer 1, and the upper electrode 110, the first edge electrode 130 and the second edge electrode 14 are at the edge of the wafer 1 93376.doc -10- 1281713 beads and / or the back side produces plasma. As described above, and in conjunction with the specific embodiment shown in the drawings, the upper electrode 110, the bottom electrode and the stage 12, the first electrode 130, and the second electrode 14 can each be an anode or a cathode. In an exemplary embodiment, the first edge electrode 13 and/or the second edge electrode (10) is a toroidal electrode that focuses plasma on the edge of the wafer 1 and/or the back side. In the non-exemplified embodiment of Figure 6, since the rf power source is supplied through the wafer 1, a lower power source can be used to generate sufficient plasma to etch the thin film layer on the wafer 1. An example of a lower power source is 5 (10) watts. As noted above, a conventional 2000 watt RF power source may create an arc at the edge bead position. It should be noted that various exemplary embodiments of the insulating plates shown in FIGS. 2 and 4 and/or various exemplary embodiments of the bottom electrodes 2A shown in FIGS. 4 and 5 are also applicable to the exemplary embodiment shown in FIG. Among the specific embodiments. Figure 7 illustrates a device 3 in accordance with another exemplary embodiment of the present invention. As shown, device 30A includes a bottom electrode and platform 220, an edge, a 'package pole 240, an insulator 250, and an RF power supply 280. As shown in Figure 7, the bottom electrode and the platform 22 support the wafer i. As also shown in Fig. 7, the edge electrode 240 is a ring-shaped edge electrode which generates plasma at the edges of the wafer 1 and/or the back side. It should be noted that various exemplary embodiments of the insulating plates shown in FIGS. 2 and 3 and/or various exemplary embodiments of the bottom electrode 20 shown in FIGS. 4 and 5 may also be exemplified by FIG. Specific embodiments are used. Figure 8 illustrates an exemplary method in accordance with the present description. In step S10, the wafer 1 is loaded in an indoor chamber. In step S20, the pressure in the chamber is reduced. In step S30, 93376.doc 1281713 is supplied with at least one etch/gas to the chamber. In step (4), 'the power is also supplied to the chamber' to etch the semiconductor wafer on the edge or back of the semiconductor wafer. After the end of step S3, the supply of the at least one etching gas and the end power source is stopped, and in step S4, an exhaust gas is supplied to the chamber. In step S50, the exhaust gas is removed from the chamber, and in step S60, the wafer is unloaded from the chamber. Figure 9 illustrates an exaggerated example of a wafer 1 after an etching procedure such as one of the exemplary procedures of Figure 8. 1A and 1B illustrate a cell region and an edge region of a wafer defect produced in accordance with an exemplary embodiment of the present invention, respectively. As shown in FIG. 10A, the wafer i includes a germanium substrate 31, a shallow trench isolation (STI) layer 320, an insulating layer 330, a tungsten (W) layer 340, and a first/second layer. The nitride layer 35 and the oxide layer 36 are. As shown, Figure 10A illustrates a cell area of a wafer i including a germanium substrate 3 10 having a working region 311 and a passive region 312. The cell region also includes trenches formed by shallow trench isolation (STI) 320. The cell region can also further include a polycrystalline layer 325. The insulating layer 330 may be boron-doped phosphosilicate glass (BPSG) or tetraethylorthosilicate (TEOS) having a thickness of 3000 to 8000 Å. The tungsten (W) layer 340 may be formed using WF6 gas and may have a thickness of 300 to 1 Å. The first and second nitride layers 330, 350 may each have a thickness of 1500 to 3500 Å, and 150 to 750 Å, and are formed using SiH4 + NH3 gas. The oxide layer 360 may be formed using SiH4+02 gas and has a thickness of from 1 Å to 5,000 Å. It should be noted that the above thicknesses and materials are merely examples, and those skilled in the art can use 93376.doc -12- 1281713 solutions, and other thicknesses and materials can also be used. Figure π illustrates exemplary program conditions that can be used to etch a wafer in accordance with an exemplary embodiment of the present invention. As shown in Figure u, 70 pairs of residual chambers can be prepared in a two-step procedure. First step: pressurization; second preparation step. Further pressurization and supply of one or more etching gases. In the etching step: maintaining the pressure; maintaining the etching gas supply; and supplying the RF power. In the first preparation step, the pressure can be increased to the chin rest. In the second preparation step, the pressure may be increased to 1.5 Torr, and the etching gases may include argon gas and /4 CF core gas, and the gas supply range is, for example, argon gas: 2 Torr to 2 〇〇 sccm; : 100 to 250 s, ccm. In an etching step of an exemplary embodiment, the RF power source is increased to 500 watts, the pressure is maintained at 丨5 Torr, and the flow rate of the etching gas is maintained constant with the second preparation step. Once the wafer 1 has been etched, the etching chamber can be vented, which is also done in a two-step process. In the _th step, the power is turned off to restore the normal sub-supply to the pressure-ventilating gas, such as A gas. In an exemplary embodiment, the purge gas has a flow rate of 1 () to 2 (8) s. In the second venting step, ventilation gas is still supplied, and a purge gas is also supplied. In the y exemplary embodiment: the embodiment, the purge gas is an inert gas and is supplied at a rate of (m) 1200 sccm. In an exemplary embodiment, α ^ may be caused in the central portion of the wafer 1 because of the sigma gas: ' Therefore, during the edge etching process, such a gas limb such as an inert gas does not flow through as shown in FIG. The center nozzle is 7〇. "The above-mentioned private sources, gases, pressures and flow rates are examples, and those skilled in the art understand that 'other types or values can be used. Also note /,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The venting steps are all examples, and those skilled in the art will appreciate that such steps may be formed in more or fewer steps. In an exemplary embodiment of the invention, it should also be noted that the gas may be due to gases such as An arc is created in the center portion of the wafer crucible so that the gas does not flow through the center nozzle during the edge etching process. Figures 12A through C illustrate the relationship between various oxide etch rates on a wafer. As a result of the test, it is shown that only one edge portion of the wafer is etched, and a central portion of the wafer is not etched. The conditions for obtaining the results of the graphs c to c include... w RF power supply, a pressure of the reactor, a program gas of argon gas and CF4 gas, wherein argon gas is supplied at a picking speed of 7 〇 sccm, and CF4 gas is supplied at a flow rate of 15 〇 sccm, and an i $ mm gap. Figure 12A to C Different layers of material having the same or similar etch rates under the same or similar procedural materials. Thus, different layers of material can be removed in a procedural step without changing or substantially altering the procedural conditions. A conventional wet method of removing layers of different materials is an advantage of this. Figure 13 illustrates that in an exemplary embodiment of the invention, the gap 44 & axis between the insulating plate and the upper electrode is opposite A graph of the length L (y-axis) from the center of one wafer to the end of the wafer. As shown in Figure η, [plus the radius of A found in the wafer! For example, the number in Figure 13 A little bit of indication · a 厶 * mm surname part of the eight series using a diameter 2 〇〇 wafer (half 1 (10) wafer) and a 1.0 mm gap 44 to produce. See you from Figure 13 Out, as the gap 44 increases, L will decrease (but a will increase accordingly). Figure 14 shows the length of the semiconductor substrate (乂 axis) as a number of different η values 93376.doc < 14- 1281713 (@ The curve of the surname rate (y-axis) between 0 · 3 and 1 0 · 0) As shown in the figure, there is a positive correlation between the distance 11 between the insulating plate 40 and the wafer 1 and the gap 44 between the cliff 45 of the insulating plate 4 and the upper electrode 1A. An exemplary graph in FIG. In the case, a 16 mm gap 44 is used, and the layer to be etched is an oxide. Figure 14 illustrates data for several different η values, some of which show better performance (9) such as ^^^(9) riding It is of course possible to use a distance from 03 mm to 1 mm in accordance with a particular embodiment of the invention. Figure 15 illustrates the use of an edge of a wafer in accordance with an exemplary embodiment of the present invention. A cross-sectional view of a plasma processing apparatus. As shown, the plasma processing apparatus may include: a chamber, a chamber (four), an elastic member 71a, a wafer inlet/outlet 72, a purge gas inlet, an upper electrode W, and an upper electrode 1 a floor 74a, a dry body 7 servant, a program gas source 75, a process gas line 75a, an inert gas source %, an inert gas line 鸠, a plate 77 of the upper electrode 1 ( (which can be moved up and down), The P electrode 10 is reported to be an anti-77 of an ancient #^. The support 77a, a drive for the plate 77 of the upper electrode 10 is 78, an insulating plate 4 (), a supplementary insulating plate, a supplementary gas outlet: C, a wafer, a bottom electrode, and a platform 20, a first An insulator 84, a first, a bar, a body 85, an edge electrode 3A, a lift pin 88 (for receiving on the bottom electrode and the platform 20 and dreaming of a clothesday sunday 1), a baffle 9〇 (for uniformity
排出程序氣體或惰性H ” _ )、一感測裔91、一冷卻劑線路 92、-冷卻劑來源94、—灯電源來源96、-升降鎖板97、 用於升降銷板97的-㈣_、以及―排氣㈣。在 93376.doc -15- 1281713 範例性實施例中，該處理裝置也可包 «體實施例中，該裝置包括：不止—準備站至 序y及不止該清除室、以及至少—傳送室。以此方式， 可裝載—晶圓而傳送另一晶圓，並處理另一晶圓。 、如上述’在範例性具體實施例中，諸如RF電源的電源係 透過晶圓來供應，並產生充足的電源，用以產生電漿來蝕 刻薄膜層。應注意，熟習技術人士瞭解：也可透過某一其 他層代替該晶圓來供應電源’或透過除該晶圓外的某一其 :層來提供電源。還應注意，該電源可低於2〇〇〇 w的傳統 電源’例如為結合本發明之—或多項範例性具體實施例所 述的500 W電源。 在一項靶例性具體實施例中，上部電極10為一實心板電 才系〇 在本lx明之la例性具體實施例中，該間隙係用於控制半 導體晶圓上的尺寸與受_區域。在其他範例性具體實施 :中’可使用額外的可互換式絕緣板，每-板可配置於該 實心上部電極附近，且每一板與該實心上部電極之間具有 一不同的間隙尺寸。在範例性具體實施例中，半導體晶圓 與絕緣板間的間隙在0·2舆約1〇 mm之間。 在-項粑例性具體實施例中，可使用〇2與SF6作為钱刻氣 體，單獨使用或與氬氣及/或CF4氣體結合使用。在一項範 例性具體實施例中，純刻氣體會㈣半導體晶圓上所有 需要i虫刻的層。 在-項耗例性具體實施例中，該該絕緣板係由諸如陶竟 93376.doc -16- 1281713 及/或石英之類絕緣材料製成。 雖然本發明已由&方式說明 多方式來變化。此類變化不應 範脅，且對熟悉技彳#人士顯而 包含在以下的申請專利範圍中 【圖式簡單說明】 圖1 $兒明依據本發明之一項』 100 〇 ’但很明顯，本發明可用許 視為背離了本發明之精神及 易見的所有此類修改皆是要 〇 I例性具體實施例的一裝置 圖2更詳細說明圖1之裝置的-範例性部分。 圖3更詳細說明圖2之一範例性突出部分。 圖4 A說明本發明之一項範例性 只專巳1夕』r生具體貫施例中之圖1的該 底部電極及平臺。 圖4B說明本發明之_項範例性具體實施例中之—上部電 極與一絕緣板的示意圖。 圖4C說明本發明之一項範例性具體實施例中之一底部電 極及平臺與一邊緣電極的平面圖。 圖5說明本發明之一項範例性實施例中，一底部電極及平 臺、一隔離器及/或絕緣體、一晶圓與一邊緣電極之間的 範例性關係。 圖6說明依據本發明之另一項範例性具體實施例的一梦 置。 、 圖7說明依據本發明之另一項範例性具體實施例的一裝 置。 圖8說明依據本發明之一項範例性具體實施例的方法。 93376.doc -17 - 1281713 圖9說明經過諸如圖8之範例性程序之餘刻程序後的一誇 大的範例性晶圓。 圖10 A與10B分別說明依據本發明之一項範例性具體實 施例所產生的晶圓的一單元區域及一邊緣區域。 圖11說明可用於依據本發明之範例性具體實施例來蝕刻 該晶圓1的範例性程序條件。 圖12 A至C依據本發明之範例性具體實施例說明顯示一 晶圓上各種氧化物的蝕刻速率之間的關係的試驗結果。 圖13說明本發明之一項範例性具體實施例中，距一晶圓 之端點的長度相對於絕緣板與上部電極之間的間隙的曲線 圖0 圖14說明依據本發明之範例性具體實施例的各種間隙。 圖15說明用於依據本發明之一項範例性具體實施例來處 理一晶圓之邊緣的一電漿處理裝置的斷面圖。 【主要元件符號說明】 1 10 20 30 31 33 35 40 40a 晶圓 上部電極 底部電極及平臺 邊緣電極 溝槽 螺栓孔 升降銷孔 絕緣板 補充絕緣板 93376.doc -18· 1281713 41 突出部分 43 傾斜部分 44 間隙 45 峭壁 50 RF電源供應 60 隔離器/絕緣體 70 中心喷嘴/室 71 室壁 71a 彈性部件 72 晶圓入口 /出口 74a 上部電極支撐 74b 幹體 74c 螺栓孔 75 程序氣體 75a 程序氣體線路 76 惰性氣體 76b 惰性氣體線路 77 上部電極板 77a 支撐 78 驅動器 79a 螺栓孔 79b 螺栓孔 79c 補充氣體出口 79d 補充絕緣板 93376.doc -19- 1281713 80 程序喷嘴 84 第一絕緣體 85 第二絕緣體 88 升降鎖 90 擋板 91 感測器 92 冷卻劑線路 94 冷卻劑來源 100 裝置 96 RF電源來源 97 升降銷板 98 驅動器 99 排氣泵 110 上部電極 120 底部電極及平臺 130 第一邊緣電極 140 第二邊緣電極 150 V 絕緣體 160 RF電源供應 170 接地終端 200 裝置 220 底部電極及平堂 240 邊緣電極 250 絕緣體 93376.doc -20- 1281713 280 RF電源供應 300 裝置 310 矽基板 311 主動區域 312 被動區域 320 淺溝渠隔離層 325 多晶矽層 330 絕緣層 340 鎢層 350 第二氮化物層 360 氧化物層 93376.doc -21 -Exhaust process gas or inert H _ _ ), a sensing source 91, a coolant line 92, a coolant source 94, a lamp power source 96, a lift lock plate 97, a - (four) _ for the lift pin plate 97, And "exhaust (4). In an exemplary embodiment, 93376.doc -15 - 1281713, the processing device may also include a body embodiment, the device comprising: more than - preparing the station to the sequence y and not only the cleaning chamber, and At least - a transfer chamber. In this manner, another wafer can be loaded while the wafer is being transferred, and another wafer is processed. As in the above-described exemplary embodiment, a power source such as an RF power source is passed through the wafer. Supply and generate sufficient power to generate plasma to etch the film layer. It should be noted that those skilled in the art understand that it is also possible to supply power through some other layer instead of the wafer' or through some other than the wafer. One: a layer to provide power. It should also be noted that the power supply can be less than 2 watts of conventional power supply 'for example, in conjunction with the present invention - or a 500 W power supply as described in the various exemplary embodiments. In the specific embodiment, the upper electrode 10 A solid board is used in the exemplary embodiment of the present invention. The gap is used to control the size and the receiving area on the semiconductor wafer. In other exemplary implementations, an additional can be used. Interchangeable insulating plates, each plate can be disposed adjacent to the solid upper electrode, and each plate has a different gap size from the solid upper electrode. In an exemplary embodiment, between the semiconductor wafer and the insulating plate The gap is between about 0.2 mm and about 1 mm. In an exemplary embodiment, 〇2 and SF6 can be used as the engraving gas, either alone or in combination with argon and/or CF4 gas. In an exemplary embodiment, the pure engraved gas will (iv) all of the layers on the semiconductor wafer that require i-insect. In an exemplary embodiment, the insulating plate is made of, for example, Tao Jing 93376.doc -16- 1281713 and / or an insulating material such as quartz. Although the invention has been changed in many ways by the & mode, such changes should not be threatened, and are familiar to those skilled in the art. Patent application scope BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a singularity of the present invention, but it is obvious that all such modifications that can be considered as departing from the spirit of the invention and that are readily apparent are intended to be exemplary. Figure 2 shows a more detailed description of the exemplary portion of the device of Figure 1. Figure 3 illustrates an exemplary highlight of Figure 2 in more detail. Figure 4A illustrates an exemplary embodiment of the present invention. The bottom electrode and the platform of Fig. 1 in the specific embodiment are shown in Fig. 4. Fig. 4B is a schematic view showing an upper electrode and an insulating plate in an exemplary embodiment of the present invention. Fig. 4C illustrates one of the present inventions. A plan view of one of the bottom electrode and the platform and an edge electrode in an exemplary embodiment. Figure 5 illustrates an exemplary relationship between a bottom electrode and a platform, an isolator and/or insulator, a wafer and an edge electrode in an exemplary embodiment of the invention. Figure 6 illustrates a dream in accordance with another exemplary embodiment of the present invention. Figure 7 illustrates an apparatus in accordance with another exemplary embodiment of the present invention. Figure 8 illustrates a method in accordance with an exemplary embodiment of the present invention. 93376.doc -17 - 1281713 Figure 9 illustrates an exaggerated exemplary wafer after a lingering procedure such as the exemplary procedure of Figure 8. 10A and 10B illustrate a cell region and an edge region of a wafer, respectively, produced in accordance with an exemplary embodiment of the present invention. Figure 11 illustrates exemplary program conditions that may be used to etch the wafer 1 in accordance with an exemplary embodiment of the present invention. 12A through C illustrate experimental results showing the relationship between etch rates of various oxides on a wafer in accordance with an exemplary embodiment of the present invention. Figure 13 illustrates a plot of the length of the end of a wafer relative to the gap between the insulating plate and the upper electrode in an exemplary embodiment of the invention. Figure 12 illustrates an exemplary implementation in accordance with the present invention. Various gaps of the example. Figure 15 illustrates a cross-sectional view of a plasma processing apparatus for processing the edges of a wafer in accordance with an exemplary embodiment of the present invention. [Main component symbol description] 1 10 20 30 31 33 35 40 40a Wafer upper electrode bottom electrode and platform edge electrode groove bolt hole lifting pin hole insulation plate supplementary insulation plate 93376.doc -18· 1281713 41 protruding portion 43 inclined portion 44 Clearance 45 Cliff 50 RF Power Supply 60 Isolator / Insulator 70 Center Nozzle / Chamber 71 Chamber Wall 71a Elastic Member 72 Wafer Inlet / Outlet 74a Upper Electrode Support 74b Dry Body 74c Bolt Hole 75 Program Gas 75a Program Gas Line 76 Inert Gas 76b Inert gas line 77 Upper electrode plate 77a Support 78 Driver 79a Bolt hole 79b Bolt hole 79c Supplemental gas outlet 79d Supplemental insulation plate 93376.doc -19- 1281713 80 Program nozzle 84 First insulator 85 Second insulator 88 Lift lock 90 Baffle 91 Sensor 92 Coolant Line 94 Coolant Source 100 Device 96 RF Power Source 97 Lift Pin Plate 98 Driver 99 Exhaust Pump 110 Upper Electrode 120 Bottom Electrode and Platform 130 First Edge Electrode 140 Second Edge Electrode 150 V Insulator 160 RF power supply 170 grounding terminal 200 Device 220 Bottom electrode and flat hall 240 Edge electrode 250 Insulator 93376.doc -20- 1281713 280 RF power supply 300 Device 310 矽 Substrate 311 Active region 312 Passive region 320 Shallow trench isolation layer 325 Polysilicon layer 330 Insulation layer 340 Tungsten layer 350 Second nitride layer 360 oxide layer 93376.doc -21 -