JP2005005321A - Semiconductor substrate, semiconductor device, and these manufacturing methods - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable efficient distortion of a semiconductor layer. <P>SOLUTION: A semiconductor substrate includes a porous layer 12 formed on a substrate 11, a semiconductor layer 13 formed on the porous layer 12, and a strain inductive region 14 which generates strain in the semiconductor layer 13 by applying a stress to the semiconductor layer 13. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor substrate, a semiconductor device, and a manufacturing method thereof.
[0002]
[Prior art]
Conventionally, a heteroepitaxial growth method in which a different material is epitaxially grown on a single crystal substrate is known. In the heteroepitaxial growth method, an epitaxial layer having a distorted crystal lattice can be formed depending on the crystal growth material and conditions. In an epitaxial layer with a distorted crystal lattice, the atomic spacing in the epitaxial layer is widened by tensile stress, so that the effective mass of carriers in the epitaxial layer is reduced and the mobility of carriers can be improved.
[0003]
As a technique using this, a technique for increasing the mobility of carriers by a silicon layer distorted by a SiGe layer (hereinafter referred to as “strained silicon layer”) is disclosed (for example, see Patent Document 1). When silicon is epitaxially grown on the SiGe layer, silicon is formed following SiGe having a lattice constant larger than that of silicon (difference between lattice constants of Si and Ge is about 4%), so that distortion of about several percent occurs. However, it depends on the amount of Ge contained in the SiGe layer.)
[0004]
On the other hand, there is a technique in which tensile stress is applied to the silicon layer from above the silicon layer to distort the crystal lattice of the silicon layer. For example, a technique for improving the mobility of the channel region by applying tensile stress to the channel region from the gate electrode side formed above the channel region is disclosed (for example, see Non-Patent Document 1). .
[0005]
[Patent Document 1]
JP 2000-286418 A
[Non-Patent Document 1]
"Development of two transistor performance enhancement technologies in the cutting-edge semiconductor field" [online], December 17, 2003, Mitsubishi Electric Corporation, Internet, <URL: http: // www. mitsubishielectric. co. jp / news / 2002 / 1217-b. html>
[0006]
[Problems to be solved by the invention]
However, in Patent Document 1, since the SiGe layer includes defects, it is difficult to form a strained silicon layer having high crystallinity. In Non-Patent Document 1, strain is introduced by the device structure formed on the silicon layer after forming the silicon layer without strain. In this case, the silicon layer is placed under the strained silicon layer. Since it is made of a material that is matched before it is distorted, when a strain is applied from the top of the silicon layer, a force is generated in the layer below the silicon layer to prevent it. In general, when biaxial stress is applied to a silicon layer to generate strain, the amount of strain is generated in the plane of silicon according to the following formula 1.
[0007]
ε = (1−ν) · σ / E (Formula 1)
Where ε is the amount of strain in the silicon surface (no unit), ν is the Poisson's ratio (no unit) of the silicon crystal, σ is the biaxial stress [Gpa] applied in the surface of the silicon layer, and E is the silicon It is the Young's modulus [Gpa] of the crystal. Normally, when E = 162 Gpa and ν = 0.26, a stress of σ = 2.2 to 4.4 (Gpa) is required to set the strain amount ε of silicon on SiGe to 1 to 2%. . Therefore, in a general Si-LSI (large-scale integration) structure, it is necessary not only to distort the silicon layer on the surface but also to distort the underlying portion. Therefore, when stress is applied from the upper part or side surface of the silicon layer, it is necessary to apply stress larger than the above value.
[0008]
The present invention has been made in view of the above background, and an object thereof is to efficiently distort a semiconductor layer.
[0009]
[Means for Solving the Problems]
A first aspect of the present invention relates to a semiconductor substrate, a semiconductor layer, a porous layer that supports the semiconductor layer, a strain-inducing region that applies stress to the semiconductor layer to cause distortion in the semiconductor layer, It is characterized by providing.
[0010]
According to a preferred embodiment of the present invention, the porous layer and the semiconductor layer include a plurality of island-shaped regions, and the strain inducing region is formed between the plurality of island-shaped regions. It is desirable.
[0011]
According to a preferred embodiment of the present invention, the semiconductor layer includes a plurality of island-shaped semiconductor regions, and the strain induction region is formed between the plurality of island-shaped semiconductor regions. desirable.
[0012]
According to a preferred embodiment of the present invention, the porous layer is preferably a porous silicon layer.
[0013]
According to a preferred embodiment of the present invention, the semiconductor layer is preferably composed of single crystal silicon.
[0014]
According to a preferred embodiment of the present invention, it is desirable that the strain induction region is made of silicon oxide.
[0015]
According to a preferred embodiment of the present invention, it is desirable that the strain induction region is made of silicon nitride.
[0016]
A second aspect of the present invention relates to a semiconductor device, wherein a semiconductor device is formed in the semiconductor layer.
[0017]
According to a preferred embodiment of the present invention, it is desirable to further include a second strain inducing region that applies a stress to the semiconductor layer to cause strain in the semiconductor layer above the channel of the semiconductor device.
[0018]
A third aspect of the present invention relates to a method of manufacturing a semiconductor substrate, the step of forming a porous layer on a substrate, the step of forming a semiconductor layer on the porous layer, and applying stress to the semiconductor layer. Forming a strain-inducing region that causes strain in the semiconductor layer.
[0019]
According to a preferred embodiment of the present invention, after the step of forming the semiconductor layer, the method further includes a step of partially etching the porous layer and the semiconductor layer to form an opening, and the strain induction In the step of forming the region, it is desirable to form the strain induction region in the opening.
[0020]
According to a preferred embodiment of the present invention, after the step of forming the semiconductor layer, the method further includes a step of partially etching the semiconductor layer to form an opening, and forming the strain induction region Then, it is desirable to form the strain induction region in the opening.
[0021]
According to a preferred embodiment of the present invention, in the step of forming the porous layer, a plurality of porous regions are formed on the substrate, and in the step of forming the strain induction region, the plurality of porous regions are formed. It is desirable to form the strain induction region between the semiconductor layers.
[0022]
A fourth aspect of the present invention relates to a method for manufacturing a semiconductor device, and includes a step of preparing a semiconductor substrate manufactured by applying the above manufacturing method, and a step of fabricating a semiconductor device on the semiconductor substrate. It is characterized by that.
[0023]
According to a preferred embodiment of the present invention, it is preferable to include a step of applying a stress to the semiconductor layer from above the channel of the semiconductor device to further strain the semiconductor layer.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
[0025]
(First embodiment)
FIG. 1A to FIG. 1E are views for explaining a substrate manufacturing method according to a preferred first embodiment of the present invention.
[0026]
In the step shown in FIG. 1A, a substrate 11 is prepared. As the substrate 11, for example, silicon is suitable, but other materials may be adopted.
[0027]
In the step shown in FIG. 1B, the porous layer 12 is formed on the surface of the substrate 11. The Young's modulus of the porous layer 12 is lower than the Young's modulus of the semiconductor layer 13 formed in the step shown in FIG. As a material constituting the porous layer 12, it is preferable to employ porous silicon obtained by making silicon porous. The porous silicon layer can be formed by anodizing the surface of the silicon substrate. Anodization can be performed by disposing an anode and a cathode in an electrolyte containing hydrofluoric acid, disposing a substrate between the electrodes, and passing a current between the electrodes.
[0028]
The porous silicon layer may be composed of a single layer having a substantially uniform porosity, or may be composed of two or more layers having mutually different porosities. Also, the Young's modulus of the porous silicon layer can be changed from at least about 1 GPa to about 83 GPa by changing the porosity (eg, L. Canham, D. Bellet, “Properties of Porous Silicon ", INSPEC, The Institution of Electrical Engineers, p. 127-131).
[0029]
FIG. The relationship between the porosity ρ of porous silicon and the Young's modulus E is illustrated based on the data disclosed in the Bellet paper. As shown in FIG. 5, it can be seen that the higher the porosity of porous silicon, the lower the Young's modulus. When using anodization, the porosity of the porous silicon can be controlled by the solution concentration, current density, specific resistance of the silicon substrate, etc., so that the Young's modulus of the porous silicon is set to a desired value. There is an advantage that can be.
[0030]
In the present invention, the method of forming the porous layer is not limited to anodization, and for example, a method of ion implantation of hydrogen, helium, or the like into the substrate can be employed.
[0031]
In the step shown in FIG. 1C, the semiconductor layer 13 is formed on the porous layer 12 by an epitaxial growth method. A high-quality single crystal semiconductor layer can be formed by an epitaxial growth method.
[0032]
In the process shown in FIG. 1D, after applying a resist on the semiconductor layer 13, the porous layer 12 and the semiconductor layer 13 are patterned by a general lithography process to form openings. Thereby, a plurality of island-shaped porous layers 12 ′ and semiconductor layers 13 ′ are formed on the substrate 11. The width of the opening is not particularly limited, but is preferably 1 μm or more.
[0033]
In the step shown in FIG. 1E, a strain induction region 14 for applying stress to the semiconductor layer 13 ′ is formed on the substrate 11 exposed in the opening formed in the step shown in FIG. The strain-inducing region 14 substantially applies the porous layer 12 ′ and the semiconductor layer 13 ′ to their surfaces so as to apply stress to the semiconductor layer 13 ′ so that the second semiconductor 13 ′ extends in a substantially horizontal direction. Work to pull in parallel direction. In the semiconductor layer 13 ′ to which a tensile force is applied in the in-plane direction by the strain induction region 14, the crystal lattice is distorted, and the mobility of carriers moving in the semiconductor layer 13 ′ is improved. As the strain inducing region 14, for example, silicon oxide or SiN using TEOS (tetraethyl orthosilicate) or the like as a raw material can be employed.
[0034]
As described above, the semiconductor layer 13 ′ is formed so that the carrier mobility of the porous layer 12 ′ formed on the substrate 11, the semiconductor layer 13 ′ formed on the porous layer 12 ′, and the semiconductor layer 13 ′ is increased. A substrate comprising a strain-inducing region 14 for applying a stress to the layer 13 ′ can be produced.
[0035]
For the formation of CVD (chemical vapor deposition) silicon oxide, TEOS, TEOS + O ₂ , TEOS + O ₃ , SiH ₄ + O ₂ , SiH ₄ + N ₂ O, SiH ₂ Cl ₂ + N ₂ O or the like is used. CVD methods include thermal CVD and plasma CVD.
[0036]
Thermal CVD and plasma CVD can be used to form silicon nitride. As a raw material containing Si as a raw material, SiCl ₂ , SiH, SiH ₂ Cl ₂ As a raw material containing N, NH ₃ , N ₂ H ₄ , N ₂ Etc.
[0037]
Further, since the porous layer 12 ′ having a lower Young's modulus than the semiconductor layer 13 ′ is disposed in the lower layer, most of the tensile force applied from the strain induction region 14 to the semiconductor layer 13 ′ is applied to the semiconductor layer 13 ′. Thus, the force for pulling the semiconductor layer 13 'is smaller. In this way, by disposing the porous layer 12 ′ below the semiconductor layer 13 ′ and efficiently converting the tensile force into in-plane strain, it is possible to generate a larger strain with less stress.
[0038]
Further, by forming the island-shaped semiconductor layer 13 ′, each of the semiconductor layers 13 ′ can be distorted independently. In the case where the semiconductor layer 13 is uniformly formed on the porous layer 12, when the semiconductor layer 13 is distorted, the total amount of distortion can be enormous. For example, a strained silicon layer on SiGe is distorted by about 1% in the plane if SiGe is completely relaxed. Considering the diameter of a 300 mm wafer, the total amount of distortion is 3 mm. When distorted from an unstrained state, the silicon layer is 3 mm larger in diameter, but in reality, the entire silicon layer cannot be distorted to such an amount. However, according to the present embodiment, by forming the island-shaped semiconductor layer 13 ′ on the substrate 11, for example, a 1 μm opening is formed on the island of the 10 μm square semiconductor layer 13 ′. The islands of the semiconductor layer 13 ′ can be individually distorted by setting the individual islands of the semiconductor layer 13 ′ to 10.1 mm and the opening in the gap to 0.9 mm.
[0039]
In the case of the formation of strained Si on SiGe, since it is already formed with strain at the time of deposition (epitaxial growth), the actual size will not increase. become.
[0040]
(Second Embodiment)
Hereinafter, description will be given of a substrate manufacturing method according to a second preferred embodiment of the present invention. The substrate manufacturing method according to the present embodiment is schematically obtained by changing some processes of the substrate manufacturing method according to the first embodiment. FIG. 2 is a diagram showing a substrate manufacturing method according to this embodiment. The steps shown in FIGS. 2A to 2C are the same as the steps shown in FIGS. 1A to 1C.
[0041]
In the step shown in FIG. 2D, the semiconductor layer 13 is etched to form an opening. In the step shown in FIG. 2E, the strain inducing region 14 is formed on the porous layer 12 exposed in the opening. By configuring as described above, the semiconductor layer 13 ′ formed on the porous layer 12 can be efficiently distorted.
[0042]
(Third embodiment)
Hereinafter, a description will be given of a substrate manufacturing method according to a preferred third embodiment of the present invention. The substrate manufacturing method according to the present embodiment is schematically obtained by changing some processes of the substrate manufacturing method according to the first embodiment. FIG. 3 is a diagram showing a substrate manufacturing method according to this embodiment. The steps shown in FIGS. 3A and 3C are the same as the steps shown in FIGS. 1A and 1C, respectively.
[0043]
In the step shown in FIG. 3B, a porous layer is partially formed on the substrate 11. As a method for forming the porous layer, when anodization is employed, for example, a protective film (for example, a nitride film or HF resistance) that protects the substrate from a chemical solution (hydrofluoric acid or the like) used in anodization. After forming the mask) on the substrate 11, the substrate 11 is anodized to form a partial porous layer 12 ″ shown in FIG. In the step shown in FIG. 3D, the semiconductor layer 13 is etched to form an opening. In the step shown in FIG. 3E, the strain induction region 14 is formed on the substrate 11 exposed in the opening. By configuring as described above, the semiconductor layer 13 ′ formed on the porous layer 12 can be efficiently distorted.
[0044]
[First application example of semiconductor substrate]
In this application example, a semiconductor device manufacturing method using a semiconductor substrate that can be manufactured by applying the substrate manufacturing method according to any one of the first to third embodiments of the present invention will be described.
[0045]
FIG. 4 shows the vicinity of the semiconductor layer 13 ′ and the strain-inducing region 14 of the substrate manufactured by the process shown in the second embodiment exemplarily among the preferred first to third embodiments of the present invention. Is. First, an element isolation region 54 and a gate insulating film 56 are formed on the surfaces of the semiconductor layers 13 and 13 ′ (see FIG. 4A). Examples of the material of the gate insulating film 56 include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, titanium oxide, scandium oxide, yttrium oxide, gadolinium oxide, lanthanum oxide, zirconium oxide, and the like. The glass mixture is suitable. The gate oxide film 56 can be formed, for example, by oxidizing the surface of the semiconductor layers 13 and 13 ′ or depositing a corresponding material on the surfaces of the semiconductor layers 13 and 13 ′ by the CVD method or the PVD method.
[0046]
Next, a gate electrode 55 is formed on the gate insulating film 56. The gate electrode 55 is made of, for example, polycrystalline silicon doped with a P-type or N-type impurity, a metal such as tungsten, molybdenum, titanium, tantalum, aluminum, or copper, or an alloy containing at least one of these, molybdenum silicide, It can be composed of a metal silicide such as tungsten silicide or cobalt silicide, or a metal nitride such as titanium nitride, tungsten nitride, or tantalum nitride. The gate insulating film 56 may be formed by stacking a plurality of layers made of different materials, such as a polycide gate. The gate electrode 55 may be formed by, for example, a method called salicide (self-aligned silicide), a method called a damascene gate process, or another method. The structure shown in FIG. 4A is obtained through the above steps.
[0047]
Next, N-type impurities such as phosphorus, arsenic, and antimony or P-type impurities such as boron are introduced into the semiconductor layers 13 and 13 ′, thereby forming relatively low concentration source and drain regions 58 (FIG. 4B). )). Impurities can be introduced, for example, by ion implantation and heat treatment.
[0048]
Next, after forming an insulating film so as to cover the gate electrode 55, the insulating film is etched back, thereby forming the sidewall 59 on the side portion of the gate electrode 59.
[0049]
Next, impurities having the same conductivity type as those described above are again introduced into the semiconductor layers 13 and 13 ′ to form relatively high concentration source / drain regions 57. The structure shown in FIG. 4B is obtained through the above steps.
[0050]
Next, a metal silicide layer 60 is formed on the upper surface of the gate electrode 55 and the upper surfaces of the source and drain regions 57 (see FIG. 4C). As a material of the metal silicide layer 60, for example, nickel silicide, titanium silicide, cobalt silicide, molybdenum silicide, tungsten silicide and the like are suitable. These silicides are formed by depositing a metal so as to cover the upper surface of the gate electrode 55 and the upper surfaces of the source and drain regions 57, and then performing a heat treatment to cause the metal to react with the underlying silicon. The unreacted portion of the metal can be removed with an etchant such as sulfuric acid. Here, if necessary, the surface of the silicide layer may be nitrided. The structure shown in FIG. 4C is obtained through the above steps.
[0051]
Next, an insulating film 61 is formed so as to cover the upper surface of the silicided gate electrode and the upper surfaces of the source and drain regions (see FIG. 4D). As a material of the insulating film 61, silicon oxide containing phosphorus and / or boron is preferable.
[0052]
Next, if necessary, a contact hole is formed in the insulating film 61 after planarizing the surface by CMP (chemical mechanical polishing). KrF excimer laser, ArF excimer laser, F ₂ When a photolithographic technique using an excimer laser, electron beam, X-ray or the like is applied, a rectangular contact hole having a side of less than 0.25 microns or a circular contact hole having a diameter of less than 0.25 microns is formed. Can do.
[0053]
Next, a conductor is filled in the contact hole. As a method for filling the conductor, after forming a film of a refractory metal serving as the barrier metal 62 or a nitride thereof on the inner wall of the contact hole, the conductor 63 such as tungsten alloy, aluminum, aluminum alloy, copper, or copper alloy is formed. A deposition method using a CVD method, a PVD (physical vapor deposition) method, a plating method, or the like is preferable. Here, the conductor deposited higher than the upper surface of the insulating film 61 may be removed by an etch back method or a CMP method. Prior to filling the conductor, the surface of the silicide layer in the source and drain regions exposed at the bottom of the contact hole may be nitrided. Through the above steps, a transistor such as a field effect transistor (FET) can be formed on the substrate, and a semiconductor device having a transistor having the structure shown in FIG. 4D can be obtained.
[0054]
As described above, according to the present embodiment, the semiconductor layer can be efficiently distorted and the carrier mobility of the semiconductor layer can be improved, so that a device such as a transistor formed in the semiconductor layer can be driven at high speed. Can be made.
[0055]
[Second application example of semiconductor substrate]
In this application example, the semiconductor device manufactured by the first application example of the semiconductor substrate is further improved. In this application example, as the gate electrode 55 formed on the surface of the semiconductor layers 13 and 13 ′ according to the first application example of the semiconductor substrate, a gate electrode 55 that extends in a substantially horizontal direction is used. Further, the semiconductor layers 13 and 13 ′ can be distorted. As such a gate electrode 55, for example, a gate electrode 55 that has been subjected to heat treatment after ion implantation can be employed.
[0056]
In this case, as the strain induction region 14, it is desirable to use a material that applies a tensile force to the island-shaped semiconductor layers 13 and 13 ′, but such a material is not necessarily used. Various materials (that is, not necessarily a material that gives a tensile force to the semiconductor layers 13 and 13 ′) and configurations that are optimized in accordance with element isolation characteristics can be employed.
[0057]
Further, by forming an interlayer insulating film on the surfaces of the semiconductor layers 13 and 13 ′ and controlling the stress caused thereby, it is possible to further apply stress to the semiconductor layers 13 and 13 ′.
【Example】
Preferred examples of the present invention will be given below.
[0058]
(Example 1)
An 8-inch P-type silicon wafer 11 (resistivity 0.013 to 0.017 Ω-cm) was prepared (corresponding to FIG. 1A), and porous silicon 12 was formed on the surface thereof by anodization ( Corresponding to FIG. Here, the anodizing solution is 50% HF: IPA = 2: 1 (volume ratio), and the current density is 8 mA / cm. ² The current application time was 11 min, and the film thickness of the porous silicon 12 was 10 μm. After anodization, the silicon wafer 11 was oxidized at 400 ° C. for 1 hour in oxygen at a low temperature, and then the surface oxide film was removed with DHF or the like and loaded into an epitaxial apparatus. After loading into the epitaxial apparatus, the silicon wafer 11 was subjected to surface treatment at 950 ° C. for 10 seconds in a hydrogen atmosphere to fill the surface holes. Furthermore, a small amount of silicon-based gas was introduced to fill the remaining surface holes. Thereafter, silicon was epitaxially grown on the silicon wafer 11 to form an epitaxial silicon layer 13 having a predetermined thickness (corresponding to FIG. 1C). The film thickness of the epitaxial silicon layer 13 was determined according to the device to be manufactured, and could be controlled over a wide range from about 10 nm to several μm.
[0059]
Next, a protective oxide film is formed on the surface of the epitaxial silicon layer 13, and patterning and etching are performed in a lithography process, thereby patterning the epitaxial silicon layer 13 and the porous silicon 12 thereunder into an island shape (FIG. 1D). )). The size and shape of the island was determined by the device to be manufactured. The size of the island could be controlled from 1 μm to several hundred μm.
[0060]
After the silicon is etched off, TEOS + O is formed in the gap between the island-shaped epitaxial silicon layer 13 ′ and the porous silicon 12 ′. ₃ An oxide film 14 was formed by a CVD method using as a raw material (corresponding to FIG. 1E). Since the stress of the silicon oxide film can be controlled in a high range, conditions were set so that a tensile force was applied to the sidewalls of the epitaxial silicon layer 13 ′ and the porous silicon 12 ′ formed in an island shape. .
[0061]
As described above, the silicon semiconductor layer 13 ′ on the surface could be distorted.
[0062]
(Example 2)
In the present embodiment, a part of the steps in Embodiment 1 is schematically changed. That is, in this embodiment, instead of patterning the epitaxial silicon layer 13 and the underlying porous silicon 12 by forming a protective oxide film on the surface of the epitaxial silicon layer 13 and performing patterning and etching in a lithography process, The epitaxial silicon layer 12 was patterned into an island shape (corresponding to FIG. 2D).
[0063]
Example 3
In the present embodiment, a part of the steps in Embodiment 1 is schematically changed. That is, in this example, a porous silicon layer 12 '' was partially formed on the silicon wafer 11 (corresponding to FIG. 3B). As a method of selectively anodizing silicon in order to partially form the porous silicon layer 12 ″ in this way, for example, (1) boron is ion-implanted into a region where silicon is made porous. (2) Patterning an HF-resistant insulating protective film on silicon to cover the surface other than the region to be selectively made porous.
[0064]
(Example 4)
In contrast to Examples 1 to 3, a CMOS (complementary metal-oxide semiconductor) structure was formed in an island shape on the surface silicon (corresponding to FIG. 4). The CMOS was formed by a general method. It was confirmed that the electron mobility and hole mobility of the N-type and P-type MOS transistors were increased with respect to the unstrained one.
[0065]
(Example 5)
A method of applying strain to the silicon semiconductor layer was further applied to Example 4. Specifically, arsenic was implanted into the gate electrode 55 immediately above the channel, and a gate protective film was formed so as to surround the gate. After that, annealing is performed, and local strain is generated in the channel region using the expansion and contraction of the gate electrode 55 and the gate protective film, in addition to the tensile force in the material that applies the tensile force between the island-shaped silicons. The semiconductor layers 13, 13 ′ could be efficiently distorted by applying stress from directly above the gate. Further, by disposing the porous silicon 12 and 12 ′ having a lower Young's modulus than the semiconductor layers 13 and 13 ′ under the semiconductor layers 13 and 13 ′, the surface silicon semiconductor layers 13 and 13 ′ are more effectively distorted. I was able to do it.
[0066]
In Examples 1 to 5 shown above, the conditions for forming porous silicon are not limited to the above conditions. In order to change the porosity, the substrate type (P type, N type), specific resistance, solution concentration, current, temperature, etc. can be changed. As a method for epitaxially growing silicon on porous silicon, various methods such as a CVD method, an MBE (molecular beam epitaxy) method, a sputtering method, and a liquid phase growth method can be employed. Further, the other steps can be carried out under various conditions as well as the conditions limited to the embodiment described here.
[0067]
【The invention's effect】
According to the present invention, for example, the semiconductor layer can be efficiently distorted.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a substrate manufacturing method according to a preferred first embodiment of the present invention.
FIG. 2 is a view for explaining a substrate manufacturing method according to a preferred second embodiment of the present invention.
FIG. 3 is a view for explaining a substrate manufacturing method according to a preferred third embodiment of the present invention.
FIG. 4 is a diagram for explaining a first application example of a semiconductor substrate according to a preferred embodiment of the present invention.
FIG. 5 is a graph showing the relationship between porosity and Young's modulus.

Claims (15)

A semiconductor layer;
A porous layer supporting the semiconductor layer;
A strain-inducing region that applies stress to the semiconductor layer to cause strain in the semiconductor layer;
A semiconductor substrate comprising: The porous layer and the semiconductor layer include a plurality of island-shaped regions, and the strain-inducing region is formed between the plurality of island-shaped regions. Semiconductor substrate. 2. The semiconductor substrate according to claim 1, wherein the semiconductor layer includes a plurality of island-shaped semiconductor regions, and the strain induction region is formed between the plurality of island-shaped semiconductor regions. The semiconductor substrate according to any one of claims 1 to 3, wherein the porous layer is a porous silicon layer. The semiconductor substrate according to claim 1, wherein the semiconductor layer is made of single crystal silicon. The semiconductor substrate according to claim 1, wherein the strain induction region is made of silicon oxide. 6. The semiconductor substrate according to claim 1, wherein the strain induction region is made of silicon nitride. The semiconductor device according to claim 1, wherein a semiconductor device is formed in the semiconductor layer. 9. The semiconductor device according to claim 8, further comprising a second strain-inducing region that applies strain to the semiconductor layer to cause strain in the semiconductor layer above the channel of the semiconductor device. Forming a porous layer on the substrate;
Forming a semiconductor layer on the porous layer;
Forming a strain-inducing region that applies stress to the semiconductor layer to cause strain in the semiconductor layer;
A method for producing a semiconductor substrate, comprising: After the step of forming the semiconductor layer, the method further includes a step of partially etching the porous layer and the semiconductor layer to form an opening, and in the step of forming the strain induction region, The method of manufacturing a semiconductor substrate according to claim 10, wherein a strain induction region is formed. After the step of forming the semiconductor layer, the method further includes a step of partially etching the semiconductor layer to form an opening. In the step of forming the strain induction region, the strain induction region is formed in the opening. The method of manufacturing a semiconductor substrate according to claim 10. In the step of forming the porous layer, a plurality of porous regions are formed on the substrate, and in the step of forming the strain induction region, the strain induction region is formed between the semiconductor layers of the plurality of porous regions. The method of manufacturing a semiconductor substrate according to claim 10. Preparing a semiconductor substrate manufactured by applying the manufacturing method according to any one of claims 10 to 13,
Forming a semiconductor device on the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising: The method for manufacturing a semiconductor device according to claim 14, further comprising applying a stress to the semiconductor layer from above the channel of the semiconductor device to further strain the semiconductor layer.

Images