JP2004146472A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving characteristics in a transistor with a strain silicon layer as a channel region by forming the high-quality strain silicon layer, where a crystalline defect is reduced on a silicon germanium layer, and to provide a method for manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device comprises a porous silicon layer 2 formed on the surface of a silicon substrate 1, a first single crystal silicon layer 3 formed on the surface of the porous silicon layer 2, a first silicon germanium layer 5a that is laminated to the first single crystal silicon layer 3 and is set to be in a strain relief state, and a single crystal silicon layer 6a for channels that is laminated to the first silicon germanium layer 5a and is set to be in a strain state becoming a channel region (6ac). <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a strained silicon layer in a strained state formed on a silicon germanium layer, and a method for manufacturing a semiconductor device.
[0002]
[Prior art]
2. Description of the Related Art In a semiconductor device, particularly a CMOS device, low power consumption has been demanded in accordance with a demand for resource saving. The MOS transistor constituting the CMOS device has been able to secure the driving capability by miniaturizing the transistor structure such as the miniaturization of the gate structure and the thinning of the gate film so as to cope with the low voltage operation. However, miniaturization of the transistor structure requires significant technological innovation for each generation, and is expected to further increase the burden on the development side in the future, along with cost investment.
[0003]
From such a background, in a MOS transistor, as a method of securing a driving capability at a low voltage irrespective of the miniaturization of the transistor structure, a fully depleted SOI structure is employed to reduce the S value, and to reduce the driving capability of the transistor. (SOI transistor device) and a method of improving the driving capability of the transistor by employing a strained silicon channel structure using germanium have been proposed.
[0004]
However, since a SOI transistor device requires a completely depleted SOI structure, it is necessary to form a transistor on a thin film SOI layer of about several tens of nm, and a high-precision processing technique more than a bulk transistor process is required. In addition, since the active silicon layer is buried below and surrounded by an oxide film, the surrounding area is surrounded by an element isolation oxide film, so that a well contact cannot be made and the design resources of the bulk device cannot be used as it is.
[0005]
On the other hand, the strained silicon channel structure releases a strain of eutectic Si (hereinafter, SiGe) containing germanium (hereinafter, Ge) having a lattice constant different from that of silicon (hereinafter, Si), and forms a so-called relaxed SiGe layer. A Si layer having a tensile strain is formed thereon, and this is used for the channel of the transistor, thereby improving the driving capability of the transistor. That is, in a strained Si layer having a tensile strain, mobility is improved by lowering the effective mass of electrons and reducing lattice scattering as compared with a non-strained Si layer. This is to improve the driving ability. From the advantage of improved characteristics, many techniques have been proposed in which a strained Si layer is applied to an N-channel MOS transistor.
[0006]
FIG. 9 is a cross-sectional view of a semiconductor device according to Conventional Example 1 having a strained Si layer. For easy understanding, hatching indicating a cross section is omitted (the same applies to other drawings). A SiGe layer 52a having a Ge concentration gradient and a SiGe layer 52b having a fixed concentration of Ge are formed on the Si substrate 51 on which the buried layer 51a is formed, and a lattice mismatch between the Si substrate 51 and the SiGe layers 52a and 52b occurs. The generated lattice strain is released, and a strained Si layer 53 having a small lattice constant is deposited thereon to be used as a strained Si channel. An intermediate layer 54, a gate oxide film 55, and a gate electrode 56 are formed on the Si layer 53, and a source region 57, a drain region 58, and a channel region 53c are defined corresponding to the gate electrode 56 (for example, see Patents). Reference 1).
[0007]
In Conventional Example 1, a Ge concentration gradient is provided to suppress the generation of dislocation at the interface between the Si substrate 51 and the SiGe layers 52a and 52b and to reduce the stress of the SiGe layers 52a and 52b caused by lattice mismatch. The deposited SiGe layer 52a is used. A gentle concentration gradient is required for stress relaxation, and consequently, control on the order of μm is required (the thickness of the SiGe layer 52a is 2 μm). The SiGe layers 52a and 52b to be epitaxially grown have a low deposition rate from the viewpoint of securing single crystallinity, usually about several nm / minute to several tens of nm / minute, and require a long time for the deposition processing during epitaxial growth, and thus require wafer processing. There is a problem that the ability is reduced.
[0008]
FIG. 10 is a cross-sectional view showing a manufacturing process of a semiconductor device according to Conventional Example 2 having a strained Si layer. An SiGe layer 62 is formed on a Si substrate 61 (FIGS. 7A and 7B), but crystal defects 63 remain at the interface. Next, at the interface between the Si substrate 61 and the SiGe layer 62, a first ion implantation of oxygen, nitrogen or the like is performed to form a stopper layer 64 for preventing solid phase growth (FIG. 3C). After that, a second ion implantation of Ge, Si, or the like is performed to amorphize the lower portion of the SiGe layer 62 by a predetermined thickness to form an amorphous SiGe layer 65a (FIG. 4D). Furthermore, the amorphous SiGe layer 65a is converted into a single-crystal SiGe layer 66 with reduced crystal defects by annealing. Subsequently, a third ion implantation of Ge, Si, or the like is performed above the SiGe layer 62, and is amorphousized by annealing, thereby forming an amorphous SiGe layer 65b (FIG. 9E). Further, the amorphous SiGe layer 65b is converted into a single-crystal SiGe layer 66 having good crystallinity by performing a re-annealing process (FIG. 6F). Thereafter, a single-crystal Si layer 67 in a strained state is grown on the single-crystal SiGe layer 66 (for example, see Patent Document 2).
[0009]
That is, in Conventional Example 2, stress control of the SiGe layer is performed by using ion implantation. In this method, ion implantation of relatively large ions and annealing treatment are repeatedly performed on the SiGe layer 62 a plurality of times, thereby performing a state conversion between crystal amorphization and recrystallization. Therefore, not only the manufacturing process becomes complicated, but also a sufficiently high-quality substrate free from crystal defects can be obtained as a substrate finally obtained due to amorphization for conversion of a crystalline state. There is a problem that can not be.
[0010]
As a conventional example 3 in which a strained Si layer is formed using a thin SiGe layer, a relaxed state in which strain has been released by ion implantation of hydrogen into a strained SiGe layer deposited on a Si plane having a (100) plane orientation and annealing treatment. Is known (for example, see Non-Patent Document 1).
[0011]
In Conventional Example 3, threading dislocations (Threading Dislocations) that occur from the Si / SiGe interface toward the substrate surface after the annealing process are present. This threading dislocation is 10 × 10 ⁶ -10 ⁹ / Cm ² This causes a problem that the electrical characteristics of the gate oxide film of the transistor and the junction leakage current of the diffusion layer increase.
[0012]
[Patent Document 1]
JP-A-9-82944
[Patent Document 2]
JP 2001-110725 A
[Non-patent document 1]
H. Trinkaus et al., Strain relaxation mechanism for hydrogen-implanted Si (1-x) Ge (x) / Si (100) heterostructures implanted with hydrogen. x) Ge (x) / Si heterostructure, "Applied Physics Letters", (United States), American Institute of Physics, June 12, 2000. , P. 3552-p. 3554
[0013]
[Problems to be solved by the invention]
As described above, in the conventional method in which a strained silicon layer is formed using a silicon germanium layer, the manufacturing process is complicated, the productivity is reduced due to a longer time, and high quality without crystal defects. There are problems such as the inability to obtain a substrate and the insufficient characteristics of a transistor having a strained silicon layer as a channel region.
[0014]
The present invention has been made in view of such a problem, and by forming a high-quality strained silicon layer with reduced crystal defects on a silicon germanium layer without sacrificing the processing capability of a wafer, An object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device which can improve characteristics of a transistor having a strained silicon layer as a channel region.
[0015]
[Means for Solving the Problems]
A semiconductor device according to the present invention is a semiconductor device in which a single crystal silicon layer in a strained state formed on a silicon germanium layer is used as a channel region of a transistor, and a porous silicon layer formed on a surface of a silicon substrate; A first single crystal silicon layer formed on the surface of the silicon layer; a first silicon germanium layer in a strain relaxed state stacked on the first single crystal silicon layer; and a channel region stacked on the first silicon germanium layer And a single-crystal silicon layer for a channel in a strained state.
[0016]
In the semiconductor device according to the present invention, the first silicon germanium layer has a germanium concentration gradient.
[0017]
A semiconductor device according to the present invention is a semiconductor device in which a single crystal silicon layer in a strained state formed on a silicon germanium layer is used as a channel region of a transistor, and a porous silicon layer formed on a surface of a silicon substrate; A first single crystal silicon layer formed on the surface of the silicon layer, a first silicon germanium layer in a strain relaxed state stacked on the first single crystal silicon layer, and a first buffer layer stacked on the first silicon germanium layer A single crystal silicon layer, a strain-relaxed second silicon germanium layer stacked on the first buffering single crystal silicon layer, and a strained channel single crystal silicon layer stacked on the second silicon germanium layer. It is characterized by having.
[0018]
A semiconductor device according to the present invention includes a second buffer single crystal silicon layer laminated between the first buffer single crystal silicon layer and the second silicon germanium layer.
[0019]
A semiconductor device according to the present invention includes a first single crystal silicon layer and a second single crystal silicon layer laminated between the first silicon germanium layer.
[0020]
In the semiconductor device according to the present invention, the thickness of the first single-crystal silicon layer or the stacked thickness of the first single-crystal silicon layer and the second single-crystal silicon layer is 5 nm to 190 nm.
[0021]
In the semiconductor device according to the present invention, the first silicon germanium layer has a thickness of 10 nm to 500 nm.
[0022]
In the semiconductor device according to the present invention, the first silicon germanium layer or the second silicon germanium layer has a germanium concentration of 10 to 50 atomic%.
[0023]
The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a transistor having a strained single crystal silicon layer formed on a silicon germanium layer as a channel region is formed, wherein a porous silicon layer is formed on the surface of the silicon substrate. And a step of converting the surface of the porous silicon into a first single-crystal silicon layer by a hydrogen annealing treatment, and sequentially forming a second single-crystal silicon layer and a first silicon-germanium layer on the first single-crystal silicon layer. A step of epitaxially growing, a step of epitaxially growing a single-crystal silicon layer for a channel on the first silicon-germanium layer, and ion implantation and annealing after the ion implantation to form a second single-crystal silicon layer in the first single-crystal silicon layer. Introducing a crystal defect into the layer or into the porous silicon layer. And wherein the door.
[0024]
In the method of manufacturing a semiconductor device according to the present invention, the first silicon germanium layer is formed with a germanium concentration gradient.
[0025]
The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a transistor having a strained single crystal silicon layer formed on a silicon germanium layer as a channel region is formed, wherein a porous silicon layer is formed on the surface of the silicon substrate. And a step of converting the surface of the porous silicon into a first single-crystal silicon layer by a hydrogen annealing treatment; and, over the first single-crystal silicon layer, a second single-crystal silicon layer, a first silicon-germanium layer, and The step of sequentially epitaxially growing the first buffer single crystal silicon layer, the ion implantation and the annealing after the ion implantation, allow the crystal to be formed in the first single crystal silicon layer, the second single crystal silicon layer, or the porous silicon layer. Introducing a defect, and forming a second buffer single crystal silicon layer and a second silicon layer on the first buffer single crystal silicon layer. Characterized in that it comprises germanium layer, and epitaxially growing a single-crystal silicon layer channel.
[0026]
In the method of manufacturing a semiconductor device according to the present invention, a step of epitaxially growing the second buffer single crystal silicon layer is omitted.
[0027]
In the semiconductor device manufacturing method according to the present invention, the second silicon germanium layer is epitaxially grown as a layer in a strain relaxed state.
[0028]
In the method of manufacturing a semiconductor device according to the present invention, the single crystal silicon layer for a channel is epitaxially grown as a strained layer.
[0029]
The semiconductor device manufacturing method according to the present invention is characterized in that a step of epitaxially growing the second single crystal silicon layer is omitted.
[0030]
In the method for manufacturing a semiconductor device according to the present invention, the thickness of the first single-crystal silicon layer or the stacked thickness of the first single-crystal silicon layer and the second single-crystal silicon layer is 5 nm to 190 nm.
[0031]
In the method for manufacturing a semiconductor device according to the present invention, the first silicon germanium layer is formed to have a thickness equal to or less than a critical thickness.
[0032]
In the method for manufacturing a semiconductor device according to the present invention, the first silicon germanium layer has a thickness of 10 nm to 500 nm.
[0033]
In the method of manufacturing a semiconductor device according to the present invention, the first silicon germanium layer or the second silicon germanium layer has a germanium concentration of 10 to 50 atomic%.
[0034]
In the method of manufacturing a semiconductor device according to the present invention, a growth temperature when the first silicon germanium layer or the second silicon germanium layer is epitaxially grown is 700 ° C. or less.
[0035]
In the method of manufacturing a semiconductor device according to the present invention, the ion species used for ion implantation is hydrogen or helium.
[0036]
In the semiconductor device manufacturing method according to the present invention, the average implantation range of the ion implantation is in any one of the porous silicon layer, the first single crystal silicon layer, and the second single crystal silicon layer. I do.
[0037]
In the method of manufacturing a semiconductor device according to the present invention, the ion implantation is performed in a plurality of times.
[0038]
In the semiconductor device manufacturing method according to the present invention, the ion implantation amount in the ion implantation is 0.3 to 3 × 10 ¹⁶ / Cm ² And a value selected from the range.
[0039]
In the method for manufacturing a semiconductor device according to the present invention, the temperature in the annealing treatment after the ion implantation is set in a range of 600 ° C. to 950 ° C.
[0040]
According to the present invention, a porous silicon layer is formed on a surface of a silicon substrate, and a region from the porous silicon layer to the first single crystal silicon layer and the second single crystal silicon layer formed on the surface of the porous silicon layer. By introducing a crystal defect into the first silicon germanium layer, the first silicon germanium layer formed by being stacked on the first single crystal silicon layer and the second single crystal silicon layer can be in a relaxed state with few crystal defects. A semiconductor device and a method for manufacturing a semiconductor device, in which a strained silicon layer formed by stacking over a layer is used as a strain channel region with few crystal defects, can be provided.
[0041]
According to the present invention, a porous silicon layer formed on a surface of a silicon substrate, a first single crystal silicon layer and a second single crystal silicon layer formed on a surface of the porous silicon layer, A first buffer single-crystal silicon layer and a second buffer single-crystal silicon layer between a first silicon germanium layer and a second silicon germanium layer formed by laminating on the second monocrystalline silicon layer By doing so, the second silicon germanium layer can be in a relaxed state with few crystal defects, so that a strained silicon layer formed by being stacked on the second silicon germanium layer is used as a strain channel region with few crystal defects. A device manufacturing method becomes possible.
[0042]
According to the present invention, a silicon germanium layer having few crystal defects can be formed by a simple process change of forming a porous silicon layer and a change of a substrate structure. A semiconductor device having a strain channel region with few defects and a semiconductor device manufacturing method can be provided.
[0043]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described with reference to the drawings showing the embodiments.
<Embodiment 1>
1 to 3 are cross-sectional views illustrating a process of manufacturing the semiconductor device according to the first embodiment of the present invention. Note that the branch numbers (af) in each figure are given throughout FIGS. Reference numeral 1 denotes a silicon (hereinafter, Si) substrate on which a porous Si layer 2 having a hole 2a is formed by a known anodizing technique. For example, a 750 μm thick Si substrate 1 is prepared, and hydrofluoric acid (HF): pure water (H ₂ O): ethanol (C ₂ H ₅ OH) was adjusted to a current density of 30 mA / cm using a conversion solution adjusted to 1: 1: 1. ² In this case, a porous Si layer 2 having a thickness of 20 to 50 μm and a porosity of 30 to 50% is obtained (FIG. 1A). As for the internal structure of the porous Si layer 2, countless formed fine pores having a diameter of several nm are distributed in a honeycomb shape or a sponge shape. Here, the fine holes are schematically shown as the holes 2a, and the shape is not necessarily vertical.
[0044]
By treating the Si substrate 1 on which the porous Si layer 2 is deposited in a hydrogen atmosphere at a temperature of 1000 ° C. for one hour, Si atoms in the vicinity of the surface of the porous Si layer 2 are migrated to fill holes localized on the surface. This converts the surface portion of the porous Si layer 2 into the first single-crystal Si layer 3 (FIG. 1B). The thickness of the first single-crystal Si layer 3 depends on the hydrogen annealing time and the porosity of the porous Si layer 2, but is generally about several nm to 1 μm. Here, as an example, the thickness of the first single-crystal Si layer 3 was set to 50 nm.
[0045]
Using a commonly used CVD method, a second single-crystal Si layer 4 is deposited on the first single-crystal Si layer 3 by epitaxial growth at a temperature of 600 ° C. to 1100 ° C. (FIG. 1B). The laminated film thickness of the first single-crystal Si layer 3 and the second single-crystal Si layer 4 is preferably about 5 nm to 190 nm in order to sufficiently relax the strained first SiGe layer 5 deposited in a later step. Here, as an example, the thickness of the second single-crystal Si layer 4 was 5 nm.
[0046]
The formation of the second single-crystal Si layer 4 can be omitted in the following cases. For example, when the Ge concentration of the first SiGe layer 5 having a concentration gradient is as low as about 15% or less, or when the thickness of the first SiGe layer 5 is as small as about 100 nm or less, the strain ion implantation energy of the first SiGe layer 5 is reduced. In order to reduce the first SiGe layer 5 efficiently, it is preferable that the second single crystal Si layer 4 deposited directly on the first single crystal Si layer 3 be as thin as possible or not. Further, the implantation range (Rp) of the ion implantation (FIG. 2D) described later is made deeper to increase the distance from the crystal defect (region) caused by hydrogen implantation in the porous Si layer 2 to the first SiGe layer 5. In order to reduce the leakage current, the distance from the crystal defect to the first SiGe layer 5 increases, so that the second single-crystal Si layer 4 is preferably as thin or as thin as possible.
[0047]
Using the above-mentioned CVD method, a first SiGe layer 5 having a concentration gradient and a single crystal Si layer 6 for a channel are sequentially deposited and formed on the second single crystal Si layer 4 by epitaxial growth (FIG. 1C). Generally, Ge (layer) deposited on Si (layer) has about 4% lattice mismatch, and is deposited on first single crystal Si layer 3 and second single crystal Si layer 4. The first SiGe layer 5 also has a compressive stress due to lattice mismatch. At this time, the first SiGe layer 5 has a strain (strain energy) caused by a difference in lattice constant (lattice mismatch) from the underlying Si (the first single crystal Si layer 3 and the second single crystal Si layer 4). It is important that the film is deposited in a strained state including the film thickness, and it is necessary to deposit the film at a film thickness equal to or less than a critical film thickness determined from the deposition temperature and the Ge concentration. The critical film thickness is a maximum film thickness capable of maintaining a strain state based on a difference in lattice constant in a stacked structure of atoms having different lattice constants (in other words, a minimum film thickness necessary for releasing strain (strain energy)). Thickness). The thickness of the first SiGe layer 5 in the strained state cannot be specified unconditionally, but can be specified by appropriately setting film forming conditions (deposition temperature, Ge concentration, and deposited film thickness). The temperature is preferably set to 700 ° C. or less in consideration of properties and the like.
[0048]
That is, when a film thickness exceeding the critical film thickness is deposited, the strain (strain energy) of the first SiGe layer 5 is released during the deposition, so that the strain cannot be set. When a film thickness exceeding the critical film thickness is deposited, misfit dislocation due to stress release occurs at the interface between the first single crystal Si layer 3 and the second single crystal Si layer 4 and the first SiGe layer 5, Cross-hatched dislocation lines are generated on the surface of the first SiGe layer 5. In this case, the crystal quality of the channel single crystal Si layer 6 deposited immediately above is degraded due to the cross hatch dislocation lines. From these viewpoints, it is preferable that the first SiGe layer 5 has an effective thickness of about 10 to 500 nm.
[0049]
Note that the Ge concentration in the first SiGe layer 5 is preferably in the range of 10 to 50 atomic% from the viewpoint of easy realization of a strain state. Further, Ge in the first SiGe layer 5 may be deposited so as to have a concentration gradient. That is, any of a so-called BOX type (without concentration gradient) and a GRADED type (with concentration gradient) may be used. The thickness of the first SiGe layer 5 can be appropriately selected within a range of 10 to 500 nm and a Ge concentration of 10 to 50 atomic% when a Ge concentration gradient is provided.
[0050]
Here, as an example, the first SiGe layer 5 was deposited to a thickness of 250 nm, and the channel single crystal Si layer 6 was deposited to a thickness of 20 nm. The first SiGe layer 5 has an initial Ge concentration of 20 atom% (on the first single crystal Si layer 3 and the second single crystal Si layer 4 side) and a final Ge concentration of 30 atom (on the channel single crystal Si layer 6 side). % Was obtained. The strained first SiGe layer 5 is deposited so as to include the strain. Since the strain must be released in the subsequent steps, the Ge concentration gradient is such that the initial Ge concentration at the time of deposition is about 10 to 20%. The final Ge concentration is preferably about 30 to 50%.
[0051]
Next, hydrogen ions are ion-implanted near the surface of the porous Si layer 2 through the first single-crystal Si layer 3, the second single-crystal Si layer 4, the first SiGe layer 5, and the single-crystal Si layer 6 for the channel ( Arrow H). From the results of the studies so far, it has been found that it is effective to set the implantation range (Rp) on the Si substrate 1 side deeper than the interface between the second single-crystal Si layer 4 and the first SiGe layer 5. . The hydrogen ions in the stopped state after the ion implantation are schematically represented as implanted hydrogen ions 7 (FIG. 2D). Here, as an example, the ion implantation energy was controlled so that the average implantation range Rp was provided in the porous Si layer 2.
[0052]
Helium other than hydrogen is preferable as the ion species to be implanted. These elements have an atomic number of 1 or 2 and are very small ions having a very small ionic radius and a small mass. Therefore, in the first SiGe layer 5 through which the ions pass, almost no nuclear stopping power is exerted, and crystal defects are caused. Is not introduced, the nucleus stopping power becomes maximum immediately before the implantation range (Rp) where ions stop, and fine crystal defects (embedded crystal defects) are introduced near the implantation range (Rp). . Therefore, the first SiGe layer 5 on the surface side of the ion-implanted material (the porous Si layer 2, the first single-crystal Si layer 3, the second single-crystal Si layer 4, the first SiGe layer 5, and the single-crystal Si layer 6 for the channel). In the vicinity of the average implantation range Rp set in the porous Si layer 2, the first single-crystal Si layer 3, and the second single-crystal Si layer 4, without destroying the crystallinity of the channel single-crystal Si layer 6. Fine crystal defects can be introduced. Further, since hydrogen and helium are rare gases, there is no fear of affecting the electrical characteristics of the Si device.
[0053]
Here, as an example, hydrogen ions were implanted at an ion implantation energy of 30 keV. Under these ion implantation conditions, the average implantation range Rp is at a position at a depth of 80 nm from the interface (misfit interface) between the first SiGe layer 5 and the second single crystal Si layer 4 containing the strain to the Si substrate 1 side. . That is, the hydrogen ions pass through the second single-crystal Si layer 4 having a thickness of 5 nm and the first single-crystal Si layer 3 having a thickness of 50 nm, and have a depth of 25 nm from the interface between the first single-crystal Si layer 3 and the porous Si layer 2. Stop in the layer of the porous Si layer 2. Immediately before hydrogen ions stop, the nucleus stopping power of the ion-implanted material (porous Si layer 2) is maximized, and embedded crystal defects (1) such as point defects are located in a region slightly shallower than the implantation range (Rp). Secondary crystal defects).
[0054]
Thereafter, annealing is performed at a temperature of 800 ° C. for 10 minutes under an inert atmosphere such as argon or a hydrogen atmosphere, and a void 8 caused by implanted hydrogen ions 7 is grown near an implantation range (Rp). Further, crystal defects 9 are generated (FIG. 2E). It is considered that the void 8 grows when hydrogen is captured by a dangling bond of Si, which is a crystal defect caused by ion implantation, and a Si—H bond is formed. The crystal defect 9 includes a dislocation line 9a and a dislocation loop / stacking defect 9b caused by the void 8, a dislocation line 9c and a dislocation loop / stacking defect 9d caused by the hole 2a, the second single crystal Si layer 4 and the Threading dislocations 9e and dislocation loops 9f newly growing from the misfit interface with the 1SiGe layer 5a are included. It has been confirmed that the dislocation lines 9a and the dislocation loops / stacking faults 9b extend over the first SiGe layer 5, and the dislocation lines 9a and the dislocation loops / stacking faults 9b extending on the first SiGe layer 5 increase. Thus, it is known that the junction leakage current of a MOS transistor formed in a later step increases. From this, the position of the buried crystal defect is set within a predetermined range from the first SiGe layer 5 to the Si substrate 1 (a depth of 190 nm from the interface between the first SiGe layer 5 and the second single crystal Si layer 4 to the Si substrate 1). By setting the thickness to about 200 nm, it is necessary to reduce the number of crystal defects 9 extending to the first SiGe layer 5. Note that a correlation was found between the position of the embedded crystal defect (secondary crystal defect) formed by the annealing treatment after the ion implantation and the crystal defect in the first SiGe layer 5.
[0055]
Here, the relationship between the ion implantation and the crystal defect (9) will be further described. The implanted hydrogen ions are gradually ionized by the electron cloud around the Si nuclei constituting the crystal lattice of the Si crystal (porous Si layer 2, first single crystal Si layer 3, second single crystal Si layer 4). Loss the injection energy (electron stopping power). Immediately before stopping, the hydrogen ions collide with Si nuclei forming a crystal lattice (nucleus stopping power) and stop. At this time, the hydrogen ions destroy the crystal lattice of the Si crystal immediately before the implantation range (Rp) at which the nuclear stopping power is maximized (lattice damage), so that buried crystal defects (primary crystal defects) are introduced. When the implanted ions are hydrogen, the degree of this lattice damage is small because the ion radius is small and light ions, and mainly point defects of lattice vacancies blown off by collision of Si at lattice positions or covalent bond of Si-Si bond. Becomes a crystal defect in the form of a partially cut Si dangling bond or the like (primary crystal defect). When annealing is performed in this state, some of the primary crystal defects recover crystallinity, and the remaining crystal defects become secondary crystal defects (voids 8 and crystal defects 9). Immediately after implantation, the implanted hydrogen ions 7 are dispersed in the Si crystal as interstitial atoms, but are bonded to surrounding Si dangling bonds (primary crystal defects) by annealing to form Si-H bonds. Since there are many primary crystal defects near the implantation range (Rp), a Si crystal lattice having many Si—H bonds is formed after the annealing process. When the ion implantation amount is large and the density of Si—H bonds is large, voids 8 are formed due to repulsion of hydrogen of Si—H and H—Si that have faced each other (assuming the reverse of hydrogen bonds). It has been confirmed by a transmission electron microscope that the amount of buried crystal defects increases or decreases due to the increase or decrease in the amount of ion implantation when performing ion implantation.
[0056]
The formation of the voids 8 is completed at an early stage of the annealing process, and stress is introduced into the porous Si layer 2 by the formation of the voids 8. Although a compressive stress is acting on the first SiGe layer 5 containing the strain, dislocation lines 9a as secondary crystal defects are formed so that the mutual stress is released by the interaction with the stress caused by the void 8. And a dislocation loop / stacking fault 9b is formed. That is, the compressive stress (strain ion implantation energy) of the first SiGe layer 5 is released due to the secondary crystal defect, and the first SiGe layer 5 becomes the relaxed first SiGe layer 5a in which the strain is relaxed (FIG. 2E). ).
[0057]
The relationship between the ion implantation amount (hydrogen ion implantation amount) and the presence or absence of the porous Si layer 2 (effect of the porous Si layer 2) will be described. In order to suppress the amount of buried crystal defects (primary crystal defects, and hence secondary crystal defects), it is effective to reduce the amount of ion implantation. However, if the amount of ion implantation is reduced, the first SiGe is subjected to a subsequent annealing process. Since the state where the layer 5 is not sufficiently relaxed is caused, the range of the ion implantation amount is limited. This range varies depending on the type of ion to be implanted, the ion implantation energy, or the annealing temperature, but is approximately 1.0 to 3 × 10 ¹⁶ / Cm ² Degree (10 ¹⁶ / Cm ² First half of the level). In the case where the porous Si layer 2 is not used, the amount of implanted hydrogen ions required to convert the first SiGe layer 5 containing the strain into the relaxed first SiGe layer 5a in which the strain is relaxed is generally about 1.0. ~ 3 × 10 ¹⁶ / Cm ² (For example, Non-Patent Document 1 discloses that a SiGe layer having a thickness of 250 nm and a Ge concentration of 15 at% is implanted with hydrogen ions at an ion implantation energy of 25 keV and an ion implantation amount of 3 × 10 3 ¹⁶ / Cm ² An example in which ion implantation is performed under the conditions described above is disclosed. ). In addition, the ion implantation amount is set to 10 ¹⁶ / Cm ² In the latter half of the level, the SOI technology can be applied, and the separation phenomenon of the substrate is likely to occur with the implanted layer due to hydrogen ions as a separation boundary, so that it cannot be applied to the present invention.
[0058]
Ion implantation amount is 1.0-3 × 10 ¹⁶ / Cm ² If it is larger than the range, a huge hydrogen void (referred to as Blistering) is generated, and the peripheral portion of the injection range (Rp) becomes blistered. On the contrary, the ion implantation amount is 1.0 to 3 × 10 ¹⁶ / Cm ² Is smaller than the range, the first SiGe layer 5 containing the strain is relaxed halfway, and cross-hatched threading dislocations are generated in the first SiGe layer 5. However, by adopting the porous Si layer 2, the ion implantation amount is reduced to 0.3 × 10 ¹⁶ / Cm ² It is possible to reliably prevent the generation of huge hydrogen voids and shorten the time required for ion implantation.
[0059]
As described above, the reason why the ion implantation amount can be reduced is that the first single crystal Si layer 3 immediately above is partially separated from the Si substrate 1 by the introduced porous Si layer 2, and furthermore, Although the amount of crystal defects caused by the implanted hydrogen ions 7 (voids 8) decreases with the decrease in the ion implantation amount, the secondary defects caused by the stress from the holes 2a of the porous Si layer 2 not caused by the voids 8 It is presumed that the generation of dislocation lines 9c and dislocation loops / stacking faults 9d as crystal defects supplement and promote the relaxation of the first SiGe layer 5 including the strain. That is, the porous Si layer 2 is introduced in order to reduce the amount of secondary crystal defects due to ion implantation, while relaxing the strained first SiGe layer 5. By introducing the porous Si layer 2, the activation energy for relaxing the stress of the strained first SiGe layer 5 is relatively reduced, and the first SiGe layer 5 can be formed under the ion implantation conditions in which the ion implantation amount is reduced. Can be relaxed. Since the amount of secondary crystal defects due to ion implantation is reduced, a junction leakage current of a MOS transistor described later can be reduced.
[0060]
As described above, by adopting the porous Si layer 2, the amount of ion implantation can be reduced, and in addition to shortening the ion implantation processing time, crystal defects (dislocations) extending to the relaxed first SiGe layer 5a in which the strain is relaxed. The line 9a and the dislocation loop / stacking fault 9b) can be relatively reduced. In addition, the range of the applicable ion implantation amount is 1.0 to 3 × 10 ¹⁶ / Cm ² From 0.3 to 3 × 10 ¹⁶ / Cm ² And the degree of freedom of control increases.
[0061]
As described above, the crystal defects (9a to 9d) extending from the buried crystal defects in the ion-implanted region (the void 8 and its periphery) may extend to the surface of the first SiGe layer 5a and grow into threading dislocations 9e. However, by providing the first SiGe layer 5a with a concentration gradient, the crystal defects (dislocation lines) to be extended into the first SiGe layer 5a are caused by the lattice mismatch stress difference corresponding to the Ge concentration gradient. Bending dislocation loops / stacking faults 9b and 9d on the way. Further, the dislocation loop 9f which is about to grow from the misfit interface between the second single crystal Si layer 4 and the first SiGe layer 5a does not extend for the same reason. Therefore, threading dislocations 9e penetrating through first SiGe layer 5a having a concentration gradient are substantially not present. The threading dislocations 9e and the dislocation loops 9f are indicated by broken lines in the figure to indicate that they hardly exist (the same applies to the second embodiment).
[0062]
The case where the average implantation range Rp is within the layer of the porous Si layer 2 has been described. However, the implantation range (Rp) is determined based on the interface between the second single crystal Si layer 4 and the first SiGe layer 5. The side may be set so as to be within the range of the porous Si layer 2. At this time, the ion implantation energy is set so that the implantation range (Rp) falls within a range from the interface between the first SiGe layer 5 and the second single-crystal Si layer 4 to a depth of about 190 nm to 200 nm toward the Si substrate 1. By setting, the transformation of the first SiGe layer 5 to the first SiGe layer 5a in the relaxed state in which the strain is relaxed can be promoted.
[0063]
The experimental results show that when ion implantation energy exceeding a depth of about 190 nm to 200 nm from the interface between the first SiGe layer 5 and the second single-crystal Si layer 4 to the Si substrate 1 side is used, a strain including strain is included. It was confirmed that the 1SiGe layer 5 was relaxed halfway and the generation of cross-hatch dislocations could not be suppressed. This is because the distance between the void 8 and the misfit interface in the first single-crystal Si layer 3 / second single-crystal Si layer 4 / first SiGe layer 5 is too large, and the compressive stress acting on the first SiGe layer 5 This can be explained by the decrease in the interaction with the stress caused by No. 8.
[0064]
When the implantation range (Rp) uses a low ion implantation energy such as that generated in the layer of the first SiGe layer 5, the first SiGe layer 5 containing the strain is relaxed, but the ion implantation is caused by the ion implantation. A large number of crystal defects (9) are introduced into the relaxed first SiGe layer 5a, which causes a problem of deterioration of device characteristics such as an increase in junction leak current.
[0065]
Further, the annealing (relaxation annealing) temperature is practically effective at 600 ° C. to 950 ° C., preferably 800 ° C. to 900 ° C. At a temperature of 600 ° C. or less, the growth of the void 8 is insufficient. At a temperature of 600 ° C. to 800 ° C., many small voids 8 insufficiently grown were observed, and the amount of crystal defects 9 (dislocation lines 9a and dislocation loops / stacking faults 9b) was suppressed. . Conversely, at a temperature of 950 ° C. or higher, Ge diffuses from the first SiGe layer 5a into the single-crystal Si layer for channel 6a, causing deterioration of device (MOS transistor) characteristics.
[0066]
Further, the ion implantation can be divided into a plurality of times. Crystal defects due to ion implantation are introduced at positions immediately before the implantation range (Rp). In order to efficiently relieve the first SiGe layer 5 having the strain stress, it is preferable that the crystal defect due to ion implantation is closer to the interface between the first single-crystal Si layer 3 (second single-crystal Si layer 4) and the first SiGe layer 5. It is advantageous. On the other hand, from the viewpoint of suppressing the amount of ion implantation, it is more advantageous that the implantation range (Rp) be in the porous Si layer 2. Therefore, in the case where the ion implantation amount is reduced by the ion implantation energy having the implantation range (Rp) into the porous Si layer 2, the first SiGe layer 5 is still insufficiently relaxed as a result. At this time, the shortage of the ion implantation amount is reduced by ion implantation with ion implantation energy having an implantation range (Rp) closer to the interface between the first single crystal Si layer 3 (second single crystal Si layer 4) and the first SiGe layer 5. Can be supplemented. That is, as compared with the case of one ion implantation, the crystal defect 9 (primary crystal defect) caused by the ion implantation is more likely to be caused by the ion implantation twice (a plurality of times) than in the case of the single ion implantation. The interface between the crystalline Si layer 4) and the first SiGe layer 5 can be separated relatively deeper (push-out effect), and the junction leakage current of a MOS transistor described later can be further reduced.
[0067]
When the degree of strain release of the first SiGe layer 5a on the substrate (FIG. 2E) manufactured as described above was analyzed by X-ray diffraction analysis (XRD), the strain ion implantation energy was released by about 90% or more. It was confirmed that the SiGe layer was converted to a substantially strain-free SiGe layer. From this, the channel single crystal Si layer 6 laminated on the relaxed first SiGe layer 5a in which the strain has been relaxed can be a strained Si layer that maintains the strain state, that is, the channel single crystal Si layer 6a. it can. Further, since the crystal defects 9 in the first SiGe layer 5 are reduced, the crystal defects in the single crystal Si layer for channel 6a can be reduced, and the characteristics of a MOS transistor described later can be improved. In the analysis using a normalski phase contrast microscope or an electron microscope (SEM), threading dislocations 9e extending from the void 8 and the misfit interface are almost negligible on the surface of the channel single crystal Si layer 6. That was confirmed.
[0068]
A MOS transistor as a semiconductor device is manufactured using the strained channel single crystal Si layer 6a formed on the first SiGe layer 5a as a channel region 6ac (FIG. 3F). A general MOS transistor manufacturing process was used for the manufacturing process of the MOS transistor. An element isolation region 10, a gate insulating film 11, a gate electrode 12, a source region 13, and a drain region 14 are formed, and a strained channel single crystal Si layer 6a corresponding to the gate electrode 12 is used as a channel region 6ac.
[0069]
When the mobility of carriers was evaluated using the fabricated MOS transistor (N-channel), the mobility of electrons was about 80% of that of a normal Si substrate type MOS transistor (N-channel) not using the SiGe layer. Improvement was confirmed. This mobility improvement effect was similarly confirmed irrespective of the presence or absence of the porous Si layer 2. However, the hydrogen ion implantation amount is 1.0 × 10 ¹⁶ / Cm ² In the case of a further decrease, there was a difference depending on the presence or absence of the porous Si layer 2. Specifically, in the MOS transistor (N-channel) manufactured under the condition that the two porous Si layers are not used, the rate of improvement in the electron mobility of the MOS transistor (N-channel) decreases as the amount of implanted hydrogen ions decreases. However, in the MOS transistor (N-channel) employing the porous Si layer 2, the hydrogen ion implantation amount was set to 0.3 × 10 ¹⁶ / Cm ² No reduction in the electron mobility improvement rate was observed until the number of electrons decreased.
[0070]
On the other hand, it is confirmed that the junction leak current of the MOS transistor tends to simply decrease with a decrease in the amount of implanted hydrogen ions. Therefore, crystal defects 9 (dislocation lines 9a and dislocation loops / stack It is suggested that the defect 9b) is responsible for the junction leakage current of the MOS transistor. In a MOS transistor not using the porous Si layer 2, 1.0 × 10 ¹⁶ / Cm ² The junction leakage current in the case of manufacturing with a hydrogen ion implantation amount of about 10 μA / cm at V = 2.5 V ² However, the porous Si layer 2 was employed to reduce the hydrogen ion implantation amount to 0.3 × 10 ¹⁶ / Cm ² Junction leakage current when reduced to 1 μA / cm ² Is obtained, and the effect of reducing the junction leak current by reducing the amount of implanted hydrogen ions accompanying the porous Si layer 2 is obtained.
[0071]
<Embodiment 2>
4 to 6 are cross-sectional views illustrating a process of manufacturing a semiconductor device according to the second embodiment of the present invention. The branch numbers (a to e) in the respective drawings are given throughout FIGS. 4 to 6. Embodiment 1 has one SiGe layer (one growth step), while Embodiment 2 has a plurality of SiGe layers (two growth steps). The same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted.
[0072]
In the same manner as in the first embodiment (FIGS. 1A and 1B), a porous Si layer 2 having a hole 2a is formed on the surface of an Si substrate 1, and a first surface is formed on the surface of the porous Si layer 2. A single-crystal Si layer 3 is formed, and a second single-crystal Si layer 4 is formed on the first single-crystal Si layer 3 by epitaxial growth.
[0073]
Next, a first SiGe layer 25 and a first buffer single crystal Si layer 26 are sequentially deposited on the second single crystal Si layer 4 by epitaxial growth substantially in the same manner as in the first embodiment (FIG. 1C). It is formed (FIG. 4A). Note that the first SiGe layer 25 is formed so as to be in a strain state including a strain (thickness equal to or less than the critical film thickness) as in the first embodiment. The deposition temperature of the first SiGe layer 25 is desirably 700 ° C. or less in consideration of controllability and the like. Further, the first buffer single crystal Si layer 26 is formed so as to be in a strained state including the strain similarly to the first SiGe layer 25.
[0074]
Here, as an example, the first single-crystal Si layer 3 was deposited to about 50 nm, the second single-crystal Si layer 4 was deposited to 5 nm, the first SiGe layer 25 was deposited to 150 nm, and the first buffer single-crystal Si layer 26 was deposited to about 3 to 8 nm. The first SiGe layer 5 has a fixed Ge concentration of 30 atomic%, but may have a concentration gradient as in the first embodiment, and includes a so-called BOX type (concentration gradient) including a second SiGe layer 28 described later. None) or GRADED type (with concentration gradient). The reason why the first buffer single crystal Si layer 26 is formed as thin as about 3 to 8 nm is that it is necessary to include a strain state in order to prevent threading dislocation due to relaxation in the first buffer single crystal Si layer 26 itself. That's why. Further, the second single-crystal Si layer 4 can be omitted as in the case of the first embodiment.
[0075]
Next, ion implantation of hydrogen ions is performed as in the first embodiment (FIG. 2D) (FIG. 4B). Here, as an example, hydrogen ions were implanted at an ion implantation energy of 19 keV. Under these ion implantation conditions, the average implantation range Rp is at a position with a depth of 70 nm from the interface (misfit interface) between the first SiGe layer 25 containing the strain and the second single crystal Si layer 4 to the Si substrate 1 side. . That is, the implanted hydrogen ions 7 pass through the second single crystal Si layer 4 of 5 nm and the first single crystal Si layer 3 of 50 nm and have a depth of 15 nm from the interface between the first single crystal Si layer 3 and the porous Si layer 2. In the porous Si layer 2 of FIG. The concept of determining the implantation conditions (average implantation range Rp, that is, the setting range of implantation energy, the effect of ion implantation, and the like) is the same as in the first embodiment.
[0076]
After the ion implantation, as in the first embodiment (FIG. 2E), annealing is performed, for example, at 800 ° C. for 10 minutes under an inert atmosphere such as argon or a hydrogen atmosphere, and the ion implantation is skipped. In the vicinity of (Rp), a secondary crystal defect is generated. In other words, the voids 8 and the crystal defects 9 caused by the implanted hydrogen ions 7 (the transition lines 9a and threading dislocations 9e grown from the hydrogen voids 8; the threading dislocations 9g in which the transition lines 9a are further extended; 9f) (FIG. 5 (c)). Note that crystal defects (dislocation lines 9c, dislocation loops / stacking faults 9d) that grow from the hole 2a are the same as in the first embodiment, and illustration and description are omitted. When the first SiGe layer 25a does not wait for the Ge concentration gradient, the dislocation line 9a terminates at the misfit interface between the first SiGe layer 25a and the second single-crystal Si layer 4 (dislocation line 9a), or almost all In this case, threading dislocations 9e and 9g are grown in the first SiGe layer 25a. Note that the number of dislocation loops / stacking faults 9f terminated as a loop in the first SiGe layer 25a is extremely small as shown by a broken line because Ge does not wait for a concentration gradient. In many cases, the threading dislocations 9e and 9g terminate at the interface between the first buffer single crystal Si layer 26 and the first SiGe layer 25a due to the occurrence of a slip dislocation.
[0077]
By the annealing process, as in the first embodiment, the compressive stress acting on the first SiGe layer 25 from the hydrogen void 8 and the hole 2a is released by the secondary crystal defect (the void 8 and the crystal defect 9). That is, the compressive stress (strain ion implantation energy) of the first SiGe layer 25 is released due to the secondary crystal defect, and the first SiGe layer 25 becomes the relaxed first SiGe layer 25a in which the strain is relaxed (FIG. 5C). ).
[0078]
Next, a second buffer single crystal Si layer 27, a second SiGe layer 28, and a channel single crystal Si layer 29 are sequentially deposited and formed on the first buffer single crystal Si layer 26 by epitaxial growth (FIG. 5 (d)). )). When the first buffer single-crystal Si layer 26 is in a strained state, the second buffer single-crystal Si layer 27 is also deposited in a strained state including the strain. Further, when the second buffer single crystal Si layer 27 is in a strain state including the strain, the subsequently deposited second SiGe layer 28 can be deposited in a relaxed state. In addition, like the first SiGe layer 5, the deposition temperature of the second SiGe layer 28 is preferably set to 700 ° C. or less in consideration of controllability and the like.
[0079]
If the thickness of the laminated structure of the first buffer single crystal Si layer 26 and the second buffer single crystal Si layer 27 (laminated film thickness, that is, the total film thickness) exceeds the critical film thickness, the first buffer single crystal Si layer 26 The strain state of the crystalline Si layer 26 and the second buffer single crystal Si layer 27 is broken and relaxed. As a result, threading dislocations (having elongated threading dislocations 9a and 9g) grow also in the first buffer single crystal Si layer 26 and the second buffer single crystal Si layer 27, and the second SiGe layer 28 Cannot be brought into a sufficiently relaxed state.
[0080]
Therefore, in order to maintain the relaxed state of the second SiGe layer 28, the deposition of the first buffer single crystal Si layer 26 and the second buffer single crystal Si layer 27 is performed under the condition that the stacked film thickness does not exceed the critical film thickness. (Deposition temperature). As a result of the investigation, it was confirmed that, for example, at a deposition temperature of 510 ° C., the strain state was maintained up to a laminated film thickness of 20 nm of the first buffer single crystal Si layer 26 and the second buffer single crystal Si layer 27. . For example, when the first buffer single crystal Si layer 26 is deposited to a thickness of about 8 nm, the strained state can be maintained if the thickness of the second buffer single crystal Si layer 27 is up to 12 nm.
[0081]
The layer thickness of the first buffer single crystal Si layer 26 and the second buffer single crystal Si layer 27 is set to be equal to or less than the critical thickness, and these strain states are maintained to extend in the first SiGe layer 25a. The crystal defects 9 (threading dislocations 9e and 9g, dislocation loop / stacking fault 9f) can be suppressed or stopped from further extending and growing. In other words, since the crystal defects 9 are stopped by the first buffer single crystal Si layer 26 and the second buffer single crystal Si layer 27, the second SiGe layer 28 is a SiGe layer in a good relaxed state without crystal defects. . In addition, since the SiGe layer has a two-layer structure of the first SiGe layer 25 and the second SiGe layer 28, the restriction on the critical film thickness can be eliminated in the second SiGe layer 28, the Ge concentration can be increased, and the electron concentration can be further increased. Mobility can be improved. Further, when it is necessary to increase the junction depth between the source region 13 and the drain region 14 of the MOS transistor described later, it can be dealt with by increasing the thickness of the second SiGe layer 28, and the degree of freedom in designing the MOS transistor structure is increased. growing. Here, as an example, the second SiGe layer 28 was deposited to a thickness of about 400 nm.
[0082]
Although the formation of the second buffer single crystal Si layer 27 can be omitted, it is preferable that the second buffer single crystal Si layer 27 has a laminated structure with the first buffer single crystal Si layer 26. That is, the second SiGe layer 28 is formed by depositing the second buffer single crystal Si layer 27 on the first buffer single crystal Si layer 26 rather than depositing directly on the first buffer single crystal Si layer 26. It is possible to form a SiGe layer with less crystal defects by depositing from. The reason is that the Si epitaxially grown layer is insensitive to the contaminants (for example, carbon, heavy metal, etc., particularly in the case of oxygen) remaining at the deposition interface, but the SiGe epitaxially grown layer is sensitive, By making the epitaxial growth layer have a laminated structure, the influence of contaminants on the surface of the second buffer single crystal Si layer 27 can be substantially reduced, and the second SiGe layer 28 has a crystal such as hillocks caused by the contaminants. This is because the occurrence of defects can be prevented.
[0083]
The channel single crystal Si layer 29 stacked on the second SiGe layer 28 needs to be deposited as a strained Si layer that maintains a strained state in order to form a strained channel region. The single-crystal Si layer 29 for the channel needs to be formed at a low deposition temperature and a thickness smaller than the critical thickness in order to maintain a strained state. For example, the thickness of the channel single crystal Si layer 29 can be in the range of about 5 to 30 nm. Here, as an example, the deposition temperature was 500 ° C. and the film thickness was 15 nm.
[0084]
It can be confirmed that the second SiGe layer 28 in the substrate (FIG. 5D) manufactured as described above is converted to a substantially strain-free SiGe layer, similarly to the first SiGe layer 5a in the first embodiment. Was. Therefore, the single crystal Si layer 29 for a channel laminated on the relaxed second SiGe layer 28 in which the strain has been relaxed can maintain the strained state. Further, since the crystal defects 9 in the second SiGe layer 28 are reduced, the crystal defects in the channel single crystal Si layer 29 can be reduced, and the characteristics of a MOS transistor described later can be improved.
[0085]
As in the first embodiment, a MOS transistor as a semiconductor device is manufactured using the strained channel single crystal Si layer 29 formed on the second SiGe layer 28 as the channel region 29c (FIG. 6E). A general MOS transistor manufacturing process was used for the manufacturing process of the MOS transistor. The element isolation region 10, the gate insulating film 11, the gate electrode 12, the source region 13, and the drain region 14 are formed, and the strained single crystal Si layer 29 corresponding to the gate electrode 12 is used as the channel region 29c. The characteristics of the fabricated MOS transistor (N-channel) were almost the same as those of the MOS transistor (N-channel) in the first embodiment. In the second embodiment, since the thickness of the second SiGe layer 28 can be increased as described above, the junction depth of the source region 13 and the drain region 14 can be increased, and the junction leakage current can be reduced and the breakdown voltage can be improved. Can be planned.
[0086]
<Comparative example>
7 and 8 are cross-sectional views illustrating a manufacturing process of a comparative example with respect to the second embodiment. Note that the branch numbers (a to c) in each figure are given throughout FIGS. In the second embodiment, a first buffer single-crystal Si layer 26 and a second buffer single-crystal Si layer 27 are provided between a first SiGe layer 25 (25a) and a second SiGe layer 28; Is a structure in which the first SiGe layer 25 (25a) and the second SiGe layer 28 are directly laminated without providing the first buffer single crystal Si layer 26 and the second buffer single crystal Si layer 27. The same parts as those in the second embodiment are denoted by the same reference numerals, and detailed description is omitted.
[0087]
As in the second embodiment (FIG. 4A), a porous Si layer 2 is formed on the surface of a Si substrate 1, and a first single-crystal Si layer 3 is formed on the surface of the porous Si layer 2. . Further, a second single-crystal Si layer 4 is formed on the first single-crystal Si layer 3 and a first SiGe layer 25 is formed on the second single-crystal Si layer 4 by epitaxial growth (FIG. 7A). For example, the first single-crystal Si layer 3 was deposited to 50 nm, the second single-crystal Si layer 4 was deposited to 5 nm, and the first SiGe layer 25 was deposited to 150 nm. The Ge concentration of the first SiGe layer 25 was 30 atomic%.
[0088]
Next, as in Embodiment 2 (FIG. 4B), ion implantation of hydrogen ions is performed at an ion implantation energy of 19 keV (FIG. 7A), and annealing is further performed to form the first SiGe layer 25. Then, the first SiGe layer 25a in the relaxed state in which the strain is relaxed from the strained state is formed (FIG. 7B). The ion implantation was performed without providing the first buffer single crystal Si layer 26. Under the ion implantation conditions at this time, the average implantation range Rp is about 70 nm in depth from the interface (misfit interface) between the first SiGe layer 25 containing the strain and the second single crystal Si layer 4 to the Si substrate 1 side. Position. That is, the implanted hydrogen ions 7 pass through the second single crystal Si layer 4 of 5 nm and the first single crystal Si layer 3 of 50 nm and have a depth of 15 nm from the interface between the first single crystal Si layer 3 and the porous Si layer 2. Stop in the layer of the porous Si layer 2 to a certain extent.
[0089]
After the ion implantation, similarly to the second embodiment (FIG. 5C), annealing is performed, for example, at 800 ° C. for 10 minutes in an inert atmosphere such as argon, and the crystal is formed near the implantation range (Rp). Generate defects. That is, the voids 8 and the crystal defects 9 caused by the implanted hydrogen ions 7 implanted by the ion implantation (transition lines 9a, threading dislocations 9e grown from the hydrogen voids 8, threading dislocations 9g further extending the transition lines 9a, dislocation loops / stacking) A defect 9f) is generated (FIG. 7B). Note that crystal defects (dislocation lines 9c, dislocation loops / stacking faults 9d) that grow from the hole 2a are the same as in the first embodiment, and illustration and description are omitted.
[0090]
By the annealing process, as in the second embodiment, the compressive stress acting on the first SiGe layer 25 from the hydrogen void 8 and the hole 2a is released by the secondary crystal defect (crystal defect 9). That is, the compressive stress of the first SiGe layer 25 is released by the crystal defect 9, and the first SiGe layer 25 becomes the relaxed first SiGe layer 25a in which the strain is relaxed (FIG. 7B). In the first SiGe layer 25a, threading dislocations 9e and 9g and dislocation loop / stacking fault 9f grow as crystal defects 9.
[0091]
Next, on the first SiGe layer 25a, a second SiGe layer 28 and a single crystal Si layer 29 for a channel are sequentially formed by epitaxial growth (FIG. 8C). Since the first SiGe layer 25a is already in a relaxed state, the thickness of the second SiGe layer 28 is not limited. In order for the channel single crystal Si layer 29 to be a channel region in a strained state, it is necessary to maintain the strained state, and there is a limitation on the critical film thickness. A second SiGe layer 28 was deposited to a thickness of 400 nm, and a channel single crystal Si layer 29 was deposited to a thickness of 20 nm at a deposition temperature of 500 ° C. The Ge concentration of the second SiGe layer 28 was 30 atomic%.
[0092]
In the case where the first SiGe layer 25 (25a) and the second SiGe layer 28 are directly laminated, the threading dislocations 9e and 9g extending to the surface of the first SiGe layer 25a are the starting points, and are introduced into the second SiGe layer 28. The threading dislocations 9ea and 9ga further extend and grow (FIG. 8C). Since the junction (source region 13 and drain region 14) of the MOS transistor is formed in the second SiGe layer 28, the presence of threading dislocations 9ea and 9ga in the junction causes an increase in junction leakage current.
[0093]
【The invention's effect】
As described in detail above, according to the semiconductor device and the semiconductor device manufacturing method according to the present invention, a porous silicon layer is formed on the surface of the silicon substrate, and the porous silicon layer is formed on the surface of the porous silicon layer from the porous silicon layer. A first silicon germanium layer formed by being stacked on top of the first single crystal silicon layer and the second single crystal silicon layer by introducing a crystal defect into a region up to the first single crystal silicon layer and the second single crystal silicon layer Can be in a relaxed state with few crystal defects, so that the strained silicon layer formed on the first silicon germanium layer can be used as a strain channel region with few crystal defects to improve the electron mobility of the MOS transistor, and to further improve the junction leakage. Current can be reduced.
[0094]
According to the semiconductor device and the method of manufacturing a semiconductor device according to the present invention, the porous silicon layer formed on the surface of the silicon substrate, and the first single crystal silicon layer and the second single crystal silicon layer formed on the surface of the porous silicon layer A first buffer single-crystal silicon layer, a second buffer single-crystal silicon layer, and a second buffer single-crystal silicon layer between the first silicon-germanium layer and the second silicon-germanium layer formed on the first single-crystal silicon layer and the second single-crystal silicon layer. By depositing the buffer single crystal silicon layer, the second silicon germanium layer can be brought into a relaxed state with few crystal defects, so that the strained silicon layer formed by stacking on the second silicon germanium layer can be strained with few crystal defects. It is possible to improve the electron mobility of the MOS transistor serving as the channel region and further reduce the junction leak current.
[0095]
ADVANTAGE OF THE INVENTION According to the semiconductor device and the semiconductor device manufacturing method according to the present invention, a simple process change of forming a porous silicon layer and a change of a substrate structure do not cause a problem that a processing capability of a wafer is reduced, and the number of crystal defects is small. A silicon germanium layer can be formed, and a strained silicon layer formed on the silicon germanium layer can be used as a high-quality strain channel region with few crystal defects to improve the electron mobility of a MOS transistor and further reduce junction leakage current. . The MOS transistor realized by the present invention can use the design resources of the conventional bulk device (MOS transistor) as it is, and can easily realize a semiconductor device with low voltage operation, high speed operation, and low power consumption.
[Brief description of the drawings]
FIG. 1 is a sectional view illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the second embodiment of the present invention.
FIG. 5 is a sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;
FIG. 6 is a sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;
FIG. 7 is a sectional view illustrating a manufacturing process of a comparative example with respect to the second embodiment.
FIG. 8 is a sectional view illustrating a manufacturing process of a comparative example with respect to the second embodiment.
FIG. 9 is a cross-sectional view of a semiconductor device according to Conventional Example 1 having a strained Si layer.
FIG. 10 is a sectional view showing a manufacturing process of a semiconductor device according to Conventional Example 2 having a strained Si layer.
[Explanation of symbols]
1 Silicon substrate (Si substrate)
2 Porous silicon layer (porous Si layer)
3 First single-crystal silicon layer (first single-crystal Si layer)
4 Second single crystal silicon layer (second single crystal Si layer)
5, 5a, 25, 25a First silicon germanium layer (first SiGe layer)
6, 6a, 29 Single-crystal silicon layer for channel (single-crystal Si layer for channel)
6ac, 29c channel region
7 Implanted hydrogen ions
8 void
9 Crystal defects
10 Device isolation area
11 Gate insulating film
12 Gate electrode
13 Source area
14 Drain region
26 First buffer single crystal silicon layer (first buffer single crystal Si layer)
27 Second buffer single crystal silicon layer (second buffer single crystal Si layer)
28 Second silicon germanium layer (second SiGe layer)

Claims (25)

In a semiconductor device in which a strained single crystal silicon layer formed over a silicon germanium layer is used as a channel region of a transistor,
A porous silicon layer formed on the surface of the silicon substrate, a first single crystal silicon layer formed on the surface of the porous silicon layer, and a first silicon germanium in a strain relaxed state laminated on the first single crystal silicon layer A single crystal silicon layer for a channel in a strained state which is stacked on the first silicon germanium layer to form a channel region;
A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the first silicon germanium layer has a germanium concentration gradient. In a semiconductor device in which a strained single crystal silicon layer formed over a silicon germanium layer is used as a channel region of a transistor,
A porous silicon layer formed on the surface of the silicon substrate, a first single crystal silicon layer formed on the surface of the porous silicon layer, and a first silicon germanium in a strain relaxed state laminated on the first single crystal silicon layer Layer, a first buffer single crystal silicon layer stacked on the first silicon germanium layer, a strain relaxed second silicon germanium layer stacked on the first buffer single crystal silicon layer, and a second silicon germanium layer A single-crystal silicon layer for a channel in a strained state laminated on
A semiconductor device comprising: 4. The semiconductor device according to claim 3, further comprising a second buffer single crystal silicon layer laminated between the first buffer single crystal silicon layer and the second silicon germanium layer. 5. The semiconductor device according to claim 1, further comprising a second single crystal silicon layer laminated between the first single crystal silicon layer and the first silicon germanium layer. 6. The semiconductor according to claim 1, wherein the thickness of the first single-crystal silicon layer or the thickness of the first single-crystal silicon layer and the second single-crystal silicon layer is 5 nm to 190 nm. apparatus. 7. The semiconductor device according to claim 1, wherein the first silicon germanium layer has a thickness of 10 nm to 500 nm. 8. The semiconductor device according to claim 1, wherein the first silicon germanium layer or the second silicon germanium layer has a germanium concentration of 10 to 50 atomic%. 9. In a semiconductor device manufacturing method for forming a transistor having a strained single crystal silicon layer formed over a silicon germanium layer as a channel region,
A step of forming a porous silicon layer on the surface of the silicon substrate, a step of converting the surface of the porous silicon into a first single-crystal silicon layer by hydrogen annealing, and a step of forming a second single-crystal on the first single-crystal silicon layer. A step of sequentially epitaxially growing a silicon layer and a first silicon germanium layer; a step of epitaxially growing a single crystal silicon layer for a channel on the first silicon germanium layer; Introducing a crystal defect into the crystalline silicon layer, the second single-crystal silicon layer, or the porous silicon layer;
A method of manufacturing a semiconductor device, comprising: 10. The method according to claim 9, wherein the first silicon germanium layer is formed with a germanium concentration gradient. In a semiconductor device manufacturing method for forming a transistor having a strained single crystal silicon layer formed over a silicon germanium layer as a channel region,
A step of forming a porous silicon layer on the surface of the silicon substrate, a step of converting the surface of the porous silicon into a first single-crystal silicon layer by hydrogen annealing, and a step of forming a second single-crystal on the first single-crystal silicon layer. A step of sequentially epitaxially growing a silicon layer, a first silicon germanium layer, and a first buffering single crystal silicon layer; and ion implantation and annealing after the ion implantation, in the first single crystal silicon layer and the second single crystal silicon layer. Introducing a crystal defect in the inside or in the porous silicon layer, and a second buffer single crystal silicon layer, a second silicon germanium layer, and a channel single crystal silicon on the first buffer single crystal silicon layer. Epitaxially growing the layer;
A method of manufacturing a semiconductor device, comprising: The method according to claim 11, wherein the step of epitaxially growing the second buffer single crystal silicon layer is omitted. 13. The method according to claim 11, wherein the second silicon germanium layer is epitaxially grown as a layer in a strain relaxed state. 14. The method according to claim 11, wherein the single crystal silicon layer for a channel is epitaxially grown as a strained layer. 15. The method according to claim 9, wherein a step of epitaxially growing the second single-crystal silicon layer is omitted. 16. The semiconductor according to claim 9, wherein the thickness of the first single-crystal silicon layer or the thickness of the first single-crystal silicon layer and the second single-crystal silicon layer is 5 nm to 190 nm. Device manufacturing method. 17. The method according to claim 9, wherein the first silicon germanium layer is formed to a thickness equal to or less than a critical thickness. The method according to claim 17, wherein the first silicon germanium layer has a thickness of 10 nm to 500 nm. 19. The method according to claim 9, wherein the first silicon germanium layer or the second silicon germanium layer has a germanium concentration of 10 to 50 atomic%. 20. The method of manufacturing a semiconductor device according to claim 9, wherein a growth temperature for epitaxially growing the first silicon germanium layer or the second silicon germanium layer is 700 [deg.] C. or less. 21. The method according to claim 9, wherein an ion species used for ion implantation is hydrogen or helium. 22. The ion implantation according to claim 9, wherein the average implantation range is in one of the porous silicon layer, the first single crystal silicon layer, and the second single crystal silicon layer. Semiconductor device manufacturing method. 23. The method according to claim 9, wherein the ion implantation is performed a plurality of times. 24. The method of manufacturing a semiconductor device according to claim 9, wherein the ion implantation amount in the ion implantation is a value selected from a range of 0.3 to 3 * 10 < ¹⁶ > / cm < ² >. 25. The method of manufacturing a semiconductor device according to claim 9, wherein a temperature in an annealing process after the ion implantation is in a range of 600 to 950.degree.

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