JP2005005319A - Method for forming wiring and wiring board - Google Patents
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- JP2005005319A JP2005005319A JP2003164048A JP2003164048A JP2005005319A JP 2005005319 A JP2005005319 A JP 2005005319A JP 2003164048 A JP2003164048 A JP 2003164048A JP 2003164048 A JP2003164048 A JP 2003164048A JP 2005005319 A JP2005005319 A JP 2005005319A
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【０００１】
【発明の属する技術分野】
本発明は、回路間の絶縁抵抗を維持して高密度プリント配線に関する。より詳しくは、フルアディティブ法によるプリント配線における、高密度プリント配線のための表面処理に関する。
【０００２】
【従来の技術】
近年、電子機器の多機能化、小型化により、多層プリント配線板は高密度配線を強く要求されるようになり、狭ピッチ配線の対応が必要となっている。従来、プリント配線板の配線形成は、エッチングで形成するサブトラクティブ法で行うのが一般的であった。しかし、サブトラクティブは、配線側が過激にエッチングされ、配線幅および間隔が５０μｍ以下になると、急激に歩留まりが低下する。そこで、フルアティティブ法が、配線の形成精度に優れている点で、サブトラクティブ法に代り採用されるようになった。
図１は一般的なフルアディティブ法による基板の断面図である。
一般的なフルアディティブ法は、内層コア基板に下地絶縁層１０を形成し、銅メッキの密着性を得るために、過マンガン酸、クロム酸等によるデスミア処理を行って下地絶縁表面の粗化を行う。次に、下地絶縁層１０の表面にパラジウムなどのメッキ触媒１１を付着させ、配線形成部分以外の下地絶縁層１０の表面にメッキレジスト１２を形成し、銅メッキにより配線１３を形成するものである（図１参照）。
【０００３】
しかし、めっきレジストと下地絶縁層の界面にめっき触媒が過剰に存在するため、配線ピッチが狭くなると回路間の絶縁抵抗が低くなり、絶縁信頼性が低下する問題がある。そこで、下地絶縁層にめっきレジストを形成した後でめっき触媒を付着させることが行われている（例えば、特許文献１を参照）。これにより、めっきレジストと下地絶縁層の界面にめっき触媒が存在せず、絶縁信頼性を確保できるものである。また、めっきレジスト表面にめっき触媒が付着していると、めっきレジスト表面にも銅めっきが析出し、隣り合う配線間が短絡してしまうので、めっきレジストに付着しためっき触媒を酸化剤に浸漬して除去している。 特許文献１に記載の技術においては、めっきレジストに付着しためっき触媒を酸化剤に浸漬して除去するため、下地絶縁層表面のめっき触媒についても一部除去されてしまうので、酸化剤に浸漬する条件の管理が難しく、下地絶縁層のめっき触媒が過剰に除去されてしまうと、銅めっきの析出不良になってしまう。
【０００４】
この他に、下地絶縁層にめっきレジストを形成した後に、表面粗化を行い、めっき触媒を付着させて、バフ研磨等でめっき触媒付着のレジスト部に対して平坦化して、その後に、めっきレジスト上へさらに上層レジストを形成する技術が知られている（例えば、特許文献２参照）。この上層レジストの存在により、後に行う銅めっき工程において、めっきレジスト上に存在するめっき触媒上への銅めっきの析出も無く、また、レジスト側面にめっき触媒が付着し、めっき成長時に発生する隣接するレジスト表面へのめっきのせり出しが無く回路のうねりも小さい。
また、特許文献２に記載の技術においては、上層レジスト形成時に露光時にて位置ずれが生じると、上層レジスト下に隙間が生じる。この事により銅めっき時に気泡が入りボイド不良となってしまう。さらに、研磨工程や上層レジスト形成工程といった工程数も増加してしまう。
【０００５】
【特許文献１】
特開平７−２９７５２０号公報
【特許文献２】
特開２０００−３１２０６５号公報
【０００６】
【発明が解決しようとする課題】
上記事情に鑑み、本発明では、配線と絶縁層間の密着力を確保しつつ触媒が絶縁層表面へ過剰に付与されることを抑制して、配線間の絶縁抵抗劣化を抑制することを目的とする。
【０００７】
【課題を解決するための手段】
本発明の配線形成方法は、基板上に形成された絶縁層表面とオゾン溶液を接触させて該絶縁層表面に紫外線照射するオゾン溶液−紫外線照射処理工程と、オゾン溶液−紫外線照射処理が施された絶縁層表面に触媒を付与する触媒付与工程と、触媒が付与された絶縁層表面に所定パターンのレジストを形成するレジスト形成工程と、レジスト形成工程後、絶縁層表面に導電層を無電解めっきにより形成する導電層形成工程と、を含む配線形成方法を用いる。
【０００８】
オゾン溶液−紫外線照射処理工程におけるオゾン溶液のオゾン濃度は１００ｐｐｍ以上であり、紫外線の照射量は１０００ｍＪ／ｃｍ２以上であることが好ましい。
【０００９】
触媒付与工程における絶縁層表面の触媒付与量は１０〜８０μｇ／ｄｍ２であることが好ましい。
【００１０】
オゾン溶液−紫外線照射処理工程にて絶縁層表面の中心線表面粗さを１．０μｍ以下とすることが好ましい。
【００１１】
本発明の配線基板は、上記本発明の配線形成方法で配線した基板であることを特徴としている。
【００１２】
導電層と絶縁層との密着強度は１ｋＮ／ｍ以上であることが好ましい。
【００１３】
【発明の実施の形態】
発明者等は数多くの検討を行った結果、めっき触媒が付着する基板表面の表面処理状態が、めっきにより形成された回路間の絶縁抵抗に大きく影響を与えることを見出した。基板表面の表面状態により、めっき触媒の残存量が変化し、めっき触媒の残存量により回路間の絶縁抵抗が影響を受けるものである。すなわち、基板の絶縁層の上面に表面処理を行い、表面状態を調節することにより、めっき触媒の残存量を調節して回路間の絶縁抵抗の低下を防ぐことができるものである。
【００１４】
発明者等は、従来の過マンガン酸やクロム酸などを用いたデスミア処理に対して、オゾン水等のオゾン溶液および紫外線照射を用いて絶縁層の表面処理を行うことにより、良好な表面状態を得ることを見出したものである。
本発明の配線形成方法におけるオゾン溶液−紫外線照射処理工程では、基板上に形成された絶縁層表面とオゾン溶液を接触させた状態で絶操層表面に紫外線を照射している。絶縁層表面と絶縁層表面とオゾン溶液を接触させた状態で絶縁層表面に紫外線を照射することによって、オゾン溶液中のオゾンのみならずオゾン溶液から発生する酸素に紫外線が照射されることで生成する酸素ラジカルにより、絶縁層表面が活性化される作用と、オゾン溶液が活性化した絶縁層表面の活性基と結合して極性基を生成する作用と、紫外線照射により絶縁層に与えられる過剰な熱をオゾン溶液に逃がすことにより絶縁層表面に与えられる熱ダメージを抑制する作用と、が相乗的に作用して、絶縁層表面の粗面化を抑制しながら絶縁層表面を効果的に活性化させることができる。
【００１５】
絶縁層の素材として不飽和結合を有する絶縁体を用いることができ、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ポリアミドイミド樹脂、ビスマレイミド樹脂、不飽和ポリエステル樹脂、ケイ素樹脂などの樹脂を例示することができる。
オゾン溶液中のオゾン濃度は１００ｐｐｍ以上とすることが望ましい。オゾン濃度を１００ｐｐｍ以上とすることによりオゾン溶液−紫外線照射処理を短時間で行うことができ、絶縁層に与えるダメージを少なくすることができる。
オゾン溶液と絶縁層表面との接触時間は４〜２０分とするのが好ましい。４分未満ではオゾン濃度を１００ｐｐｍとしても活性化が不足することがあり、２０分を超えると絶縁層に劣化が生じる場合がある。
オゾン溶液は、通常は水を溶媒とするが、有機又は無機の極性溶媒を溶媒とすることができる。有機極性溶媒としてはメタノール、エタノール等のアルコール類、酢酸等の有機酸類、或いはこれらを水やアルコール系溶媒と混合したものが例示される。また無機性極性溶媒としては、硝酸、塩酸、フッ酸等の無機酸が例示される。
【００１６】
照射する紫外線の照射量は１０００ｍＪ／ｃｍ２以上であることが望ましい。紫外線の照射量が１０００ｍＪ／ｃｍ２より少ないとオゾン溶液のオゾン濃度が低い場合に絶縁層表面の活性化が不足することがある。
オゾン溶液と絶縁層表面を接触させる方法は、オゾン溶液中に基板を浸漬させる方法、絶縁層表面にオゾン溶液をスプレーする方法などがある。
本発明の発明形成方法では、オゾン溶液−紫外線照射工程後、絶縁層表面とアルカリ成分を含む溶液とを接触させるアルカリ溶液処理工程をさらに行うことが好ましい。アルカリ成分は絶縁層表面を分子レベルで溶解する機能を持ち、絶縁層表面の脆化部を除去して官能基をより多く表出させることができるので、配線となるめっき被膜の密着力が向上する。
アルカリ成分としては、絶縁層表面を分子レベルで溶解する機能を持つものを用いることができ、水酸化ナトリウム、水酸化カリウム、水酸化リチウム等が例示される。
アルカリ成分を含む溶液には、さらに陰イオン性界面活性剤及び非イオン性界面活性剤の少なくとも一方が含まれていることが望ましい。
本発明の配線形成方法では、オゾン溶液―紫外線照射処理工程において絶縁層表面はオゾン溶液―紫外線照射処理により粗面化が抑制され表面積の増大が抑制されているので、触媒付与工程で触媒が絶縁層表面に過剰に付与されることは抑制される。
【００１７】
触媒付与工程における絶縁層表面に付与する触媒付与量は１０〜８０μｇ／ｄｍ２であることが望ましい。触媒付与量が１０μｇ／ｄｍ２より少ないとオゾン溶液−紫外線照射処理においてオゾン溶液のオゾン濃度が低い場合や紫外線照射量が少ない場合に無電解めっき膜の密着力が小さくなることがある。触媒付与量が８０μｇ／ｄｍ２より多いと配線間の間隔が１００μｍ以下となった場合に配線間の絶縁信頼性が低下することがある。
本発明の配線形成方法では、触媒付与工程で触媒が絶縁層表面に過剰に付与されることが抑制されているので、レジスト形成工程ではレジストと絶縁層の界面に過剰に触媒が存在することが抑制された状態で絶縁層表面にレジストを形成することができる。
本発明の配線形成方法では、絶縁層表面はオゾン溶液−紫外線照射処理されることにより効果的に活性化されているので、導電層形成工程における無電解めっき処理では、触媒の付与が抑制されていても密着力を確保することができる。
【００１８】
【実施例】
本発明の配線形成方法を実施例、比較例、参考例、参考比較例により具体的に説明する。
【００１９】
（参考例１）
参考例１のめっき被膜の成形方法について説明する。
厚さ０．６ｍｍのガラスエポキシ基板を基材とした。基板に厚さ５０μｍのドライフィルム型接着剤をラミネータにより貼り合わせ、紫外線を露光し、加熱して完全硬直させた。これにより、基材の上に絶縁層を形成した。
なお、硬化させるための紫外線はピーク波長が４００ｎｍであり、１〜３Ｊ／ｃｍ２で露光させたものである。加熱温度は１２０〜１４０℃であり、加熱時間は１〜２時間であった。
【００２０】
絶縁層を形成した基板をオゾン濃度が１００ｐｐｍ以上のオゾン水へ浸漬し、基板を浸漬したまま絶縁層に紫外光を照射した。オゾン水への浸漬時間は４分〜２０分であり、紫外光の照射量は少なくとも１０００ｍＪ／ｃｍ２以上であった。その後、触媒処理液に基板を浸漬させて絶縁層表面にパラジウム触媒を付着させた。
この後に、基板を無電解めっき液に浸漬し、厚さ２５μｍ以上の銅めっき被膜を絶縁層上に形成した。
上記参考例１のめっき被膜の形成方法によりめっき被膜を形成した基板を数個作成した。
【００２１】
（参考比較例１）
参考比較例１のめっき被膜の形成方法について説明する。
参考例１と同様の基板を用いて参考例１と同様に、絶縁層を形成した。
絶縁層と形成した基板を過マンガン酸溶液で処理し絶縁層表面にパラジウム触媒を付着させた後、参考例１と同様に絶縁層表面に参考例１と同等厚さの銅めっき被覆を形成した。上記参考比較例１のめっき被膜の形成方法によりめっき被膜を形成した基板を数個作成した。
【００２２】
（参考比較例２）
参考比較例２のめっき被膜の形成方法について説明する。
参考例１と同様の基板を用いて、参考例１と同様に絶縁層形成後、酸素濃度が５〜１００％の気体雰囲気で紫外線を照射した。紫外線の照射量は参考例１と同等であった。この後に、参考例１と同様の触媒処理液を用いて絶縁層表面にパラジウム触媒を付着させた後、参考例１と同様に絶縁層表面に参考例１と同等厚さの銅めっき被膜を形成した。上記参考比較例２のめっき被膜の形成方法によりめっき被膜を形成した基板を数個作成した。
【００２３】
（参考評価）
次に、各基板について、銅めっき被膜と絶縁層間の密着強度をピール強度測定により測定した。また、銅めっきをエッチングした後、表面粗さ測定装置にて、中心平均粗さ（Ｒａ）を測定した。また、絶縁膜上のパラジウム触媒量も測定した。表１はピール強度測定、中心線平均粗さ（Ｒａ）測定、パラジウム吸着量および外観についての結果を示すものである。
【表１】
結果、ピール強度は、いずれの基板も１．０ｋＮ／ｍ以上を満たした。
中心線平均粗さ（Ｒａ）測定では、参考例１、参考比較例２では１．０μｍ以下と非常に平滑であった。参考比較例１で５〜６μｍとデスミア処理により粗さが大きくなっている。
下地絶縁材上のＰｄ量は、参考比較例１においては、１６０〜２５０μｇ／ｄｍ２であったのに対して、参考例１と参考比較例２ではそれぞれ、２５〜５０μｇ／ｄｍ２、３０〜５０μｇ／ｄｍ２となり参考比較例１の約三分の一から約十分の一の量になっていることがわかる。
このことから、絶縁層表面の粗面化を抑制することによって、触媒付与量を抑制できることは明らかである。
各基板の外観を観察したところ、参考比較例２においては、基板の一部にヤケが発生しており、ひどく焼けた部分についてはめっきが析出していなかった。参考例１では外観に問題はなかった。このことは、参考比較例２のような気体雰囲気では生じる紫外線によるダメージが、オゾン溶液により抑制された結果であると考えられる。
【００２５】
（実施例１）
実施例１の配線形成方法および配線基板
参考例１と同様の基板を用いて、参考例１と同様に絶縁層を形成した。
絶縁層を形成した基板をオゾン濃度が１００ｐｐｍ以上のオゾン水へ浸漬し、基板を浸漬したまま絶縁層に紫外光を照射した。オゾン水への浸漬時間は４分〜２０分であり、紫外光の照射量は少なくとも１０００ｍＪ／ｃｍ２以上であった。その後、触媒処理液に基板を浸漬させて絶縁層表面にパラジウム触媒を付着させた。
次に、レジストフィルム（ドライフィルムレジスト）をラミネータにてラミネートし、配線パターンを露光して形成した。これにより、配線幅および間隔が２０、４０、６０μｍの櫛形パターンを形成した。
そして、基板全体を無電解めっき液に浸漬し、配線部にめっき銅を析出させ、無電解銅めっき層により配線を形成して、配線基板を製作した。
【００２６】
（比較例１）
比較例１の配線形成方法および配線基板について説明する。
実施例１と同様の基板を用いて、実施例と同様に絶縁層を構成した。絶縁層を形成した基板を過マンガン酸溶液で処理して絶縁層表面の粗面化（デスミア処理）を行った。実施例１と同様の触媒処理液を用いて絶縁層表面にパラジウム触媒を付着させた後、実施例１と同様に、レジストフィルム用いて、回路幅および間隔が２０、４０、６０μｍの櫛形パターンを形成し、無電解めっき液に浸漬して配線部に銅を析出させて銅めっき配線を形成して、配線基板を製作した。
【００２７】
（比較例２）
比較例２の配線形成方法および配線基板について説明する。
実施例１と同様の基板を用いて実施例１と同様に絶縁層を形成した後に、酸素濃度が５〜１００％の気体雰囲気下で紫外線を照射した。紫外線の照射量は実施例１と同等であった。
この後に、実施例１と同様の触媒処理液を用いて絶縁層表面に実施例１と同様にパラジウム触媒を付着させ、レジストフィルム用いて、回路幅および間隔が２０、４０、６０μｍの櫛形パターンを形成し、無電解銅めっきに浸漬して配線部に銅を析出させて銅めっき配線を形成して、配線基板を製作した。
【００２８】
（評価）
実施例１、比較例１および比較例２の基板について、めっきレジストと下地絶縁層の界面に残存するめっき触媒による回路間の絶縁抵抗劣化を評価するための電食試験を行った。試験は、温度８５℃、湿度８５％の恒温恒湿槽内で行い、各櫛形回路パターンには直流１００Ｖを印加しながら配線間の絶縁抵抗を測定した。配線形成の可否および電食試験についての結果を表２に示す。
【表２】
表２において、Ｌ／Ｓ＝Ｏ／Ｏμｍは下段の数値（６０／６０など）に対応するものであり、Ｌは配線の幅を、Ｓは配線間におけるめっきレジストの幅を示すものである。また、表２中の○は配線が良好に成形されていることを意味するものである。例えば、「配線形成の可否」の「６０／６０」の行での○は配線を、６０μｍの間隔を空けて、幅を６０μｍで形成した場合に、配線線の形成状態が良好であったことを示すものである。
【００３０】
結果、実施例１、比較例１、比較例２について、いずれの配線基板においても配線は形成されていた。そして、電食試験において、比較例１の配線基板は、間隔が２０μｍ、４０μｍ、６０μｍのもの全てで、１０００時間経過後において、配線間にショートがみられたが、実施例１の配線基板では、全てのパターンで初期値で１０１２Ω以上、１０００時間経過後でも１０１２Ω以上の配線間絶縁抵抗が得られた。電食試験後に各配線基板の外観を観察したところ、比較例２の配線基板にのみ配線の一部がはがれて断線している部分が見られた。
【００３１】
以上のことから、実施例１の配線形成方法では、絶縁層表面とオゾン溶液を接触させた状態で紫外線を照射することにより、絶縁層表面の粗面化を抑制ながら絶縁層表面を効果的に活性化させて、触媒が絶縁層表面に過剰に付与されることを抑制した上で配線を形成するので、配線間に過剰に触媒が残存することを抑制することができ、配線の密着力（ピール強度１ｋＮ／ｍ以上）を確保しつつ配線間の絶縁抵抗劣化を抑制された配線基板が製作できていることが明らかである。
【００３２】
【発明の効果】
本発明によれば、配線と絶縁層間の密着力を確保しつつ配線間の絶縁抵抗劣化を抑制することができる。
【図面の簡単な説明】
【図１】一般的なフルアディティブ法による基板の断面図。
【符号の説明】
１０ 絶縁層
１１ めっき触媒
１２ めっきレジスト
１３ 配線[0001]
BACKGROUND OF THE INVENTION
The present invention relates to high-density printed wiring while maintaining insulation resistance between circuits. More specifically, the present invention relates to surface treatment for high-density printed wiring in printed wiring by a full additive method.
[0002]
[Prior art]
In recent years, with the increase in functionality and miniaturization of electronic devices, multilayer printed wiring boards have been strongly required to have high-density wiring, and it is necessary to cope with narrow-pitch wiring. Conventionally, wiring formation of a printed wiring board has been generally performed by a subtractive method formed by etching. However, in the subtractive process, when the wiring side is etched extremely, and the wiring width and interval become 50 μm or less, the yield decreases rapidly. Therefore, the full-active method has come to be used in place of the subtractive method in that it has excellent wiring formation accuracy.
FIG. 1 is a cross-sectional view of a substrate by a general full additive method.
In a general full additive method, a
[0003]
However, since the plating catalyst is excessively present at the interface between the plating resist and the base insulating layer, when the wiring pitch is narrowed, there is a problem that the insulation resistance between circuits is lowered and the insulation reliability is lowered. Therefore, a plating catalyst is attached after forming a plating resist on the base insulating layer (see, for example, Patent Document 1). Thereby, there is no plating catalyst at the interface between the plating resist and the base insulating layer, and insulation reliability can be ensured. In addition, if a plating catalyst adheres to the plating resist surface, copper plating will also deposit on the plating resist surface, causing a short circuit between adjacent wirings, so the plating catalyst adhering to the plating resist is immersed in an oxidizing agent. Have been removed. In the technique described in Patent Document 1, since the plating catalyst adhering to the plating resist is immersed and removed in the oxidizing agent, the plating catalyst on the surface of the underlying insulating layer is also partially removed, so that it is immersed in the oxidizing agent. If the conditions are difficult to manage and the plating catalyst of the underlying insulating layer is excessively removed, copper plating deposition failure will occur.
[0004]
In addition to this, after forming a plating resist on the base insulating layer, surface roughening is performed, a plating catalyst is attached, and the plating catalyst adhesion resist portion is flattened by buffing or the like. A technique for further forming an upper layer resist on the top is known (for example, see Patent Document 2). Due to the presence of this upper layer resist, there is no deposition of copper plating on the plating catalyst existing on the plating resist in the copper plating step to be performed later, and the plating catalyst adheres to the side surface of the resist, so that it is adjacent to the plating generated during the growth of plating. There is no protrusion of the plating on the resist surface, and the circuit undulation is small.
In the technique described in Patent Document 2, if a positional shift occurs during exposure during the formation of the upper layer resist, a gap is generated under the upper layer resist. As a result, air bubbles enter during copper plating, resulting in a void failure. Furthermore, the number of steps such as a polishing step and an upper layer resist forming step also increases.
[0005]
[Patent Document 1]
JP-A-7-297520 [Patent Document 2]
Japanese Patent Laid-Open No. 2000-312065
[Problems to be solved by the invention]
In view of the above circumstances, an object of the present invention is to suppress an excessive application of the catalyst to the surface of the insulating layer while ensuring adhesion between the wiring and the insulating layer, and to suppress deterioration of insulation resistance between the wires. To do.
[0007]
[Means for Solving the Problems]
In the wiring forming method of the present invention, an ozone solution-ultraviolet irradiation treatment process in which an insulating layer surface formed on a substrate is brought into contact with an ozone solution to irradiate the insulating layer surface with ultraviolet rays, and an ozone solution-ultraviolet irradiation treatment are performed. A catalyst applying step for applying a catalyst to the surface of the insulating layer, a resist forming step for forming a resist of a predetermined pattern on the surface of the insulating layer provided with the catalyst, and an electroless plating on the surface of the insulating layer after the resist forming step. And a conductive layer forming step formed by the step.
[0008]
The ozone concentration of the ozone solution in the ozone solution-ultraviolet irradiation treatment step is preferably 100 ppm or more, and the irradiation amount of ultraviolet rays is preferably 1000 mJ / cm 2 or more.
[0009]
The amount of catalyst applied on the surface of the insulating layer in the catalyst application step is preferably 10 to 80 μg / dm 2 .
[0010]
In the ozone solution-ultraviolet irradiation treatment process, the center line surface roughness of the insulating layer surface is preferably 1.0 μm or less.
[0011]
The wiring board of the present invention is a board wired by the wiring forming method of the present invention.
[0012]
The adhesion strength between the conductive layer and the insulating layer is preferably 1 kN / m or more.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
As a result of many investigations, the inventors have found that the surface treatment state of the substrate surface to which the plating catalyst adheres greatly affects the insulation resistance between circuits formed by plating. The remaining amount of the plating catalyst varies depending on the surface state of the substrate surface, and the insulation resistance between the circuits is affected by the remaining amount of the plating catalyst. That is, by performing a surface treatment on the upper surface of the insulating layer of the substrate and adjusting the surface state, it is possible to adjust the remaining amount of the plating catalyst and prevent a decrease in the insulation resistance between the circuits.
[0014]
The inventors have achieved a good surface condition by performing surface treatment of the insulating layer using ozone solution such as ozone water and ultraviolet irradiation in contrast to conventional desmear treatment using permanganic acid or chromic acid. It has been found to obtain.
In the ozone solution-ultraviolet irradiation treatment process in the wiring forming method of the present invention, the surface of the insulating layer is irradiated with ultraviolet rays while the ozone solution is in contact with the surface of the insulating layer formed on the substrate. Generated by irradiating not only the ozone in the ozone solution but also the oxygen generated from the ozone solution by irradiating the insulating layer surface with the ultraviolet ray while the insulating layer surface, the insulating layer surface and the ozone solution are in contact with each other. Oxygen radicals activate the surface of the insulating layer, the ozone solution activates the active groups on the surface of the insulating layer to generate polar groups, and the excessive amount given to the insulating layer by ultraviolet irradiation. It works synergistically with the action of suppressing heat damage given to the surface of the insulating layer by releasing heat to the ozone solution, effectively activating the surface of the insulating layer while suppressing the roughening of the surface of the insulating layer Can be made.
[0015]
An insulator having an unsaturated bond can be used as the material for the insulating layer, and examples thereof include resins such as epoxy resins, phenol resins, polyimide resins, polyamideimide resins, bismaleimide resins, unsaturated polyester resins, and silicon resins. it can.
The ozone concentration in the ozone solution is desirably 100 ppm or more. By setting the ozone concentration to 100 ppm or more, the ozone solution-ultraviolet irradiation treatment can be performed in a short time, and damage to the insulating layer can be reduced.
The contact time between the ozone solution and the insulating layer surface is preferably 4 to 20 minutes. If it is less than 4 minutes, activation may be insufficient even if the ozone concentration is 100 ppm, and if it exceeds 20 minutes, the insulating layer may be deteriorated.
The ozone solution usually uses water as a solvent, but can use an organic or inorganic polar solvent as a solvent. Examples of the organic polar solvent include alcohols such as methanol and ethanol, organic acids such as acetic acid, or a mixture of these with water or an alcohol solvent. Examples of the inorganic polar solvent include inorganic acids such as nitric acid, hydrochloric acid, and hydrofluoric acid.
[0016]
The irradiation amount of ultraviolet rays to be irradiated is desirably 1000 mJ / cm 2 or more. When the irradiation amount of ultraviolet rays is less than 1000 mJ / cm 2 , activation of the insulating layer surface may be insufficient when the ozone concentration of the ozone solution is low.
As a method of bringing the ozone solution into contact with the surface of the insulating layer, there are a method of immersing a substrate in the ozone solution, a method of spraying the ozone solution on the surface of the insulating layer, and the like.
In the invention forming method of the present invention, it is preferable to further perform an alkali solution treatment step of bringing the insulating layer surface into contact with a solution containing an alkali component after the ozone solution-ultraviolet irradiation step. Alkali components have a function of dissolving the insulating layer surface at the molecular level, and can remove more brittle parts on the insulating layer surface to expose more functional groups, thus improving the adhesion of the plating film used as wiring. To do.
As an alkali component, what has the function to melt | dissolve the insulating layer surface in a molecular level can be used, and sodium hydroxide, potassium hydroxide, lithium hydroxide, etc. are illustrated.
It is desirable that the solution containing the alkaline component further contains at least one of an anionic surfactant and a nonionic surfactant.
In the wiring formation method of the present invention, the surface of the insulating layer is suppressed by the ozone solution-ultraviolet irradiation treatment in the ozone solution-ultraviolet irradiation treatment process, and the increase in surface area is suppressed. Excessive application to the layer surface is suppressed.
[0017]
The amount of catalyst applied to the surface of the insulating layer in the catalyst application step is desirably 10 to 80 μg / dm 2 . When the amount of applied catalyst is less than 10 μg / dm 2 , the adhesion of the electroless plating film may be reduced when the ozone concentration of the ozone solution is low or the amount of ultraviolet irradiation is small in the ozone solution-ultraviolet irradiation treatment. When the applied amount of the catalyst is more than 80 μg / dm 2 , the insulation reliability between the wirings may be lowered when the distance between the wirings is 100 μm or less.
In the wiring formation method of the present invention, since excessive application of the catalyst to the surface of the insulating layer is suppressed in the catalyst application step, excessive catalyst may exist at the interface between the resist and the insulating layer in the resist formation step. A resist can be formed on the surface of the insulating layer in a suppressed state.
In the wiring formation method of the present invention, since the surface of the insulating layer is effectively activated by the ozone solution-ultraviolet irradiation treatment, the application of the catalyst is suppressed in the electroless plating treatment in the conductive layer formation step. Even if it adheres, it can ensure.
[0018]
【Example】
The wiring forming method of the present invention will be specifically described with reference to examples, comparative examples, reference examples, and reference comparative examples.
[0019]
(Reference Example 1)
A method for forming the plating film of Reference Example 1 will be described.
A glass epoxy substrate having a thickness of 0.6 mm was used as a base material. A dry film adhesive having a thickness of 50 μm was bonded to the substrate by a laminator, exposed to ultraviolet rays, and heated to be completely cured. This formed the insulating layer on the base material.
The ultraviolet ray for curing has a peak wavelength of 400 nm and is exposed at 1 to 3 J / cm 2 . The heating temperature was 120-140 ° C., and the heating time was 1-2 hours.
[0020]
The substrate on which the insulating layer was formed was immersed in ozone water having an ozone concentration of 100 ppm or more, and the insulating layer was irradiated with ultraviolet light while the substrate was immersed. The immersion time in ozone water was 4 to 20 minutes, and the irradiation amount of ultraviolet light was at least 1000 mJ / cm 2 or more. Thereafter, the substrate was immersed in the catalyst treatment liquid to adhere the palladium catalyst to the surface of the insulating layer.
Thereafter, the substrate was immersed in an electroless plating solution, and a copper plating film having a thickness of 25 μm or more was formed on the insulating layer.
Several substrates on which plating films were formed by the plating film forming method of Reference Example 1 were prepared.
[0021]
(Reference Comparative Example 1)
A method for forming the plating film of Reference Comparative Example 1 will be described.
An insulating layer was formed in the same manner as in Reference Example 1 using the same substrate as in Reference Example 1.
After the substrate formed with the insulating layer was treated with a permanganic acid solution to deposit a palladium catalyst on the surface of the insulating layer, a copper plating coating having a thickness equivalent to that of Reference Example 1 was formed on the surface of the insulating layer in the same manner as in Reference Example 1. . Several substrates on which plating films were formed by the method for forming a plating film of Reference Comparative Example 1 were prepared.
[0022]
(Reference Comparative Example 2)
A method for forming the plating film of Reference Comparative Example 2 will be described.
Using the same substrate as in Reference Example 1, after forming the insulating layer as in Reference Example 1, ultraviolet rays were irradiated in a gas atmosphere having an oxygen concentration of 5 to 100%. The amount of UV irradiation was the same as in Reference Example 1. Thereafter, a palladium catalyst is attached to the surface of the insulating layer using the same catalyst treatment liquid as in Reference Example 1, and then a copper plating film having the same thickness as that of Reference Example 1 is formed on the surface of the insulating layer in the same manner as in Reference Example 1. did. Several substrates on which plating films were formed by the plating film forming method of Reference Comparative Example 2 were prepared.
[0023]
(Reference evaluation)
Next, for each substrate, the adhesion strength between the copper plating film and the insulating layer was measured by peel strength measurement. Moreover, after etching copper plating, center average roughness (Ra) was measured with the surface roughness measuring apparatus. The amount of palladium catalyst on the insulating film was also measured. Table 1 shows the results of peel strength measurement, centerline average roughness (Ra) measurement, palladium adsorption amount and appearance.
[Table 1]
As a result, the peel strength of all the substrates satisfied 1.0 kN / m or more.
In the measurement of the center line average roughness (Ra), Reference Example 1 and Reference Comparative Example 2 were very smooth with 1.0 μm or less. In Reference Comparative Example 1, the roughness is increased to 5 to 6 μm by desmear treatment.
The amount of Pd on the base insulating material was 160 to 250 μg / dm 2 in Reference Comparative Example 1, whereas it was 25 to 50 μg / dm 2 and 30 to 30 in Reference Example 1 and Reference Comparative Example 2, respectively. It can be seen that the amount is 50 μg / dm 2 , which is about one-third to about one-tenth that of Reference Comparative Example 1.
From this, it is clear that the amount of catalyst applied can be suppressed by suppressing the roughening of the surface of the insulating layer.
As a result of observing the appearance of each substrate, in Reference Comparative Example 2, burns occurred on a part of the substrate, and plating was not deposited on the part that was severely burnt. In Reference Example 1, there was no problem in appearance. This is considered to be a result of the damage caused by the ultraviolet rays generated in the gas atmosphere as in Reference Comparative Example 2 being suppressed by the ozone solution.
[0025]
(Example 1)
An insulating layer was formed in the same manner as in Reference Example 1 using the same substrate as that in Reference Example 1 and the wiring formation method of Example 1.
The substrate on which the insulating layer was formed was immersed in ozone water having an ozone concentration of 100 ppm or more, and the insulating layer was irradiated with ultraviolet light while the substrate was immersed. The immersion time in ozone water was 4 to 20 minutes, and the irradiation amount of ultraviolet light was at least 1000 mJ / cm 2 or more. Thereafter, the substrate was immersed in the catalyst treatment liquid to adhere the palladium catalyst to the surface of the insulating layer.
Next, a resist film (dry film resist) was laminated with a laminator, and a wiring pattern was exposed and formed. As a result, comb patterns having wiring widths and intervals of 20, 40, and 60 μm were formed.
And the whole board | substrate was immersed in the electroless-plating liquid, the plating copper was deposited on the wiring part, the wiring was formed with the electroless copper plating layer, and the wiring board was manufactured.
[0026]
(Comparative Example 1)
The wiring formation method and wiring board of Comparative Example 1 will be described.
Using the same substrate as in Example 1, an insulating layer was formed in the same manner as in Example. The substrate on which the insulating layer was formed was treated with a permanganic acid solution to roughen the surface of the insulating layer (desmear treatment). After depositing a palladium catalyst on the surface of the insulating layer using the same catalyst treatment solution as in Example 1, a resist pattern was used to form a comb pattern having circuit widths and intervals of 20, 40, and 60 μm as in Example 1. Then, it was immersed in an electroless plating solution to deposit copper on the wiring part to form a copper-plated wiring, and a wiring board was manufactured.
[0027]
(Comparative Example 2)
The wiring formation method and wiring board of Comparative Example 2 will be described.
After an insulating layer was formed in the same manner as in Example 1 using the same substrate as in Example 1, ultraviolet rays were irradiated in a gas atmosphere having an oxygen concentration of 5 to 100%. The amount of UV irradiation was the same as in Example 1.
Thereafter, using the same catalyst treatment liquid as in Example 1, a palladium catalyst was attached to the insulating layer surface in the same manner as in Example 1, and a resist pattern was used to form a comb pattern with circuit widths and intervals of 20, 40, and 60 μm. It was formed and immersed in electroless copper plating to deposit copper on the wiring portion to form a copper plated wiring, and a wiring board was manufactured.
[0028]
(Evaluation)
For the substrates of Example 1, Comparative Example 1 and Comparative Example 2, an electrolytic corrosion test was conducted to evaluate the deterioration of the insulation resistance between circuits due to the plating catalyst remaining at the interface between the plating resist and the base insulating layer. The test was conducted in a constant temperature and humidity chamber at a temperature of 85 ° C. and a humidity of 85%, and the insulation resistance between the wirings was measured while applying a direct current of 100 V to each comb circuit pattern. Table 2 shows the results of the possibility of wiring formation and the results of the electrolytic corrosion test.
[Table 2]
In Table 2, L / S = O / O μm corresponds to the lower numerical value (60/60, etc.), L indicates the width of the wiring, and S indicates the width of the plating resist between the wirings. In Table 2, ◯ means that the wiring is well formed. For example, in the row of “60/60” in “Wiring availability”, the wiring line was well formed when the wiring was formed with a width of 60 μm with an interval of 60 μm. Is shown.
[0030]
As a result, with respect to Example 1, Comparative Example 1, and Comparative Example 2, wiring was formed on any wiring board. In the electrolytic corrosion test, the wiring board of Comparative Example 1 had all intervals of 20 μm, 40 μm, and 60 μm, and a short circuit was observed between the wirings after 1000 hours. In the wiring board of Example 1, In all patterns, the initial value was 10 12 Ω or more, and an insulation resistance between wirings of 10 12 Ω or more was obtained after 1000 hours. When the external appearance of each wiring board was observed after the electrolytic corrosion test, only a part of the wiring was peeled off from the wiring board of Comparative Example 2, and a disconnected part was seen.
[0031]
From the above, in the wiring forming method of Example 1, the insulating layer surface is effectively prevented from being roughened by irradiating the ultraviolet ray in a state where the insulating layer surface and the ozone solution are in contact with each other. Since the wiring is formed after the activation and the excessive application of the catalyst to the surface of the insulating layer is suppressed, it is possible to suppress the catalyst from remaining excessively between the wirings, and the adhesion force of the wiring ( It is clear that a wiring board in which deterioration of insulation resistance between wirings is suppressed while securing a peel strength of 1 kN / m or more can be manufactured.
[0032]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the insulation resistance deterioration between wiring can be suppressed, ensuring the adhesive force between wiring and an insulating layer.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a substrate by a general full additive method.
[Explanation of symbols]
10 Insulating
Claims (6)
オゾン溶液−紫外線照射処理が施された絶縁層表面に触媒を付与する触媒付与工程と、
触媒が付与された絶縁層表面に所定パターンのレジストを形成するレジスト形成工程と、
レジスト形成工程後、絶縁層表面に導電層を無電解めっきにより形成する導電層形成工程と、
を含むことを特徴とする配線形成方法。An ozone solution-ultraviolet irradiation treatment process in which the surface of the insulating layer formed on the substrate is brought into contact with the ozone solution to irradiate the surface of the insulating layer with ultraviolet rays;
A catalyst applying step for applying a catalyst to the surface of the insulating layer subjected to the ozone solution-ultraviolet irradiation treatment;
A resist forming step of forming a resist of a predetermined pattern on the surface of the insulating layer provided with the catalyst;
A conductive layer forming step of forming a conductive layer on the surface of the insulating layer by electroless plating after the resist forming step;
A wiring forming method comprising:
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| JP2003164048A JP2005005319A (en) | 2003-06-09 | 2003-06-09 | Method for forming wiring and wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003164048A JP2005005319A (en) | 2003-06-09 | 2003-06-09 | Method for forming wiring and wiring board |
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| JP2005005319A true JP2005005319A (en) | 2005-01-06 |
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| JP2003164048A Pending JP2005005319A (en) | 2003-06-09 | 2003-06-09 | Method for forming wiring and wiring board |
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| JP2008244139A (en) * | 2007-03-27 | 2008-10-09 | Hioki Ee Corp | Electric circuit board having metal pattern |
| WO2012020713A2 (en) | 2010-08-10 | 2012-02-16 | 日立化成工業株式会社 | Resin composition, cured resin product, wiring board, and manufacturing method for wiring board |
| JP2012036339A (en) * | 2010-08-10 | 2012-02-23 | Hitachi Chem Co Ltd | Resin composition, resin cured product, wiring board, and method for manufacturing the wiring board |
| US8784638B2 (en) | 2007-05-22 | 2014-07-22 | Toyota Jidosha Kabushiki Kaisha | Resin board to be subjected to ozone treatment, wiring board, and method of manufacturing the wiring board |
| WO2020130101A1 (en) * | 2018-12-20 | 2020-06-25 | 日立化成株式会社 | Wiring board and production method for same |
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2003
- 2003-06-09 JP JP2003164048A patent/JP2005005319A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008244139A (en) * | 2007-03-27 | 2008-10-09 | Hioki Ee Corp | Electric circuit board having metal pattern |
| US8784638B2 (en) | 2007-05-22 | 2014-07-22 | Toyota Jidosha Kabushiki Kaisha | Resin board to be subjected to ozone treatment, wiring board, and method of manufacturing the wiring board |
| WO2012020713A2 (en) | 2010-08-10 | 2012-02-16 | 日立化成工業株式会社 | Resin composition, cured resin product, wiring board, and manufacturing method for wiring board |
| JP2012036339A (en) * | 2010-08-10 | 2012-02-23 | Hitachi Chem Co Ltd | Resin composition, resin cured product, wiring board, and method for manufacturing the wiring board |
| WO2012020713A3 (en) * | 2010-08-10 | 2012-04-12 | 日立化成工業株式会社 | Resin composition, cured resin product, wiring board, and manufacturing method for wiring board |
| US11319457B2 (en) | 2010-08-10 | 2022-05-03 | Showa Denko Materials Co., Ltd | Support-provided insulating layer, laminate, and wiring board |
| WO2020130101A1 (en) * | 2018-12-20 | 2020-06-25 | 日立化成株式会社 | Wiring board and production method for same |
| CN113396241A (en) * | 2018-12-20 | 2021-09-14 | 昭和电工材料株式会社 | Wiring substrate and method for manufacturing same |
| TWI829833B (en) * | 2018-12-20 | 2024-01-21 | 日商力森諾科股份有限公司 | Wiring substrate and manufacturing method thereof |
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