JP2004531899A5 - - Google Patents
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- JP2004531899A5 JP2004531899A5 JP2003507879A JP2003507879A JP2004531899A5 JP 2004531899 A5 JP2004531899 A5 JP 2004531899A5 JP 2003507879 A JP2003507879 A JP 2003507879A JP 2003507879 A JP2003507879 A JP 2003507879A JP 2004531899 A5 JP2004531899 A5 JP 2004531899A5
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- Prior art keywords
- conductive material
- corner
- corners
- electrodes
- recess
- Prior art date
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- 239000004020 conductor Substances 0.000 claims 96
- 238000004377 microelectronic Methods 0.000 claims 23
- 239000000758 substrate Substances 0.000 claims 22
- 239000000463 material Substances 0.000 claims 14
- TWXTWZIUMCFMSG-UHFFFAOYSA-N nitride(3-) Chemical compound [N-3] TWXTWZIUMCFMSG-UHFFFAOYSA-N 0.000 claims 14
- 239000012530 fluid Substances 0.000 claims 9
- 230000001808 coupling Effects 0.000 claims 6
- 238000010168 coupling process Methods 0.000 claims 6
- 238000005859 coupling reaction Methods 0.000 claims 6
- 239000000126 substance Substances 0.000 claims 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N HCl Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N HF Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims 4
- 239000003792 electrolyte Substances 0.000 claims 3
- 230000001590 oxidative Effects 0.000 claims 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 3
- 229910052710 silicon Inorganic materials 0.000 claims 3
- 239000010703 silicon Substances 0.000 claims 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 2
- 229910002804 graphite Inorganic materials 0.000 claims 2
- 239000010439 graphite Substances 0.000 claims 2
- 229910052697 platinum Inorganic materials 0.000 claims 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims 2
- 229910052715 tantalum Inorganic materials 0.000 claims 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 2
- 230000005670 electromagnetic radiation Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000002210 silicon-based material Substances 0.000 claims 1
Claims (51)
ミクロ電子基板の導電物質に隣接して電解流体を配置し、導電物質は第1平面に第1表面、およびこの第1表面に凹部を有しており、凹部は第2平面における第2表面により境界決めされており、導電物質は更に第1表面と第2表面との間に角部を有しており、
第1および第2電極を電解流体に流体連通して位置決めし、電極のうちの少なくとも一方を電位源に結合することによって角部から導電物質の少なくとも一部を除去することを特徴とするミクロ電子基板を処理する方法。 In a method of processing a microelectronic substrate,
An electrolytic fluid is disposed adjacent to the conductive material of the microelectronic substrate, the conductive material having a first surface in the first plane and a recess in the first surface, the recess being defined by the second surface in the second plane. Bounded, the conductive material further has a corner between the first surface and the second surface;
A microelectron comprising: positioning first and second electrodes in fluid communication with an electrolytic fluid; and removing at least a portion of a conductive material from a corner by coupling at least one of the electrodes to a potential source. A method of processing a substrate.
前記角部から導電物質の少なくとも一部を除去することは、
導電物質の角部のところで電気信号を受信し、
電気信号を導電物質に通すことにより角部のところの導電物質の少なくとも一部を酸化し、
導電物質の酸化部分を化学エッチング剤にさらすことを含むことを特徴とする請求項1に記載の方法。 Further comprising transmitting electrical signals from the first and second electrodes spaced from the microelectronic substrate ;
Removing at least a portion of the conductive material from the corner,
Receive electrical signals at the corners of conductive materials,
Oxidize at least part of the conductive material at the corners by passing an electrical signal through the conductive material,
The method of claim 1 including exposing the oxidized portion of the conductive material to a chemical etchant.
角部から導電物質の少なくとも一部を除去する前に概ね非導電性の層の少なくとも一部を除去して導電物質の角部を露出させることを更に含むことを特徴とする請求項1に記載の方法。 Disposing a generally non-conductive layer on the conductive material;
The method of claim 1, further comprising removing at least a portion of the generally non-conductive layer to expose a corner of the conductive material before removing at least a portion of the conductive material from the corner. the method of.
前記酸化物層上に窒化物層を配置し、
角部から導電物質を除去する前に窒化物層の少なくとも一部および酸化物層の一部を除去して導電物質の角部を露出させることを更に含むことを特徴とする請求項1に記載の方法。 An oxide layer is disposed on the conductive material;
A nitride layer is disposed on the oxide layer;
The method of claim 1, further comprising removing at least a portion of the nitride layer and a portion of the oxide layer to expose the corners of the conductive material before removing the conductive material from the corners. the method of.
ミクロ電子基板の導電物質に隣接して概ね非導電性の物質を配置し、
概ね非導電性の物質を通って導電物質の中へ延びる凹部を形成し、この凹部は導電物質と概ね非導電性の物質との間の界面に少なくとも隣接して角部を構成しており、
角部を電位に露出させることによって角部から導電物質の少なくとも一部を除去して角部を少なくとも部分的に鈍くすることを含むことを特徴とするミクロ電子基板を処理する方法。 In a method of processing a microelectronic substrate,
A non-conductive material is generally placed adjacent to the conductive material of the microelectronic substrate,
Forming a recess extending through the generally nonconductive material into the conductive material, the recess forming a corner at least adjacent to the interface between the conductive material and the generally nonconductive material;
A method of processing a microelectronic substrate comprising exposing at least a portion of a conductive material from a corner by exposing the corner to an electrical potential to at least partially blunt the corner.
導電物質の角部のところで電気信号を受信し、
電気信号を導電物質に通すことにより角部のところの導電物質の少なくとも一部を酸化し、
導電物質の酸化された部分を化学エッチング剤にさらすことを更に含むことを特徴とする請求項20に記載の方法。 An electrical signal is transmitted from an electrode spaced from the microelectronic substrate,
Receive electrical signals at the corners of conductive materials,
Oxidize at least part of the conductive material at the corners by passing an electrical signal through the conductive material,
21. The method of claim 20, further comprising exposing the oxidized portion of the conductive material to a chemical etchant.
前記酸化物層上に窒化物層を配置し、
角部から導電物質の少なくとも一部を除去する前に窒化物層の少なくとも一部および酸化物層の一部を除去して導電物質の角部を露出させることを更に含むことを特徴とする請求項20に記載の方法。 An oxide layer is disposed on the conductive material;
A nitride layer is disposed on the oxide layer;
The method further comprises removing at least a portion of the nitride layer and a portion of the oxide layer to remove a corner of the conductive material before removing at least a portion of the conductive material from the corner. Item 21. The method according to Item 20.
ミクロ電子基板のドープされたシリコン物質上に酸化物層を形成し、
前記酸化物層上に窒化物層を配置し、
窒化物層および酸化物層を通って導電物質の中へ延びる凹部をエッチングし、
凹部に近接した窒化物層および酸化物層の一部を除去して導電物質の角部を露出させ、 導電物質の角部に隣接して電解流体を配置し、
ミクロ電子基板に近接し且つそこから間隔を隔てて第1電極および第2電極を位置決めし、これらの電極のうちの少なくとも一方を電位源に結合することによって角部のところの導電物質の少なくとも一部を酸化し、
酸化された物質をエッチング剤にさらすことによって酸化された物質の少なくとも一部を除去し、
角部を丸くすることによって物質を角部から除去する速度を減じて少なくとも一方の電極から角部までの電流の流れを減少させることを含むことを特徴とするミクロ電子基板を処理する方法。 In a method of processing a microelectronic substrate,
Forming an oxide layer on the doped silicon material of the microelectronic substrate;
A nitride layer is disposed on the oxide layer;
Etching recesses extending through the nitride and oxide layers into the conductive material;
Removing a portion of the nitride and oxide layers adjacent to the recess to expose the corners of the conductive material, and placing the electrolytic fluid adjacent to the corners of the conductive material;
At least one of the conductive materials at the corners is positioned by positioning the first and second electrodes proximate to and spaced from the microelectronic substrate and coupling at least one of these electrodes to a potential source. Oxidize part
Removing at least a portion of the oxidized material by exposing the oxidized material to an etchant;
A method of processing a microelectronic substrate, comprising reducing the current flow from at least one electrode to a corner by reducing the rate at which material is removed from the corner by rounding the corner.
ミクロ電子基板の導電物質に凹部を形成し、この凹部は孔と導電物質の平面との交差点に角部を構成しており、
凹部に導電性ミクロ電子特徴を形成し、
凹部により構成される角部を丸くすることによって導電性ミクロ電子特徴からの電磁放射を制御し、角部を丸くすることは電位源を角部に電気的に結合して導電物質を酸化し、酸化された物質をエッチング剤にさらすことによって角部から酸化された物質を除去することを含むことを特徴とするミクロ電子基板を処理する方法。 In a method of processing a microelectronic substrate,
A recess is formed in the conductive material of the microelectronic substrate, and this recess forms a corner at the intersection of the hole and the plane of the conductive material,
Forming conductive microelectronic features in the recesses,
Controlling electromagnetic radiation from conductive microelectronic features by rounding the corners constituted by the recesses, rounding the corners electrically couples the potential source to the corners to oxidize the conductive material, A method of processing a microelectronic substrate comprising removing oxidized material from a corner by exposing the oxidized material to an etchant.
導電物質の角部のところで電気信号を受信し、
電気信号を導電物質に通すことによって角部のところの導電物質の少なくとも一部を酸化し、
導電物質の酸化された部分を化学エッチング剤にさらすことを更に含むことを特徴とする請求項41に記載の方法。 An electrical signal is transmitted from an electrode spaced from the microelectronic substrate,
Receive electrical signals at the corners of conductive materials,
Oxidize at least part of the conductive material at the corners by passing an electrical signal through the conductive material,
42. The method of claim 41, further comprising exposing the oxidized portion of the conductive material to a chemical etchant.
角部から導電物質の少なくとも一部を除去する前に、非導電層の少なくとも一部を除去して導電物質の角部を露出されることを更に含むことを特徴とする請求項41に記載の方法。 Placing a non-conductive layer on conductive material,
42. The method of claim 41, further comprising removing at least a portion of the non-conductive layer to expose a corner of the conductive material before removing at least a portion of the conductive material from the corner. Method.
前記酸化物層上に窒化物層を配置し、
角部から導電物質の少なくとも一部を除去する前に、窒化物層の少なくとも一部および酸化物層の一部を除去して導電物質の角部を露出させることを更に含むことを特徴とする請求項41に記載の方法。 An oxide layer is disposed on the conductive material;
A nitride layer is disposed on the oxide layer;
The method further includes removing at least a portion of the nitride layer and a portion of the oxide layer to expose a corner portion of the conductive material before removing at least a portion of the conductive material from the corner portion. 42. The method of claim 41.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/887,767 US7094131B2 (en) | 2000-08-30 | 2001-06-21 | Microelectronic substrate having conductive material with blunt cornered apertures, and associated methods for removing conductive material |
US09/888,002 US7160176B2 (en) | 2000-08-30 | 2001-06-21 | Methods and apparatus for electrically and/or chemically-mechanically removing conductive material from a microelectronic substrate |
US09/888,084 US7112121B2 (en) | 2000-08-30 | 2001-06-21 | Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a microelectronic substrate |
PCT/US2002/019496 WO2003001582A2 (en) | 2001-06-21 | 2002-06-20 | Microelectronic substrate having conductive material with blunt cornered apertures, and associated methods for removing conductive material |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004531899A JP2004531899A (en) | 2004-10-14 |
JP2004531899A5 true JP2004531899A5 (en) | 2008-08-07 |
Family
ID=27420529
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003507879A Pending JP2004531899A (en) | 2001-06-21 | 2002-06-20 | Method and apparatus for electrically, mechanically and / or chemically removing conductive materials from microelectronic substrates |
JP2003507878A Expired - Fee Related JP4446271B2 (en) | 2001-06-21 | 2002-06-20 | Method and apparatus for electrically, mechanically and / or chemically removing a conductive material from a microelectronic substrate |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003507878A Expired - Fee Related JP4446271B2 (en) | 2001-06-21 | 2002-06-20 | Method and apparatus for electrically, mechanically and / or chemically removing a conductive material from a microelectronic substrate |
Country Status (6)
Country | Link |
---|---|
EP (2) | EP1399957A2 (en) |
JP (2) | JP2004531899A (en) |
KR (2) | KR100663662B1 (en) |
CN (1) | CN100356523C (en) |
AU (1) | AU2002316303A1 (en) |
WO (2) | WO2003001581A2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6848970B2 (en) | 2002-09-16 | 2005-02-01 | Applied Materials, Inc. | Process control in electrochemically assisted planarization |
US6837983B2 (en) * | 2002-01-22 | 2005-01-04 | Applied Materials, Inc. | Endpoint detection for electro chemical mechanical polishing and electropolishing processes |
US7842169B2 (en) | 2003-03-04 | 2010-11-30 | Applied Materials, Inc. | Method and apparatus for local polishing control |
US7998335B2 (en) | 2005-06-13 | 2011-08-16 | Cabot Microelectronics Corporation | Controlled electrochemical polishing method |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01241129A (en) * | 1988-03-23 | 1989-09-26 | Toshiba Corp | Manufacture of semiconductor device |
KR960006714B1 (en) * | 1990-05-28 | 1996-05-22 | 가부시끼가이샤 도시바 | Semiconductor device fabrication process |
JPH10189909A (en) * | 1996-12-27 | 1998-07-21 | Texas Instr Japan Ltd | Dielectric capacitor and dielectric memory and manufacture thereof |
US5911619A (en) * | 1997-03-26 | 1999-06-15 | International Business Machines Corporation | Apparatus for electrochemical mechanical planarization |
WO1999026758A1 (en) * | 1997-11-25 | 1999-06-03 | John Hopkins University | Electrochemical-control of abrasive polishing and machining rates |
KR100280107B1 (en) * | 1998-05-07 | 2001-03-02 | 윤종용 | How to form trench isolation |
US6143155A (en) * | 1998-06-11 | 2000-11-07 | Speedfam Ipec Corp. | Method for simultaneous non-contact electrochemical plating and planarizing of semiconductor wafers using a bipiolar electrode assembly |
US6121152A (en) * | 1998-06-11 | 2000-09-19 | Integrated Process Equipment Corporation | Method and apparatus for planarization of metallized semiconductor wafers using a bipolar electrode assembly |
JP4513145B2 (en) * | 1999-09-07 | 2010-07-28 | ソニー株式会社 | Semiconductor device manufacturing method and polishing method |
US6797623B2 (en) * | 2000-03-09 | 2004-09-28 | Sony Corporation | Methods of producing and polishing semiconductor device and polishing apparatus |
US6867448B1 (en) * | 2000-08-31 | 2005-03-15 | Micron Technology, Inc. | Electro-mechanically polished structure |
JP2002093761A (en) * | 2000-09-19 | 2002-03-29 | Sony Corp | Polishing method, polishing system, plating method and plating system |
US6736952B2 (en) * | 2001-02-12 | 2004-05-18 | Speedfam-Ipec Corporation | Method and apparatus for electrochemical planarization of a workpiece |
-
2002
- 2002-06-20 EP EP02746596A patent/EP1399957A2/en not_active Withdrawn
- 2002-06-20 WO PCT/US2002/019495 patent/WO2003001581A2/en active Application Filing
- 2002-06-20 EP EP02744464A patent/EP1399956A2/en not_active Withdrawn
- 2002-06-20 JP JP2003507879A patent/JP2004531899A/en active Pending
- 2002-06-20 CN CNB028122380A patent/CN100356523C/en not_active Expired - Fee Related
- 2002-06-20 WO PCT/US2002/019496 patent/WO2003001582A2/en active Application Filing
- 2002-06-20 KR KR1020037016758A patent/KR100663662B1/en not_active IP Right Cessation
- 2002-06-20 AU AU2002316303A patent/AU2002316303A1/en not_active Abandoned
- 2002-06-20 JP JP2003507878A patent/JP4446271B2/en not_active Expired - Fee Related
- 2002-06-20 KR KR1020037016756A patent/KR100598477B1/en not_active IP Right Cessation
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