EP1341218A3 - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

Info

Publication number
EP1341218A3
EP1341218A3 EP02257693A EP02257693A EP1341218A3 EP 1341218 A3 EP1341218 A3 EP 1341218A3 EP 02257693 A EP02257693 A EP 02257693A EP 02257693 A EP02257693 A EP 02257693A EP 1341218 A3 EP1341218 A3 EP 1341218A3
Authority
EP
European Patent Office
Prior art keywords
film
dielectric
forming
capacitor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP02257693A
Other languages
German (de)
French (fr)
Other versions
EP1341218B1 (en
EP1341218A2 (en
Inventor
Hideaki c/o Fujitsu Limited Kikuchi
Genichi c/o Fujitsu Limited Komuro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to EP05012335A priority Critical patent/EP1592046B1/en
Publication of EP1341218A2 publication Critical patent/EP1341218A2/en
Publication of EP1341218A3 publication Critical patent/EP1341218A3/en
Application granted granted Critical
Publication of EP1341218B1 publication Critical patent/EP1341218B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B53/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/55Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B53/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/55Capacitors with a dielectric comprising a perovskite structure material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Materials Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

There is provided a semiconductor device manufacturing method having a ferroelectric or high- dielectric capacitor, which comprises the steps of forming an underlying insulating film (8) over a semiconductor substrate (1), forming a first conductive (15) film on the underlying insulating film, forming a dielectric film (16) consisting of ferroelectric material and high-dielectric material on the first conductive film (15), forming a second conductive film (17) on the dielectric film (16), etching selectively the second conductive film (17) in a first atmosphere containing bromine to form a capacitor upper electrode (17a), etching selectively the dielectric film in a second atmosphere containing chlorine to form a capacitor dielectric film (16a), and etching selectively the first conductive film in a third atmosphere containing bromine to form a capacitor lower electrode (15a).
EP02257693A 2002-02-28 2002-11-06 Semiconductor device manufacturing method Expired - Fee Related EP1341218B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05012335A EP1592046B1 (en) 2002-02-28 2002-11-06 Semiconductor device manufacturing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002054440 2002-02-28
JP2002054440A JP2003257942A (en) 2002-02-28 2002-02-28 Method for manufacturing semiconductor device

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP05012335A Division EP1592046B1 (en) 2002-02-28 2002-11-06 Semiconductor device manufacturing method
EP05012335.5 Division-Into 2005-06-08

Publications (3)

Publication Number Publication Date
EP1341218A2 EP1341218A2 (en) 2003-09-03
EP1341218A3 true EP1341218A3 (en) 2004-08-11
EP1341218B1 EP1341218B1 (en) 2012-01-11

Family

ID=27678569

Family Applications (2)

Application Number Title Priority Date Filing Date
EP02257693A Expired - Fee Related EP1341218B1 (en) 2002-02-28 2002-11-06 Semiconductor device manufacturing method
EP05012335A Expired - Fee Related EP1592046B1 (en) 2002-02-28 2002-11-06 Semiconductor device manufacturing method

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP05012335A Expired - Fee Related EP1592046B1 (en) 2002-02-28 2002-11-06 Semiconductor device manufacturing method

Country Status (6)

Country Link
US (1) US6682944B2 (en)
EP (2) EP1341218B1 (en)
JP (1) JP2003257942A (en)
KR (1) KR100832683B1 (en)
DE (1) DE60238952D1 (en)
TW (1) TWI267916B (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4865978B2 (en) * 2002-02-28 2012-02-01 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
WO2004093193A1 (en) * 2003-04-15 2004-10-28 Fujitsu Limited Method for fabricating semiconductor device
US7105400B2 (en) * 2003-09-30 2006-09-12 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device
JP3785170B2 (en) * 2003-12-01 2006-06-14 株式会社東芝 Semiconductor device and manufacturing method thereof
JP4551725B2 (en) * 2004-09-13 2010-09-29 Okiセミコンダクタ株式会社 Manufacturing method of semiconductor device
JP2006093451A (en) * 2004-09-24 2006-04-06 Toshiba Corp Semiconductor device
JP2006147771A (en) * 2004-11-18 2006-06-08 Oki Electric Ind Co Ltd Ferroelectric memory and its manufacturing method
KR100663356B1 (en) * 2005-02-14 2007-01-02 삼성전자주식회사 Methods of fabricating feroelectric memory device having partially chemical mechanical polishing process
JP4746357B2 (en) * 2005-06-09 2011-08-10 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
JP4882548B2 (en) * 2006-06-30 2012-02-22 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
JP2008028229A (en) * 2006-07-24 2008-02-07 Seiko Epson Corp Ferroelectric memory manufacturing method
KR101110802B1 (en) 2007-03-20 2012-02-24 후지쯔 세미컨덕터 가부시키가이샤 Process for producing semiconductor device
JP5245383B2 (en) * 2007-12-11 2013-07-24 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
JP5510162B2 (en) * 2010-07-30 2014-06-04 日立金属株式会社 Method for manufacturing piezoelectric thin film wafer, piezoelectric thin film element, and piezoelectric thin film device
US9837605B2 (en) 2013-08-16 2017-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell having resistance variable film and method of making the same
US9224592B2 (en) * 2013-09-12 2015-12-29 Texas Intruments Incorporated Method of etching ferroelectric capacitor stack

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0725430A2 (en) * 1995-02-03 1996-08-07 Matsushita Electronics Corporation Method of manufacturing semiconductor device having capacitor
EP0786805A2 (en) * 1996-01-26 1997-07-30 Matsushita Electronics Corporation Method of plasma etching a film made of one of a ferroelectric material, high dielectric constant material or platinum
WO1999036956A1 (en) * 1998-01-13 1999-07-22 Applied Materials, Inc. Etching methods for anisotropic platinum profile
US6100201A (en) * 1997-03-05 2000-08-08 Nec Corporation Method of forming a semiconductor memory device
WO2000049649A2 (en) * 1999-02-17 2000-08-24 Applied Materials, Inc. Method for preventing corrosion of a dielectric material

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3122579B2 (en) 1994-07-27 2001-01-09 シャープ株式会社 Pt film etching method
US6232174B1 (en) * 1998-04-22 2001-05-15 Sharp Kabushiki Kaisha Methods for fabricating a semiconductor memory device including flattening of a capacitor dielectric film
KR100319879B1 (en) 1998-05-28 2002-08-24 삼성전자 주식회사 Method of forming lower electrode of capacitor using dry etching of platinum group metal film
JP2001036024A (en) 1999-07-16 2001-02-09 Nec Corp Capacitor and manufacture thereof
KR100309077B1 (en) * 1999-07-26 2001-11-01 윤종용 Triple metal 1t/1c ferroelectric capacitor and method for fabricating thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0725430A2 (en) * 1995-02-03 1996-08-07 Matsushita Electronics Corporation Method of manufacturing semiconductor device having capacitor
EP0786805A2 (en) * 1996-01-26 1997-07-30 Matsushita Electronics Corporation Method of plasma etching a film made of one of a ferroelectric material, high dielectric constant material or platinum
US6100201A (en) * 1997-03-05 2000-08-08 Nec Corporation Method of forming a semiconductor memory device
WO1999036956A1 (en) * 1998-01-13 1999-07-22 Applied Materials, Inc. Etching methods for anisotropic platinum profile
WO2000049649A2 (en) * 1999-02-17 2000-08-24 Applied Materials, Inc. Method for preventing corrosion of a dielectric material

Also Published As

Publication number Publication date
KR100832683B1 (en) 2008-05-27
EP1592046B1 (en) 2011-01-12
DE60238952D1 (en) 2011-02-24
EP1592046A2 (en) 2005-11-02
US6682944B2 (en) 2004-01-27
TWI267916B (en) 2006-12-01
EP1341218B1 (en) 2012-01-11
EP1592046A3 (en) 2008-05-07
JP2003257942A (en) 2003-09-12
EP1341218A2 (en) 2003-09-03
KR20030071475A (en) 2003-09-03
US20030166326A1 (en) 2003-09-04

Similar Documents

Publication Publication Date Title
EP1341218A3 (en) Semiconductor device manufacturing method
EP1017096A3 (en) Method of fabricating semiconductor memory device
EP1975978A3 (en) Semiconductor device manufacturing method
EP1189262A3 (en) Semiconductor device comprising a capacitor and method of manufacturing the same
EP1313141A3 (en) Semiconductor device and method of manufacturing the same
TW200505033A (en) Capacitor and method of fabricating the same
EP1022786A3 (en) Semiconductor device and process for production thereof
EP2312664A3 (en) Electronic devices
EP0738009A3 (en) Semiconductor device having capacitor
EP0920061A3 (en) Capacitor and corresponding memory device, and method of manufacturing the same
WO2006023026A3 (en) Method of forming a semiconductor device and structure thereof
EP1061573A3 (en) Semiconductor device and method of manufacturing the same
EP0989615A3 (en) Semiconductor device with capacitor and manufacturing method thereof
EP1150344A3 (en) Semiconductor device having ferroelectric thin film and fabricating method therefor
EP1471566A3 (en) Semiconductor device and method for fabricating the same
EP0949682A3 (en) Ferroelectric memory device with improved ferroelectric capacitor characteristics
EP1237194A3 (en) Ferroelectric memory device and method for fabricating the same
WO2003046974A3 (en) Capacitor and a method for producing a capacitor
EP1376662A3 (en) Semiconductor device and method for fabricating the same
EP1326277A3 (en) Semiconductor device and method of manufacturing the same
EP1148543A3 (en) Semiconductor device and process of manufacturing the same
WO2002029865A3 (en) Method of manufacturing a semiconductor component and semiconductor component thereof
EP1420436A3 (en) Method of manufacturing high precision integrated circuit capacitors
EP1267405A3 (en) Semiconductor device and method for fabricating the same
EP0769813A3 (en) Integrated circuit with planarized dielectric layer between successive polysilicon layers

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SK TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SK TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

17P Request for examination filed

Effective date: 20041104

17Q First examination report despatched

Effective date: 20050202

AKX Designation fees paid

Designated state(s): DE FR GB IT

RBV Designated contracting states (corrected)

Designated state(s): DE FR GB IT

17Q First examination report despatched

Effective date: 20050202

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: FUJITSU MICROELECTRONICS LIMITED

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: FUJITSU SEMICONDUCTOR LIMITED

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 60241941

Country of ref document: DE

Effective date: 20120308

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120111

26N No opposition filed

Effective date: 20121012

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 60241941

Country of ref document: DE

Effective date: 20121012

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20121106

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20130731

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20121106

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20121130

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20171031

Year of fee payment: 16

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 60241941

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190601