JP2004511933A - デジタル移相器 - Google Patents

デジタル移相器 Download PDF

Info

Publication number
JP2004511933A
JP2004511933A JP2002533474A JP2002533474A JP2004511933A JP 2004511933 A JP2004511933 A JP 2004511933A JP 2002533474 A JP2002533474 A JP 2002533474A JP 2002533474 A JP2002533474 A JP 2002533474A JP 2004511933 A JP2004511933 A JP 2004511933A
Authority
JP
Japan
Prior art keywords
clock signal
delay
signal
clk
delay line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002533474A
Other languages
English (en)
Japanese (ja)
Inventor
ヤング，スティーブン・ピィ
ローグ，ジョン・ディ
パーシー，アンドルー・ケイ
ゲティン，エフ・エリック
チン，アルビン・ワイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/684,540 external-priority patent/US6775342B1/en
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of JP2004511933A publication Critical patent/JP2004511933A/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2002533474A 2000-10-06 2001-10-05 デジタル移相器 Pending JP2004511933A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/684,540 US6775342B1 (en) 1998-06-22 2000-10-06 Digital phase shifter
PCT/US2001/031450 WO2002029975A2 (fr) 2000-10-06 2001-10-05 Dephaseur numerique

Publications (1)

Publication Number Publication Date
JP2004511933A true JP2004511933A (ja) 2004-04-15

Family

ID=24748471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002533474A Pending JP2004511933A (ja) 2000-10-06 2001-10-05 デジタル移相器

Country Status (4)

Country Link
EP (1) EP1323234B1 (fr)
JP (1) JP2004511933A (fr)
CA (1) CA2424706C (fr)
WO (1) WO2002029975A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007251371A (ja) * 2006-03-14 2007-09-27 Nec Electronics Corp スペクトラム拡散クロック制御装置及びスペクトラム拡散クロック発生装置
JP2013078129A (ja) * 2007-06-11 2013-04-25 Sk Hynix Inc 周波数調整装置及びそれを含むｄｌｌ回路

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003098414A1 (fr) * 2002-05-16 2003-11-27 Infineon Technologies Ag Appareil permettant de regler la phase d'un signal numerique
KR100541548B1 (ko) 2003-09-08 2006-01-11 삼성전자주식회사 대역 확산 클럭 발생회로 및 방법
SG120185A1 (en) 2004-08-30 2006-03-28 Micron Technology Inc Delay lock loop phase glitch error filter
DE602005012605D1 (de) 2004-12-03 2009-03-19 Nxp Bv Verwaltung von Anzapfstellen in einer digitalen Verzögerungsleitung
JP4846486B2 (ja) * 2006-08-18 2011-12-28 富士通株式会社 情報処理装置およびその制御方法
KR102632074B1 (ko) * 2021-03-16 2024-02-02 한국전자통신연구원 부궤환 루프 구조의 위상 복조기

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6289068B1 (en) * 1998-06-22 2001-09-11 Xilinx, Inc. Delay lock loop with clock phase shifter
US6043717A (en) * 1998-09-22 2000-03-28 Intel Corporation Signal synchronization and frequency synthesis system configurable as PLL or DLL

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007251371A (ja) * 2006-03-14 2007-09-27 Nec Electronics Corp スペクトラム拡散クロック制御装置及びスペクトラム拡散クロック発生装置
JP2013078129A (ja) * 2007-06-11 2013-04-25 Sk Hynix Inc 周波数調整装置及びそれを含むｄｌｌ回路

Also Published As

Publication number Publication date
EP1323234B1 (fr) 2011-12-07
CA2424706C (fr) 2010-12-14
EP1323234A2 (fr) 2003-07-02
WO2002029975A3 (fr) 2003-03-27
WO2002029975A2 (fr) 2002-04-11
CA2424706A1 (fr) 2002-04-11

Similar Documents

Publication Publication Date Title
US6775342B1 (en) Digital phase shifter
US7295053B2 (en) Delay-locked loop circuits
JP4056388B2 (ja) 同期マルチ出力デジタルクロックマネージャ
US6225840B1 (en) Clock generation circuit which reduces a transition time period and semiconductor device using the same
US6240152B1 (en) Apparatus and method for switching frequency modes in a phase locked loop system
US7276944B2 (en) Clock generation circuit and clock generation method
KR101165491B1 (ko) 다중 기준 클럭 신시사이저
JP3323207B2 (ja) 周波数―電圧変換回路、遅延量判定回路、周波数―電圧変換回路を備えたシステム、周波数―電圧変換回路の入出力特性を調整する方法、および周波数―電圧変換回路の入出力特性を自動調整する装置
US7282971B2 (en) Digital delay lock loop
US7321249B2 (en) Oscillator, frequency multiplier, and test apparatus
US10790837B1 (en) Self-tuning digital clock generator
CA2424706C (fr) Dephaseur numerique
US6967536B2 (en) Phase-locked loop circuit reducing steady state phase error
US7564283B1 (en) Automatic tap delay calibration for precise digital phase shift
KR101000486B1 (ko) 지연고정 루프 기반의 주파수 체배기
KR100884642B1 (ko) 자가 보정 기능을 갖는 지연 고정 루프 기반의 주파수 체배장치 및 방법
US7073086B2 (en) System for controlling a tunable delay by transferring a signal from a first plurality of points along a first propagating circuit to a second plurality of points along a second propagating circuit
JP4686108B2 (ja) 同期を有するディジタルクロック逓倍器および分周器
WO2004010583A1 (fr) Commande de courant de fuite de condensateur de filtre a boucle
JPH1141095A (ja) クロック生成回路
JP2004062578A (ja) 多相出力クロック発生回路
JP2003218691A (ja) ディレイロックドループ回路

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040917

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20061101

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070306

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20070731