JP2004500608A - ユニバーサルリソースアクセスコントローラ - Google Patents

ユニバーサルリソースアクセスコントローラ Download PDF

Info

Publication number
JP2004500608A
JP2004500608A JP2000582896A JP2000582896A JP2004500608A JP 2004500608 A JP2004500608 A JP 2004500608A JP 2000582896 A JP2000582896 A JP 2000582896A JP 2000582896 A JP2000582896 A JP 2000582896A JP 2004500608 A JP2004500608 A JP 2004500608A
Authority
JP
Japan
Prior art keywords
memory
command
controller
access
resource
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000582896A
Other languages
English (en)
Japanese (ja)
Inventor
ストラコブスキー・ヘンリー
シャベルスキー・ピオトル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/439,544 external-priority patent/US6532505B1/en
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of JP2004500608A publication Critical patent/JP2004500608A/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
JP2000582896A 1998-11-16 1999-11-15 ユニバーサルリソースアクセスコントローラ Pending JP2004500608A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10893098P 1998-11-16 1998-11-16
US09/439,544 US6532505B1 (en) 1999-11-12 1999-11-12 Universal resource access controller
PCT/US1999/026994 WO2000029955A1 (en) 1998-11-16 1999-11-15 Universal resource access controller

Publications (1)

Publication Number Publication Date
JP2004500608A true JP2004500608A (ja) 2004-01-08

Family

ID=26806431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000582896A Pending JP2004500608A (ja) 1998-11-16 1999-11-15 ユニバーサルリソースアクセスコントローラ

Country Status (6)

Country Link
JP (1) JP2004500608A (zh)
KR (1) KR100710531B1 (zh)
CN (1) CN1311357C (zh)
DE (1) DE19983738T1 (zh)
GB (1) GB2361561B (zh)
WO (1) WO2000029955A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005158076A (ja) * 2003-11-25 2005-06-16 Agere Systems Inc コンピューティング・システムにおける周辺装置用ユニバーサル・コントローラ
JP2007524146A (ja) * 2003-06-30 2007-08-23 レイセオン・カンパニー 効率的なメモリ制御装置
JP2010262537A (ja) * 2009-05-08 2010-11-18 Canon Inc メモリ制御回路
JP2016520226A (ja) * 2013-05-16 2016-07-11 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 領域特有のメモリアクセススケジューリングを有するメモリシステム

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL137085A (en) 2000-06-29 2004-08-31 Eci Telecom Ltd Method for effective utilizing of shared resources in computerized systems
CN100445954C (zh) * 2004-12-25 2008-12-24 鸿富锦精密工业（深圳）有限公司 控管服务使用资源的系统及方法
DE102010047718A1 (de) * 2010-10-07 2012-04-12 Infineon Technologies Ag Vorrichtung und Verfahren zum Formatieren und Vorauswählen von Trace Daten
US10394711B2 (en) * 2016-11-30 2019-08-27 International Business Machines Corporation Managing lowest point of coherency (LPC) memory using a service layer adapter
KR102540964B1 (ko) * 2018-02-12 2023-06-07 삼성전자주식회사 입출력 장치의 활용도 및 성능을 조절하는 메모리 컨트롤러, 애플리케이션 프로세서 및 메모리 컨트롤러의 동작
CN112699067B (zh) * 2021-01-04 2024-05-14 瑞芯微电子股份有限公司 一种指令寻址方法及装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4354225A (en) * 1979-10-11 1982-10-12 Nanodata Computer Corporation Intelligent main store for data processing systems
US4803623A (en) * 1986-10-31 1989-02-07 Honeywell Bull Inc. Universal peripheral controller self-configuring bootloadable ramware
JPH04354225A (ja) * 1991-05-31 1992-12-08 Nec Corp 交換システムの装置間通信制御方式
US5878240A (en) * 1995-05-11 1999-03-02 Lucent Technologies, Inc. System and method for providing high speed memory access in a multiprocessor, multimemory environment
JP4803623B2 (ja) * 2001-07-04 2011-10-26 旭サナック株式会社 エアースプレイハンドガン

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007524146A (ja) * 2003-06-30 2007-08-23 レイセオン・カンパニー 効率的なメモリ制御装置
JP4838120B2 (ja) * 2003-06-30 2011-12-14 レイセオン カンパニー 効率的なメモリ制御装置
JP2005158076A (ja) * 2003-11-25 2005-06-16 Agere Systems Inc コンピューティング・システムにおける周辺装置用ユニバーサル・コントローラ
JP2010262537A (ja) * 2009-05-08 2010-11-18 Canon Inc メモリ制御回路
JP2016520226A (ja) * 2013-05-16 2016-07-11 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 領域特有のメモリアクセススケジューリングを有するメモリシステム

Also Published As

Publication number Publication date
DE19983738T1 (de) 2002-03-14
WO2000029955A1 (en) 2000-05-25
GB2361561B (en) 2003-10-29
KR20010086034A (ko) 2001-09-07
KR100710531B1 (ko) 2007-04-23
GB2361561A (en) 2001-10-24
GB0111925D0 (en) 2001-07-04
CN1311357C (zh) 2007-04-18
CN1354854A (zh) 2002-06-19
WO2000029955A8 (en) 2000-09-14
WO2000029955A9 (en) 2000-10-26

Similar Documents

Publication Publication Date Title
JP4472186B2 (ja) 外部デバイスへのアクセスを優先順序付けるための方法および装置
JP4695761B2 (ja) コマンド再順序付けシステム
US6526484B1 (en) Methods and apparatus for reordering of the memory requests to achieve higher average utilization of the command and data bus
US6385708B1 (en) Using a timing-look-up-table and page timers to determine the time between two consecutive memory accesses
US6587894B1 (en) Apparatus for detecting data collision on data bus for out-of-order memory accesses with access execution time based in part on characterization data specific to memory
JP2002530743A (ja) ページタグレジスタを使用して、メモリデバイス内の物理ページの状態を追跡すること
KR100610730B1 (ko) 메모리 액세스 대기시간을 감소시키기 위한 메모리 액세스스케쥴링 방법 및 장치
KR100724557B1 (ko) 아웃 오브 오더 ｄｒａｍ 시퀀서
US4449183A (en) Arbitration scheme for a multiported shared functional device for use in multiprocessing systems
US6510474B1 (en) Methods and apparatus for re-reordering command and data packets in order to restore an original order of out-of-order memory requests
US6286075B1 (en) Method of speeding up access to a memory page using a number of M page tag registers to track a state of physical pages in a memory device having N memory banks where N is greater than M
WO2001048617A2 (en) Prioritized bus request scheduling mechanism for processing devices
US6532505B1 (en) Universal resource access controller
JP2000501536A (ja) 種々のメモリセグメント間のメモリコントロールシーケンスのタイミングを最適にするメモリコントローラユニット
US6378049B1 (en) Universal memory controller
US5202973A (en) Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus
JP2004500608A (ja) ユニバーサルリソースアクセスコントローラ
US6539440B1 (en) Methods and apparatus for prediction of the time between two consecutive memory accesses
KR101022473B1 (ko) 다층 버스 시스템에서의 메모리 뱅크 인터리빙 방법 및장치
US5708783A (en) Data bus arbiter for pipelined transactions on a split bus
JPH1131072A (ja) メモリ先行ロード装置