WO2000029955A8 - Universal resource access controller - Google Patents

Universal resource access controller

Info

Publication number
WO2000029955A8
WO2000029955A8 PCT/US1999/026994 US9926994W WO0029955A8 WO 2000029955 A8 WO2000029955 A8 WO 2000029955A8 US 9926994 W US9926994 W US 9926994W WO 0029955 A8 WO0029955 A8 WO 0029955A8
Authority
WO
WIPO (PCT)
Prior art keywords
resource
universal
requesting system
universal resource
controller
Prior art date
Application number
PCT/US1999/026994
Other languages
French (fr)
Other versions
WO2000029955A1 (en
WO2000029955A9 (en
Inventor
Henry Stracovsky
Piotr Szabelski
Original Assignee
Infineon Ag
Henry Stracovsky
Piotr Szabelski
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/439,544 external-priority patent/US6532505B1/en
Application filed by Infineon Ag, Henry Stracovsky, Piotr Szabelski filed Critical Infineon Ag
Priority to DE19983738T priority Critical patent/DE19983738T1/en
Priority to JP2000582896A priority patent/JP2004500608A/en
Priority to GB0111925A priority patent/GB2361561B/en
Priority to CNB998156523A priority patent/CN1311357C/en
Publication of WO2000029955A1 publication Critical patent/WO2000029955A1/en
Publication of WO2000029955A8 publication Critical patent/WO2000029955A8/en
Publication of WO2000029955A9 publication Critical patent/WO2000029955A9/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture

Abstract

A universal resource access controller (104) is coupled to a requesting system (102) and a resource (108), such that when the requesting system (102) desires access to the resource (108), the requesting system (102) generates a resource access request which is passed to the universal resource controller (104). The universal resource controller (104), in turn, uses a specific characteristic operating parameter of the requested resource as well as a current state of the requested resource to generate a corresponding sequenced universal access request command suitable for accessing the resource (108) as required by the requesting system (102).
PCT/US1999/026994 1998-11-16 1999-11-15 Universal resource access controller WO2000029955A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE19983738T DE19983738T1 (en) 1998-11-16 1999-11-15 Universal resource access control
JP2000582896A JP2004500608A (en) 1998-11-16 1999-11-15 Universal resource access controller
GB0111925A GB2361561B (en) 1998-11-16 1999-11-15 Universal resource access controller
CNB998156523A CN1311357C (en) 1998-11-16 1999-11-15 Universal resource access controller

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10893098P 1998-11-16 1998-11-16
US60/108,930 1998-11-16
US09/439,544 US6532505B1 (en) 1999-11-12 1999-11-12 Universal resource access controller
US09/439,544 1999-11-12

Publications (3)

Publication Number Publication Date
WO2000029955A1 WO2000029955A1 (en) 2000-05-25
WO2000029955A8 true WO2000029955A8 (en) 2000-09-14
WO2000029955A9 WO2000029955A9 (en) 2000-10-26

Family

ID=26806431

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/026994 WO2000029955A1 (en) 1998-11-16 1999-11-15 Universal resource access controller

Country Status (6)

Country Link
JP (1) JP2004500608A (en)
KR (1) KR100710531B1 (en)
CN (1) CN1311357C (en)
DE (1) DE19983738T1 (en)
GB (1) GB2361561B (en)
WO (1) WO2000029955A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL137085A (en) 2000-06-29 2004-08-31 Eci Telecom Ltd Method for effective utilizing of shared resources in computerized systems
JP4838120B2 (en) * 2003-06-30 2011-12-14 レイセオン カンパニー Efficient memory controller
US8856401B2 (en) * 2003-11-25 2014-10-07 Lsi Corporation Universal controller for peripheral devices in a computing system
CN100445954C (en) * 2004-12-25 2008-12-24 鸿富锦精密工业（深圳）有限公司 System and method of control and management service use resources
JP5414350B2 (en) * 2009-05-08 2014-02-12 キヤノン株式会社 Memory control circuit and control method thereof
DE102010047718A1 (en) * 2010-10-07 2012-04-12 Infineon Technologies Ag Apparatus and method for formatting and preselecting trace data
KR102453193B1 (en) * 2013-05-16 2022-10-11 어드밴스드 마이크로 디바이시즈, 인코포레이티드 Memory system with region-specific memory access scheduling
US10394711B2 (en) * 2016-11-30 2019-08-27 International Business Machines Corporation Managing lowest point of coherency (LPC) memory using a service layer adapter
KR102540964B1 (en) * 2018-02-12 2023-06-07 삼성전자주식회사 Memory Controller and Application Processor controlling utilization and performance of input/output device and Operating Method of Memory Controller

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4354225A (en) * 1979-10-11 1982-10-12 Nanodata Computer Corporation Intelligent main store for data processing systems
US4803623A (en) * 1986-10-31 1989-02-07 Honeywell Bull Inc. Universal peripheral controller self-configuring bootloadable ramware
JPH04354225A (en) * 1991-05-31 1992-12-08 Nec Corp Inter-equipment communication control system for exchange system
US5878240A (en) * 1995-05-11 1999-03-02 Lucent Technologies, Inc. System and method for providing high speed memory access in a multiprocessor, multimemory environment
JP4803623B2 (en) * 2001-07-04 2011-10-26 旭サナック株式会社 Air play hand gun

Also Published As

Publication number Publication date
KR20010086034A (en) 2001-09-07
CN1354854A (en) 2002-06-19
GB2361561B (en) 2003-10-29
KR100710531B1 (en) 2007-04-23
WO2000029955A1 (en) 2000-05-25
GB2361561A (en) 2001-10-24
JP2004500608A (en) 2004-01-08
CN1311357C (en) 2007-04-18
GB0111925D0 (en) 2001-07-04
DE19983738T1 (en) 2002-03-14
WO2000029955A9 (en) 2000-10-26

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