JP2004361488A - Electrooptical device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent defect of an image quality such as crosstalk by reducing the time constant of a capacitance line, in an electrooptical device such as a liquid crystal display or the like. <P>SOLUTION: The electrooptical device is provided with a plurality of pixel electrodes (9a), a plurality of signal lines and electronic elements for supplying pixel signals to the plurality of pixel electrodes, capacitance lines (300) which constitute storage capacitances (70) connected to the plurality of pixel electrodes, and a counter electrode potential line (503) supplying a predetermined potential to a counter electrode via vertically conducting materials (106) disposed between an element substrate and a counter substrate on the element substrate. An inter-wiring capacitance (501) is constructed between the counter electrode potential line and the capacitance lines on the element substrate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention belongs to the technical field of an electro-optical device such as a liquid crystal device and an electronic apparatus including the electro-optical device such as a liquid crystal projector.
[0002]
[Background Art]
In this type of liquid crystal device, for example, liquid crystal is sandwiched between an element substrate and a counter substrate. A pixel electrode and a thin film transistor (hereinafter referred to as “TFT” as appropriate) connected to each of the pixel electrodes are provided on the element substrate, and a scanning line and a data line connected to each of the TFTs are further provided. Signal lines. On the other hand, an opposing electrode is provided on the opposing electrode so as to oppose the pixel electrode. During the operation, a counter electrode potential is supplied to the counter electrode. Usually, the supply of the counter electrode potential is performed from a counter electrode potential line provided on the element substrate via a vertical conductive material provided between the two substrates. In parallel with the supply of the counter electrode potential, an image signal potential is supplied as an image signal to the pixel electrode via each TFT. Then, liquid crystal driving by an active matrix driving method is performed by a liquid crystal driving voltage applied between these electrodes.
[0003]
On the other hand, in this type of liquid crystal device, a storage capacitor is provided for each pixel electrode in parallel with a liquid crystal capacitor in order to improve charge retention characteristics in order to display a higher quality image.
[0004]
[Problems to be solved by the invention]
In this type of electro-optical device, in order to display a brighter image, the area occupied by various signal lines and storage capacitors on the substrate is reduced, and light actually contributing to image display is transmitted or reflected at each pixel by transmission or reflection. It is generally desired to improve the aperture ratio of each pixel by making the light transmission region, which is the region from which light is emitted, larger. In addition, it is generally desired to increase the driving frequency in order to increase the definition of a displayed image and to save power. In order to achieve these objects, it is necessary to reduce the pixel pitch or the wiring pitch, and particularly to reduce the wiring width of various wirings.
[0005]
However, when the capacitance line that forms the storage capacitor is also finely formed, the wiring resistance of the capacitance line increases, and the wiring time constant increases. As a result, there is a technical problem that a potential variation occurs in a capacitance line that is originally assumed to have a predetermined potential, which may eventually cause crosstalk, ghost, and the like in a display image. Furthermore, since the capacitance line is wired within a limited area on the substrate, even if the increase in the wiring resistance is suppressed, other various types that come closer in three dimensions with miniaturization and miniaturization. Parasitic capacitance with the signal line becomes relatively large. For this reason, problems such as crosstalk may become more serious.
[0006]
In order to cope with this, it is not impossible to consider a means of reducing the resistance of the capacitance line, that is, reducing the wiring time constant by increasing the thickness of the wiring while maintaining the wiring width of the capacitance line. However, it is hard to say that this is a sufficient measure capable of responding to the general demand for minimizing and narrowing down each component in the apparatus and preventing a problem relating to image quality such as crosstalk while reducing the size.
[0007]
The present invention has been made in view of the above problems, and an electro-optical device and an electro-optical device capable of preventing a problem of image quality such as crosstalk by reducing a time constant of a capacitance line. It is an object to provide an electronic device including:
[0008]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the electro-optical device of the present invention includes an electro-optical material sandwiched between a pair of element substrates and a counter substrate, and includes a counter electrode having a predetermined potential on the counter substrate. On the element substrate, a plurality of pixel electrodes arranged to face the counter electrode, a plurality of signal lines and an electronic element for supplying an image signal to the plurality of pixel electrodes, and the plurality of pixel electrodes were connected to the plurality of pixel electrodes. A capacitor line that forms a storage capacitor; and a counter electrode potential line that supplies the predetermined potential to the counter electrode via a vertically conductive material disposed between the element substrate and the counter substrate. Above, an inter-wire capacitance is established between the counter electrode potential line and the capacitance line.
[0009]
According to the electro-optical device of the present invention, during operation, an image signal is supplied to a pixel electrode by a signal line such as a data line and a scanning line and an electronic element such as a TFT for pixel switching. At the same time, a predetermined potential is supplied to the counter electrode via the counter electrode potential line and the vertical conductive material. For example, the upper and lower conductive members are provided at four corners on the element substrate, and the counter electrode potential lines are wired so as to pass through the four corners. By supplying these potentials, it is possible to drive an electro-optical material such as a liquid crystal sandwiched between the two electrodes. At this time, the charge retention characteristics of each pixel electrode are improved by the storage capacitor. Here, in particular, on the element substrate, an interwiring capacitance is constructed between the counter electrode potential line and the capacitance line. Each of these wirings has a very high power supply capability on the element substrate. Therefore, by constructing such inter-wiring capacitance, the time constant of the capacitance line can be reduced very efficiently.
[0010]
Therefore, even if the capacitance line is finely formed, it is possible to effectively suppress an increase in the wiring time constant, and to reduce potential fluctuation in the capacitance line that is scheduled to be fixed to the ground potential or the counter electrode potential. It can be significantly reduced. As a result, finally, crosstalk, ghost, and the like in the display image can be reduced, and a high-quality image can be displayed.
[0011]
In one aspect of the electro-optical device according to the aspect of the invention, the inter-wiring capacitance may be a part of the counter electrode potential line, extend from the counter electrode potential line, or be connected to the counter electrode potential line. One conductive layer and a second conductive layer formed of a part of, extending from, or connected to the capacitance line are opposed to each other on the element substrate via a dielectric film. Be placed.
[0012]
According to this aspect, the inter-wiring capacitance includes, for example, the first conductive layer connected to the counter electrode potential line and the second conductive layer connected to the capacitor line, which are opposed to each other via the dielectric film. Alternatively, a first conductive layer formed of a part of the counter electrode potential line and a second conductive layer formed of a part of the capacitor line are disposed on the element substrate via a dielectric film. In any case, the time constant of the capacitance line can be reduced very efficiently by constructing the inter-wiring capacitance between the counter electrode potential line and the capacitance line having a very high power supply capability on the element substrate.
[0013]
In this aspect, the counter electrode potential line and the first conductive layer are connected via one contact hole, and the capacitor line and the second conductive layer are connected via another contact hole. May be done.
[0014]
According to this structure, the conductive layer forming the counter electrode potential line and the first conductive layer, which is another layer, and the conductive layer forming the capacitor line, and the second conductive layer, which is another layer, are disposed so as to face each other. Can build the capacity between. Therefore, for example, it is also possible to construct an inter-wiring capacitance by overlapping the counter electrode potential line or the capacitance line in a plan view, thereby increasing the capacitance value. Also, for example, even if the counter electrode potential line and the capacitance line are formed of the same conductive layer, the inter-wiring capacitance can be constructed from two conductive layers different from the same conductive layer, so that both wirings are most excellent in conductivity. It is also possible to form the same conductive layer.
[0015]
In another aspect of the electro-optical device of the present invention, at least one of the pixel potential side capacitor electrode and the fixed potential side capacitor electrode forming the storage capacitor is formed from the same layer as the first conductive layer or the second conductive layer. It is configured.
[0016]
According to this aspect, since the storage capacitor and the inter-wiring capacitance are at least partially composed of the same conductive layer, it is possible to simplify the laminated structure and the manufacturing process on the element substrate.
[0017]
In this aspect, the inter-wiring capacitance and the storage capacitance may be configured to have the same laminated structure formed simultaneously in the same process at the time of manufacturing.
[0018]
With this configuration, it is possible to remarkably simplify the laminated structure and the manufacturing process on the element substrate.
[0019]
In another aspect of the electro-optical device of the present invention, the counter electrode potential line and the capacitor line are formed of the same conductive layer formed simultaneously in the same process at the time of manufacturing.
[0020]
According to this aspect, it is possible to simplify the laminated structure and the manufacturing process on the element substrate, and in particular, it is possible to form both wirings from the same conductive layer having the highest conductivity.
[0021]
In another aspect of the electro-optical device of the present invention, an image display area in which the plurality of pixel electrodes are arranged is defined on the element substrate, and a peripheral area is defined around the image display area, The inter-wiring capacitance is at least partially disposed in the peripheral region.
[0022]
According to this aspect, the capacitance between wires can be constructed using the peripheral region. The area where the inter-wiring capacitance is arranged is more advantageous as it is closer to the image display area, which is the area where the capacitance line functions for the storage capacitor in the peripheral area.
[0023]
In the aspect in which the interwiring capacitance is arranged in the peripheral region, the interwiring capacitance may be arranged in a region of the peripheral region facing the counter substrate.
[0024]
With this configuration, the inter-wiring capacitance can be constructed in a region relatively close to the image display region in the peripheral region.
[0025]
In this case, further, the element substrate and the counter substrate are bonded together along their edges in the peripheral region with a sealing material, and the inter-wiring capacitance is at least partially set by the sealing material in the peripheral region. It may be configured to be located in an existing seal area.
[0026]
According to this configuration, the inter-wiring capacitance can be constructed in a region of the peripheral region that is very close to the image display region by using the seal region.
[0027]
In this case, the semiconductor device further includes a plurality of dummy patterns on the element substrate for keeping a gap between the elements between the element substrate and the counter substrate at a predetermined value, and the capacitance between the wirings is planar on the element substrate. In view of the above, the plurality of dummy patterns may be configured so as to be divided into a plurality of parts or provided in a comb-tooth shape corresponding to the gap between the plurality of dummy patterns.
[0028]
With this configuration, the dummy pattern can be used to allow the sealing material made of the photo-curable resin to be photo-cured, and the gap between the substrates can be maintained at a predetermined value. A plurality of divided or comb-shaped inter-wiring capacitances can be constructed corresponding to the gaps.
[0029]
In the aspect in which the interwiring capacitance is arranged in the above-described peripheral region, a peripheral driving circuit that drives the plurality of signal lines is arranged in an area of the peripheral area along one side or a plurality of sides of the element substrate. The inter-wiring capacitance may be at least partially arranged in a region along another side of the peripheral region different from the one or more sides.
[0030]
With this configuration, of the four regions along the four sides of the peripheral region, one or a plurality of regions that can secure a wide region for creating the inter-wiring capacitance because the peripheral driving circuit is not arranged, The capacitance between the wirings can be formed, and the capacitance value can be relatively easily increased.
[0031]
In the aspect in which the interwiring capacitance is arranged in the peripheral region, a plurality of external circuit connection terminals including the terminal for the counter electrode potential line are arranged in a region along one side of the element substrate in the peripheral region. The inter-wiring capacitance may be arranged at least partially in a region along another side of the peripheral region opposite to the one side.
[0032]
With this configuration, of the four regions along the four sides of the peripheral region, one or a plurality of regions that can secure a wide region for forming the inter-wiring capacitance because the external circuit connection terminal is not arranged are provided. In addition, the inter-wiring capacitance can be formed, and the capacitance value can be increased relatively easily.
[0033]
In the aspect in which the inter-wiring capacitance is arranged in the peripheral region described above, the plurality of signal lines include a plurality of data lines to which the image signal is supplied and a plurality of data lines which intersect the plurality of data lines and to which a scanning signal is supplied. And the electronic element includes a pixel switching thin film transistor that supplies the image signal from the data line to the pixel electrode in response to the supply of the scanning signal.
[0034]
According to this aspect, during the operation, a scanning signal is supplied to the thin film transistor from the scanning line, and in response to this, an image signal supplied from the data line is supplied to the pixel electrode via the thin film transistor. As a result, the TFT active matrix drive capable of displaying a high-quality image can be performed by the inter-wiring capacitance built in the peripheral region.
[0035]
In this aspect, the capacitance value of the inter-wire capacitance may be equal to or greater than the total capacitance value of the plurality of data lines.
[0036]
With this configuration, the potential change of the capacitor line due to the data line potential inversion when the AC inversion drive is adopted to prevent the deterioration of the electro-optical material such as the liquid crystal and reduce the flicker is reduced. Can be suppressed to about half or less. Preferably, the capacitance value of the inter-line capacitance is increased, for example, from several times to several tens times or several tens times the total capacitance value of the plurality of data lines, so that the potential inversion of the data lines during inversion driving is performed. , It is possible to suppress the potential variation of the capacitor line due to the above to several tenths to several tenths or several tenths of the potential variation of the data line.
[0037]
According to another aspect of the invention, an electronic apparatus includes the above-described electro-optical device (including various aspects thereof).
[0038]
According to the electronic apparatus of the present invention, since the electronic apparatus includes the above-described electro-optical device of the present invention, a projection display device (liquid crystal projector), a liquid crystal television, a mobile phone, and an electronic organizer capable of displaying a high-quality image are provided. And various electronic devices such as a word processor, a viewfinder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel.
[0039]
The operation and other advantages of the present invention will become more apparent from the embodiments explained below.
[0040]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the electro-optical device of the present invention is applied to a TFT active matrix driving type liquid crystal device.
[0041]
(1st Embodiment)
First, an overall configuration of a first embodiment according to the electro-optical device of the present invention will be described with reference to FIGS. Here, FIG. 1 is a plan view of the electro-optical device when the TFT array substrate is viewed from the counter substrate side together with the components formed thereon, and FIG. 2 is a cross-sectional view taken along the line HH ′ in FIG. It is. Here, a TFT active matrix driving type liquid crystal device with a built-in driving circuit, which is an example of an electro-optical device, is taken as an example.
[0042]
1 and 2, in the electro-optical device according to the first embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the opposing substrate 20, and the TFT array substrate 10 and the opposing substrate 20 are separated from each other by a sealing material provided in a sealing area 52a located around the image display area 10a. 52 are mutually bonded.
[0043]
The sealing material 52 is made of, for example, a photocurable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in a manufacturing process, and then cured by ultraviolet irradiation, heating, or the like. Things. Further, a gap material such as glass fiber or glass beads for dispersing the gap (inter-substrate gap) between the TFT array substrate 10 and the opposing substrate 20 to a predetermined value is dispersed in the sealing material 52.
[0044]
In a region outside the sealing material 52, a data line driving circuit 101 for driving the data line 6 a by supplying an image signal to the data line 6 a at a predetermined timing and an external circuit connection terminal 102 are connected to one side of the TFT array substrate 10. The scanning line driving circuit 104 that drives a scanning line by supplying a scanning signal to the scanning line at a predetermined timing is provided along two sides adjacent to this one side.
[0045]
If the delay of the scanning signal supplied to the scanning line does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuits 101 may be arranged on both sides along the side of the image display area 10a.
[0046]
On one remaining side of the TFT array substrate 10, a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the image display area 10a are provided. In at least one of the corners of the counter substrate 20, a conductive material 106 for electrically connecting the TFT array substrate 10 and the counter substrate 20 is provided.
[0047]
In addition, at four corners of the opposing substrate 20, an upper / lower conductive material 106 functioning as an upper / lower conductive terminal between the two substrates is arranged. On the other hand, the TFT array substrate 10 is provided with upper and lower conductive terminals in regions facing these four corners. Thus, electrical continuity can be established between the TFT array substrate 10 and the counter substrate 20.
[0048]
In FIG. 2, an alignment film is formed on the pixel electrode 9a after TFTs for pixel switching and wiring such as scanning lines and data lines are formed on the TFT array substrate 10. On the other hand, on the opposing substrate 20, in addition to the opposing electrode 21, a grid-shaped or striped light-shielding film 23, and further, an alignment film is formed on the uppermost layer portion. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.
[0049]
On the TFT array substrate 10 shown in FIGS. 1 and 2, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the image signal on the image signal line is sampled and supplied to the data line. Sampling circuit, a precharge circuit that supplies a precharge signal of a predetermined voltage level to a plurality of data lines prior to an image signal, and a method for inspecting the quality, defects, and the like of the electro-optical device during manufacturing or shipping. An inspection circuit or the like may be formed.
[0050]
In the first embodiment, particularly, in the peripheral area of the image display area 10a, an inter-wiring capacitance is provided in an area along one side of the image display area 10a in which the data line driving circuit 101 and the scanning line driving circuit 104 are not arranged. Is formed. This will be described in detail later.
[0051]
Next, a configuration in the image display area 10a of the electro-optical device according to the first embodiment will be described with reference to FIG. Here, FIG. 3 is an equivalent circuit of various elements, wiring, and the like in a plurality of pixels formed in a matrix forming the image display area 10a of the electro-optical device.
[0052]
In FIG. 3, a plurality of pixels formed in a matrix forming an image display area of the electro-optical device according to the present embodiment are each provided with a pixel electrode 9a and a TFT 30 for controlling switching of the pixel electrode 9a. The data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, but in the present embodiment, in particular, the image signals S1, S2,. The image signals are serial-parallel-developed into a plurality of image signals, and can be supplied from N image signal lines 115 to N data lines 6a adjacent to each other for each group.
[0053]
In a peripheral area outside the image display area, one end (the lower end in FIG. 3) of the data line 6a is connected to the switching circuit element 202 forming the sampling circuit 301. The switching circuit element may be an n-channel TFT or a p-channel TFT as shown in the figure. In addition, a complementary TFT or the like can be used (hereinafter, the switching circuit element 202 shown in FIG. 3 is referred to as a “TFT 202”). In this case, the lower end of the data line 6a in FIG. 3 is connected to the drain of the TFT 202 via a lead wiring 206, and the image signal line 115 is connected to the source of the TFT 202 via a lead wiring 116. A sampling circuit drive signal line 114 connected to the data line drive circuit 101 is connected to the gate of the TFT 202. The image signals S1, S2,..., Sn on the image signal line 115 are sampled by the sampling circuit 301 in response to the sampling signal being supplied from the data line driving circuit 101 through the sampling circuit driving signal line 114. It is configured to be supplied to each data line 6a.
[0054]
The image signals S1, S2,..., Sn written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. It may be. In the present embodiment, as shown in FIG. 3, a set of six data lines 6a is supplied with an image signal at a time.
[0055]
Also, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulsed manner in this order at a predetermined timing. It is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and by closing the switch of the TFT 30 as a switching element for a certain period, the image signals S1, S2,... Write at a predetermined timing.
[0056]
The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal as an example of the electro-optical material via the pixel electrodes 9a are held for a certain period between the pixel electrodes 9a and the counter electrode formed on the counter substrate. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. In the normally white mode, the transmittance for the incident light decreases according to the voltage applied in each pixel unit, and in the normally black mode, the light enters according to the voltage applied in each pixel unit Light transmittance is increased, and light having a contrast corresponding to an image signal is emitted from the electro-optical device as a whole.
[0057]
In addition, the transmittance of the liquid crystal is determined by the effective value of the applied voltage, and when a DC voltage is applied to the liquid crystal, the composition changes and a problem such as so-called burn-in occurs. For this reason, in the electro-optical device according to the present embodiment, AC inversion driving for inverting the voltage polarity applied to the liquid crystal at a predetermined cycle is performed. That is, in order to perform the AC inversion driving, the voltage polarity of the image signal is inverted every predetermined period such as one horizontal scanning period (one frame) or one field (for example, two frames).
[0058]
In order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. The storage capacitor 70 is provided alongside the scanning line 3a, includes a fixed potential side capacitor electrode, and includes a capacitor line 300 fixed to a constant potential. Due to this storage capacitor 70, the charge retention characteristics of each pixel electrode are improved.
[0059]
On the TFT array substrate 10, a counter electrode potential line 503 is connected to the above-described upper and lower conductive members 106 and passes through four zero corners on the TFT array substrate 10. Here, a predetermined potential is supplied to the counter electrode 21 via the vertical conductive member 106 and the counter electrode potential line 503. By supplying these potentials, it is possible to drive the liquid crystal sandwiched between the pixel electrode 9a and the counter electrode 21 as described above.
[0060]
In the present embodiment, in particular, as shown in FIG. 3, a peripheral area of the image display area 10a and a position facing the data line driving circuit 101 with the image display area 10a interposed therebetween, that is, an upper end of FIG. , An inter-wiring capacitance 501 is provided. The inter-wiring capacitance 501 includes a conductive layer (first conductive layer 511 described later) connected to the capacitor line 300 as one capacitor electrode, and another conductive layer connected to the counter electrode potential line 503 maintained at a predetermined potential. (A second conductive layer 512 described later) is used as the other capacitor electrode, and a dielectric film (a dielectric film 75 described later) is sandwiched between them. The charge corresponding to the difference between the potential of the capacitor line 300 and the potential of the counter electrode potential line 503 is accumulated in the inter-wiring capacitance 501.
[0061]
Here, the capacity line 300 and the counter electrode potential line 503 have extremely high power supply capabilities on the TFT array substrate 10. Therefore, by constructing such an inter-wiring capacitance, the capacitance around the capacitance line 300 is appropriately secured, and the time constant of the capacitance line 300 itself can be reduced very efficiently.
[0062]
Therefore, even if the capacitance line 300 is finely formed, an increase in the wiring time constant can be effectively suppressed, and the potential of the capacitance line 300 electrically connected to the constant potential source and set to the fixed potential is set. Fluctuations can be significantly reduced. As a result, finally, crosstalk, ghost, and the like in the display image can be reduced, and a high-quality image can be displayed. In a more specific configuration of the present embodiment, which will be described later with reference to FIG. 4, the inter-wiring capacitance 501 is connected to the capacitance line 300 via a capacitance line connection wiring 505 (see FIG. 4). However, such a detailed configuration will be described later later.
[0063]
(Seal area)
Hereinafter, the arrangement configuration of the seal region 52a, various wirings, the capacitance 501 between the wirings, and the like in the TFT array substrate 10, particularly in the peripheral region of the image display region 10a, will be described with reference to FIG. FIG. 4 is an enlarged plan view of a corner portion of the TFT array substrate 10 in FIG. 1, that is, a region C of FIG. In FIG. 4, only components particularly relevant to the present invention are shown, and other configurations are omitted as appropriate.
[0064]
As shown in FIG. 4, a seal area 52a in which the seal material 52 is arranged is formed in a peripheral area of the image display area 10a. More specifically, the outer periphery of the opposing substrate 20 indicated by a dotted line in FIG. 4 is disposed inside the outer perimeter of the TFT array substrate 10, and is located inside the opposing substrate 20 and along the outer periphery of the opposing substrate 20. The sealing material 52 is arranged in the sealed region 52a, and both the TFT array substrate 10 and the counter substrate 20 are bonded to each other as described above. The upper and lower conductive members 106 are arranged at the corners (upper right in FIG. 4) of the seal region 52a, and the counter electrode potential lines 503 pass through the upper and lower conductive members 106 and extend along the outer periphery of the seal region 52a. Are located.
[0065]
On the other hand, in the peripheral region of the image display region 10a, inside the seal region 52a, that is, in the region on the image display region 10a side, the capacitance line connection wiring 505 is arranged along the inner periphery of the seal region 52a. . Here, the capacitance line connection wiring 505 is made of, for example, a low-resistance material such as a metal such as aluminum or an alloy, and is formed so as to overlap the formation region of the scanning line 3a on the plane shown in FIG. Each of the plurality of capacitance lines 300 is connected via a contact hole 507. The detailed configuration and the laminated structure of the various wirings including the capacitance line 300 and the various components in the image display area 10a will be described later in detail.
[0066]
Here, in the present embodiment, particularly, as shown in FIG. 4, an inter-wiring capacitance 501 is arranged in a region between the counter electrode potential line 503 and the capacitance line connecting wiring 505 in the peripheral region of the image display region 10a. Have been. In other words, the inter-wiring capacitance 501 is arranged such that a large part of its area is covered by the seal region 52a in plan view.
[0067]
Here, with reference to the perspective view of FIG. 5, the arrangement of the inter-wiring capacitance 501 will be described. In FIG. 5, the main purpose is to show the arrangement relationship of each component of the inter-wiring capacitance 501, and therefore, for example, the dielectric film 75 and each interlayer insulating film will be described later in detail with reference to FIG. Illustration of some components is omitted.
[0068]
As shown in FIG. 5, the inter-wiring capacitance 501 includes a first conductive layer 511 connected to the capacitance line connection wiring 505, and a second conductive layer 512 connected to the counter electrode potential line 503. The conductive layer 511 and the second conductive layer 512 are configured to be opposed to each other on the TFT array substrate 10 with a dielectric film 75 (not shown) interposed therebetween. With such a configuration, a capacitance is formed between the counter electrode potential line 503 and the capacitance line 300 via the capacitance line connection wiring 505, both of which have high power supply capability, and the capacitance around the capacitance line 300 is increased. The capacity is appropriately secured. Therefore, as described above, the time constant of the capacitance line 300 itself can be reduced very efficiently, and the potential fluctuation in the capacitance line 300 can be significantly reduced.
[0069]
In addition, the wiring layer forming the capacitor line connection wiring 505 and the first conductive layer, which is another layer, and the wiring layer of the counter electrode potential line 503 and the second conductive layer, which is another layer, are arranged so as to face each other. By further extending the first conductive layer and the second conductive layer, the inter-wiring capacitance 501 is configured to overlap the region where the capacitance line connecting wiring 505 or the counter electrode potential line 503 is wired in plan view. It is also possible to easily increase the capacitance value.
[0070]
Further, as shown in FIG. 4, the inter-wiring capacitance 301 having such a configuration includes the data line driving circuit 101, the scanning line driving circuit 104, and the external circuit connection terminal 102 in the peripheral area of the image display area 10a. It is arranged in a region along one side that is not arranged, and is arranged so that most of its area is covered by the seal region 52a in plan view. In other words, the inter-wiring capacitance 501 is a “dead space” in a region where a large area for forming the inter-wiring capacitance 501 can be ensured because the peripheral driving circuit as described above is not arranged. Was formed by effectively utilizing the former area. Therefore, it is possible to relatively easily form the relatively large-capacity wiring capacitance 501 without newly providing a special region on the TFT array substrate 10. The inter-wiring capacitance 501 is also very advantageous from the viewpoint that it can be formed in a region relatively close to the image display region 10a, which is a region where the capacitance line 300 functions for the storage capacitor 70.
[0071]
Here, in the present embodiment, preferably, the capacitance value of the inter-wiring capacitance 501 is equal to or larger than the total capacitance value of the plurality of data lines 6a, and is, for example, about several times to tens of times the total capacitance value of the plurality of data lines 6a. Or about several tens of times. Here, more specifically, the film thicknesses of the first and second conductive layers constituting the upper and lower electrodes of the inter-wiring capacitance 501, the distance between the first and second conductive layers, and the dielectric film 75 Under the condition that the dielectric constant of the wiring is constant, the capacitance value of the inter-wiring capacitance 501 increases in proportion to the area on the substrate plane shown in FIG. On the other hand, the total capacitance value of the plurality of data lines 6a is mainly governed by the wiring width of each data line 6a under the condition that the material and thickness thereof and the number of each data line 6a are constant. It increases in proportion to the total area on the substrate plane. Therefore, the inter-wiring capacitance 501 according to the present embodiment has the maximum possible width in the arrangement between the counter electrode potential line 503 and the capacitance line connecting wiring 505 in the Y direction in FIG. By adjusting the length in the X direction in FIG. 4 according to the wiring width, it is possible to set a sufficient capacitance with respect to the total capacitance value of the data lines 6a.
[0072]
In this way, by configuring the capacitance value of the inter-wiring capacitance 501 to be equal to or greater than the total capacitance value of the plurality of data lines 6a, the AC inversion driving that inverts the voltage polarity applied to the liquid crystal at a predetermined cycle as described above. In this case, the potential variation of the capacitor line 300 due to the potential inversion of the data line 6a can be suppressed to about half or less of the potential variation of the data line 6a. Further, by increasing the capacitance value of the inter-wiring capacitance 501 to, for example, about several times to about ten and several times or about several tens times of the total capacitance value of the plurality of data lines, the data line 6a during AC inversion driving is formed. , The potential change of the capacitance line 300 due to the potential inversion of the data line 6a can be suppressed to about one-seventh to one-tenth or one-tenth of the potential change of the data line 6a.
[0073]
In the present embodiment, it is preferable that the inter-wiring capacitance 501 is arranged as close as possible to the image display area 10a in the Y direction shown in FIG. 4, but the arrangement position in the X direction shown in FIG. Is not particularly limited in moving in parallel from the arrangement position shown in FIG. 4 in the seal region 52a.
[0074]
Hereinafter, a more specific configuration of the electro-optical device in which the above-described circuit operation is realized by the data line 6a, the scanning line 3a, the TFT 30, and the like will be described with reference to FIGS. FIG. 6 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed, and FIG. 7 is a cross-sectional view taken along line AA ′ of FIG. In FIG. 7, the scale of each layer / member is made different so that each layer / member has a size recognizable in the drawing.
[0075]
First, as shown in FIG. 7, which is a cross-sectional view taken along the line AA ′ of FIG. 6, the electro-optical device according to the present embodiment includes a transparent TFT array substrate 10 and a transparent counter substrate 20 that is disposed to face the TFT array substrate. It has. The TFT array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate.
[0076]
As shown in FIG. 7, a pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive film such as an ITO (Indium Tin Oxide) film. On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode 21. The counter electrode 21 is made of a transparent conductive film such as an ITO film, like the pixel electrode 9a, and the alignment films 16 and 22 are made of a transparent organic film such as a polyimide film. The liquid crystal layer 50 assumes a predetermined alignment state by the alignment films 16 and 22 when no electric field is applied from the pixel electrode 9a.
[0077]
On the other hand, in FIG. 6, a plurality of the pixel electrodes 9a are provided in a matrix on the TFT array substrate 10 (the outline is indicated by a dotted line portion 9a '). The data line 6a and the scanning line 3a are provided along. The data line 6a is made of, for example, a metal film such as an aluminum film or an alloy film, and the scanning line 3a is made of, for example, a conductive polysilicon film. Further, the scanning line 3a is arranged so as to face a channel region 1a 'indicated by a hatched region in the semiconductor layer 1a, which rises to the right in the figure, and the scanning line 3a functions as a gate electrode. That is, pixel switching TFTs 30 are provided at the intersections of the scanning lines 3a and the data lines 6a, in which the main lines of the scanning lines 3a are opposed to each other as gate electrodes in the channel region 1a '.
[0078]
As shown in FIG. 7, the TFT 30 has an LDD (Lightly Doped Drain) structure, and its component is a scanning line 3a functioning as a gate electrode as described above, for example, a scanning line made of a polysilicon film. A channel region 1a 'of the semiconductor layer 1a in which a channel is formed by an electric field from 3a, an insulating film 2 including a gate insulating film for insulating the scanning line 3a from the semiconductor layer 1a, a lightly doped source region 1b in the semiconductor layer 1a, A high concentration drain region 1c, a high concentration source region 1d and a high concentration drain region 1e are provided.
[0079]
The TFT 30 preferably has an LDD structure as shown in FIG. 7, but may have an offset structure in which impurities are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c, or a part of the scanning line 3a. A self-aligned TFT in which a high concentration source region and a high concentration drain region are formed in a self-aligned manner by implanting impurities at a high concentration using a gate electrode formed of as a mask. Further, in the present embodiment, a single gate structure in which only one gate electrode of the pixel switching TFT 30 is disposed between the high-concentration source region 1d and the high-concentration drain region 1e has been described. Electrodes may be arranged. When a TFT is formed with a dual gate or triple gate or more as described above, a leak current at a junction between a channel and a source / drain region can be prevented, and a current in an off state can be reduced. Further, the semiconductor layer 1a constituting the TFT 30 may be a non-single-crystal layer or a single-crystal layer. For forming the single crystal layer, a known method such as a bonding method can be used. By using the semiconductor layer 1a as a single crystal layer, the performance of peripheral circuits in particular can be improved.
[0080]
On the other hand, in FIG. 7, the storage capacitor 70 includes a relay layer 71 as a pixel potential side capacitor electrode connected to the high-concentration drain region 1e and the pixel electrode 9a of the TFT 30, and a capacitor line 300 as a fixed potential side capacitor electrode. A part of them is formed by being opposed to each other with a dielectric film 75 interposed therebetween. According to the storage capacitor 70, the potential holding characteristic of the pixel electrode 9a can be significantly improved.
[0081]
The relay layer 71 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitance electrode. However, the relay layer 71 may be formed of a single-layer film or a multilayer film containing a metal or an alloy, similarly to the capacitance line 300 described later. The relay layer 71 has a function of relaying the pixel electrode 9a and the high-concentration drain region 1e of the TFT 30 via the contact holes 83 and 85, in addition to the function as the pixel potential side capacitor electrode.
[0082]
The capacitance line 300 is made of, for example, a conductive film containing a metal or an alloy, and extends from the image display region 10a where the pixel electrode 9a is arranged to the periphery thereof, and is electrically connected to a constant potential source having a relatively low potential. , Function as a fixed-potential-side capacitor electrode of the storage capacitor 70. As shown in FIG. 6, when viewed in plan, the capacitance line 300 is formed so as to overlap the formation region of the scanning line 3a. More specifically, the capacitance line 300 includes a main line portion extending along the scanning line 3a, a protrusion protruding upward along the data line 6a from each location intersecting the data line 6a in the figure, and a contact hole. A portion corresponding to 85 is provided with a constricted portion slightly constricted. Of these, the protruding portion contributes to an increase in the formation area of the storage capacitor 70 by utilizing the area above the scanning line 3a and the area below the data line 6a.
[0083]
As shown in FIG. 7, the dielectric film 75 is, for example, a relatively thin HTO (High Temperature Oxide) film having a thickness of about 5 to 200 nm, a silicon oxide film such as an LTO (Low Temperature Oxide) film, or a silicon nitride film. Consists of From the viewpoint of increasing the storage capacitance 70, the thinner the dielectric film 75 is, the better the reliability of the film can be obtained.
[0084]
6 and 7, in addition to the above, a lower light shielding film 11a is provided below the TFT 30. The lower light-shielding film 11a is patterned in a lattice pattern, thereby defining an opening area of each pixel. Note that the definition of the opening region is also made by the data line 6a in FIG. 6 and the capacitor line 300 formed so as to intersect with the data line 6a. Also, the lower light-shielding film 11a is extended from the image display area to the periphery thereof in order to prevent the potential fluctuation from adversely affecting the TFT 30, as in the case of the above-described capacitance line 300. It may be connected to a potential source.
[0085]
The base insulating film 12 is provided below the TFT 30. The base insulating film 12 has a function of interlayer insulating the TFT 30 from the lower light-shielding film 11a, and is formed over the entire surface of the TFT array substrate 10 so that the surface of the TFT array substrate 10 is roughened at the time of polishing the surface and dirt remaining after cleaning. It has a function of preventing a change in the characteristics of the pixel switching TFT 30.
[0086]
In addition, on the scanning line 3a, a first interlayer insulating film 41 in which a contact hole 81 leading to the high-concentration source region 1d and a contact hole 83 leading to the high-concentration drain region 1e are respectively formed.
[0087]
A relay layer 71 and a capacitance line 300 are formed on the first interlayer insulating film 41, and a contact hole 81 leading to the high-concentration source region 1d and a contact hole 85 leading to the relay layer 71 are formed thereon. An apertured second interlayer insulating film 42 is formed.
[0088]
In addition, a data line 6a is formed on the second interlayer insulating film 42, and a third interlayer insulating film 43 having a contact hole 85 leading to the relay layer 71 is formed thereon. I have.
[0089]
(Configuration of capacitance between wirings)
In the following, with respect to each component of the inter-wiring capacitance 501, which is a feature of the present embodiment, the laminated structure thereof will be described with reference to FIG. 8 which corresponds to the laminated structure of the pixel portion described above with reference to FIG. This will be described in more detail. FIG. 8 is a sectional view taken along the line BB 'in FIG. In FIG. 8, the scale of each layer and each member is made different so that each layer and each member has a size recognizable in the drawing.
[0090]
As described with reference to FIGS. 4 and 5, the inter-wiring capacitance 501 includes the first conductive layer 511 connected to the capacitance line 300 via the capacitance line connection wiring 505 as one capacitance electrode, and the counter electrode The second conductive layer 512 connected to the potential line 503 is used as the other capacitor electrode, and the dielectric film 75 is sandwiched between them.
[0091]
First, the second conductive layer 512 is formed on the first interlayer insulating film 41 as shown in FIG. That is, as can be seen by comparing FIGS. 7 and 8, the second conductive layer 512 is formed as the same film as the relay layer 71 constituting the storage capacitor 70.
[0092]
The second conductive layer 512 is mutually connected to the counter electrode potential line 503 via the contact hole 582. Here, the contact hole 582 is opened through the second interlayer insulating film 42.
[0093]
Here, the counter electrode potential line 503 is wired along the outer periphery of the counter substrate 20 through the upper / lower conductive material 106, and is formed as the same film as the data line 6a. That is, when the data line 6a is formed including aluminum as described above, the counter electrode potential line 503 is also formed including aluminum. As described above, if the counter electrode potential line 503 is formed including a low-resistance material such as aluminum, the wiring delay or the like does not matter. With this configuration, the second conductive layer 512 has the same potential as the counter electrode potential line 503.
[0094]
On the other hand, the first conductive layer 511 is formed on the dielectric film 75 formed on the second conductive layer 512 so as to face the second conductive layer 512, as shown in FIG. The first conductive layer 511 is connected via a contact hole 581 to a capacitance line connecting wiring 505 formed on the second interlayer insulating film 42. Here, like the contact hole 582, the contact hole 581 is opened through the second interlayer insulating film 42.
[0095]
Here, the capacitance line connection wiring 505 extends along the outer periphery of the image display region 10a, and a contact hole is formed in a region between the image display region 10a and the scanning line driving circuit 104 in a peripheral region of the image display region 10a. It is connected to the capacitance line 300 via 507. Then, as shown in FIG. 8, the capacitance line connection wiring 505 is formed as the same film as the data line 6a. That is, when the data line 6a is formed including aluminum as described above, the capacitance line connecting wiring 505 is also formed including aluminum. As described above, if the capacitance line connection wiring 505 is formed including a low-resistance material such as aluminum, the wiring delay or the like does not matter. With such a configuration, the first conductive layer 511 has the same potential as the capacitor line 300.
[0096]
Since the inter-wiring capacitance 501 according to the present embodiment is configured as described above, as is apparent from a comparison between FIG. 7 and FIG. Is formed. Specifically, as described above, the first conductive layer 511 and the relay layer 71 are formed as the same film for the capacitor line 300 and the second conductive layer 512, respectively. The dielectric film 75 is shared by the inter-wiring capacitance 501 and the storage capacitance 70. In the present embodiment, the data line 6a, the counter electrode potential line 503, and the capacitor line connection wiring 505 are further formed as the same film.
[0097]
As described above, in the present embodiment, the inter-wiring capacitance 501 and its related configuration are formed at the same time as the components (the data line 6a and the storage capacitor 70, etc.) formed in the image display area 10a. Therefore, it is possible to simplify the laminated structure and the manufacturing process on the TFT array substrate or to reduce the manufacturing cost.
[0098]
The counter electrode potential line 503 is connected to a predetermined potential source (not shown) for supplying a predetermined potential such as a fixed potential or an inversion potential inverted to AC inversion drive to the counter electrode 21 (not shown). The second conductive layer 512 is also at a predetermined potential. On the other hand, the capacitor line connection wiring 505 is connected to the capacitor line 300, and the capacitor line 300 is used to supply a relatively low fixed potential to the capacitor line 300 constituting the storage capacitor 70. Since the first conductive layer 511 is connected to the potential source, the first conductive layer 511 also has a fixed potential. In the present embodiment, in order to set the first conductive layer 511 and the second conductive layer 512 to a predetermined potential, a power supply for the capacitor line 300 and a power supply for the counter electrode 21 can be used. Since there is no need to provide a power supply specifically for the conductive layer and the second conductive layer 512, the device configuration can be simplified accordingly.
[0099]
The dielectric film 75 serving as an insulating layer of the inter-wiring capacitance 501 is the same as the above-described dielectric film 75 of the storage capacitance 70, as is apparent from the name and reference numeral. That is, the dielectric film 75 is shared by the inter-wiring capacitance 501 and the storage capacitance 70.
[0100]
(2nd Embodiment)
A second embodiment according to the electro-optical device of the present invention will be described with reference to FIGS. Here, FIG. 9 is an enlarged view of the area C of FIG. 1 as a view having the same effect as FIG. 4, and shows wiring formed in a peripheral area of the image display area in the electro-optical device according to the second embodiment. It is a top view which shows the structure of an inter-capacity. FIG. 10 is a sectional view taken along the line BB ′ of FIG.
[0101]
The second embodiment is different from the first embodiment in that the inter-wiring capacitance on the plane and the distance between the TFT array substrate and the opposing substrate, that is, the inter-substrate gap, are adjusted. The difference is that a dummy pattern is provided. Therefore, the circuit configuration and operation in the image display area, and the overall configuration of the liquid crystal device are the same as in the first embodiment. Therefore, hereinafter, a configuration different from the first embodiment will be described. 9 to 10, the same components as those in the first embodiment shown in FIGS. 1 to 8 are denoted by the same reference numerals, and the description thereof will be omitted.
[0102]
As shown in FIG. 9, in the present embodiment, the distance between the TFT array substrate 10 and the opposing substrate 20, that is, the gap between the substrates, that is, the gap between the substrates, is kept within a sealing region 52 a on the TFT array substrate 10. A dummy pattern 600 is provided. Here, the adjustment of the gap between the substrates by the dummy pattern 600 will be described.
[0103]
In the electro-optical device according to the present embodiment, as to the structure for bonding both the TFT array substrate 10 and the opposing substrate 20, as shown in FIGS. The gap between the substrates is maintained at a predetermined value by the sealing material 52 containing a plurality of spherical gap materials having a diameter. However, when the seal area 52a is compared with each other in four areas corresponding to the four sides of the image display area 10a, various wiring layers wired from the peripheral drive circuit to the image display area 10a across the seal area 52a are provided. The height of each of the above-mentioned gap members, that is, the height of a portion to be a base of the above-mentioned gap material is different. More specifically, in the area corresponding to the three sides on the left, right, and lower sides of the image display area 10a shown in FIGS. 1 and 3 in the seal area 52a, the scanning wired from the left and right scanning line driving circuits 104 There is a position higher than the other region due to the line 3a, the lead-out wiring 116 wired from the data line driving circuit 101 arranged on the lower side, and the like. Therefore, in the area corresponding to one side on the upper side of the image display area 10a shown in FIG. 1 in the seal area 52a, since the above-described various wirings and the like do not exist, the uppermost layer in the laminated structure of the TFT array substrate 10, That is, the layer to be the base of the gap material is formed lower than the other three sides. Due to such circumstances, in the region corresponding to the above-described one side on the upper side, the dummy pattern 600 is provided in order to match the height with the other three sides.
[0104]
The dummy pattern 600 formed for the above purpose is formed as a plurality of patterns in parallel on the substrate plane, corresponding to the arrangement of the plurality of data lines 6a, as shown by the dotted lines in FIG.
[0105]
Here, particularly in the present embodiment, as shown in FIG. 9, the inter-wiring capacitance 501 is provided by being divided into a plurality corresponding to the gaps of the plurality of dummy patterns 600 when viewed in plan on the TFT array substrate 10. Have been.
[0106]
More specifically, the counter electrode potential line 503 wired in the X direction along the upper side of the counter substrate 20 in FIG. 9 extends in a comb-like shape in the Y direction corresponding to the plurality of dummy patterns 600 described above. And is connected via a contact hole 582 to a plurality of second conductive layers 512 constituting a plurality of inter-wiring capacitances 501.
[0107]
On the other hand, the capacitance line connection wiring 505 wired in the X direction along the upper side of the image display area 10a in FIG. 9 has a comb-like shape in the direction opposite to the Y direction corresponding to the plurality of dummy patterns 600 described above. And is connected via a contact hole 581 to a plurality of first conductive layers 511 constituting a plurality of inter-wiring capacitances 501.
[0108]
With this configuration, the inter-wiring capacitance 501 as a capacitance between the capacitance line 300 and the counter electrode potential line 503 is divided into a plurality of parts and constructed similarly to the first embodiment described above. It will be.
[0109]
According to the above configuration, after the sealing material 52 made of a photocurable resin is applied on the TFT array substrate 10 in a manufacturing process in order to bond the two substrates, for example, the back surface side of the TFT array substrate 10 When cured by irradiation with ultraviolet light or the like from above, the irradiation light reaches the sealing material 52 by sewing through the gap between the dummy pattern 600 and the inter-wiring capacitance 501 that are formed in a comb-like shape as described above. . That is, even when the opaque dummy pattern 600 and the inter-wiring capacitance 501 are formed in the sealing region 52a as in the present embodiment, since these have a plurality of gaps, the irradiation light effectively reaches the sealing material. The sealing material 52 can be cured by light irradiation without being hindered by the dummy pattern 600 and the capacitance 501 between the wirings.
[0110]
The plurality of inter-wiring capacitances 501 of the present embodiment are formed in the same area as the inter-wiring capacitance 501 of the first embodiment shown in FIG. 4 on the substrate plane shown in FIG. In other words, similarly, since a peripheral drive circuit or the like is not disposed, a region where the inter-wiring capacitance 501 can be formed widely can be secured. Utilized and formed. Accordingly, a plurality of relatively large-capacity inter-wiring capacitances 501 can be formed relatively easily without newly providing a special region on the TFT array substrate 10.
[0111]
The total capacitance value of the plurality of inter-wiring capacitances 501 in the present embodiment is equal to or greater than the total capacitance value of the plurality of data lines 6a, and is preferably, for example, several times to 10 times the total capacitance value of the plurality of data lines 6a. It is about several times or several tens times. As described in the first embodiment, the total capacitance value of the inter-wiring capacitance 501 increases in proportion to the total area of the plurality of inter-wiring capacitances 501 on the substrate plane shown in FIG. Therefore, the inter-wiring capacitance 501 is as large as possible in the arrangement between the counter electrode potential line 503 and the capacitance line connecting wiring 505 in the Y direction in FIG. Accordingly, by adjusting the width and the number of the inter-wiring capacitances 501 in the X direction shown in FIG. 10, it is possible to set a sufficient capacitance with respect to the total capacitance value of the data lines 6a.
[0112]
Next, with reference to FIG. 10, a laminated structure of the inter-wiring capacitance 501 and the dummy pattern 600 in the present embodiment will be described below. Here, FIG. 10 is a cross-sectional view taken along the line BB ′ of FIG.
[0113]
As shown in FIG. 10, a plurality of inter-wiring capacitances 501 are formed in the present embodiment, and the laminated structure of each of them is the same as the laminated structure in the first embodiment shown in FIG.
[0114]
In this embodiment, in particular, a dummy pattern 600 made of the same layer as the scanning line 3a shown in FIG.
[0115]
Here, in particular, as shown in FIG. 10, the sealing material 52 is disposed in the sealing region 52a so as to cover a part of the region where the dummy pattern 600 is formed and a part of the region where the inter-wiring capacitance 501 is formed. The height of a portion of the gap material included in the sealing material 52 that should serve as a base is the same as that of FIG. 10 where the dummy pattern 600 is formed in the wiring layer of the counter electrode potential line 503 located at the highest position in the laminated structure. It is defined by the height of the D part. That is, even if the inter-wiring capacitance 501 is provided so as to correspond to the plurality of dummy patterns 600 when viewed in a plan view as shown in FIG. The uppermost layer of the region where the dummy pattern 600 is formed is formed to be the same as or lower than the uppermost layer of the region D where the dummy pattern 600 is formed. Height is not affected.
[0116]
Therefore, while using the dummy pattern 600, the sealing material 52 made of a photo-curable resin can be photo-cured and the gap between the substrates can be maintained at a predetermined value, and the gap between the dummy patterns 600 can be reduced. Correspondingly, a plurality of divided or comb-shaped inter-wiring capacitances can be constructed.
[0117]
The location of the dummy pattern 600 in the laminated structure is not limited to the above-described embodiment. For example, the dummy pattern 600 may be directly formed on the TFT array substrate 10 or formed on the same layer as other wiring layers. May be done.
[0118]
Finally, in the present embodiment, the function and effect of the inter-wiring capacitance 501 configured as described above and the gain obtained thereby are the same as those of the inter-wiring capacitance 501 in the first embodiment.
[0119]
(Electronics)
Next, an overall configuration, particularly an optical configuration, of an embodiment of a projection type color display device as an example of an electronic apparatus using the electro-optical device described above in detail as a light valve will be described. FIG. 11 is a schematic cross-sectional view of the projection type color display device.
[0120]
In FIG. 11, a liquid crystal projector 1100, which is an example of a projection type color display device according to the present embodiment, prepares three liquid crystal modules each including a liquid crystal device in which a driving circuit is mounted on a TFT array substrate, and each of them has a light valve for RGB. The projector is configured as a projector used as 100R, 100G, and 100B. In the liquid crystal projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, three mirrors 1106 and two dichroic mirrors 1108 emit light components R, G and R corresponding to the three primary colors RGB. B, and are led to light valves 100R, 100G, and 100B corresponding to each color. In this case, in particular, the B light is guided through a relay lens system 1121 including an entrance lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss due to a long optical path. The light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are combined again by the dichroic prism 1112, and then projected as a color image on the screen 1120 via the projection lens 1114.
[0121]
The present invention is not limited to the above-described embodiment, and can be appropriately changed within the scope of the invention or the idea that can be read from the entirety of the claims and the specification, and an electro-optical device with such a change. And electronic devices are also included in the technical scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a plan view illustrating an overall configuration of an electro-optical device according to a first embodiment of the invention.
FIG. 2 is a sectional view taken along the line HH ′ of FIG. 1;
FIG. 3 is a circuit diagram showing an equivalent circuit such as various elements and wiring provided in a plurality of pixels in a matrix forming an image display area in the electro-optical device according to the first embodiment of the present invention.
FIG. 4 is a plan view of the electro-optical device in which a region C in FIG. 1 is enlarged.
FIG. 5 is a perspective view illustrating a configuration of an inter-wire capacitance according to the first embodiment of the present invention.
FIG. 6 is a plan view of a plurality of adjacent pixel groups on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the electro-optical device according to the first embodiment of the present invention.
FIG. 7 is a sectional view taken along line AA ′ of FIG. 6;
FIG. 8 is a sectional view taken along the line BB ′ of FIG. 4;
FIG. 9 is a plan view illustrating a configuration of an inter-wiring capacitance formed in a peripheral area of an image display area in the electro-optical device according to the second embodiment.
FIG. 10 is a sectional view taken along the line BB ′ of FIG. 9;
FIG. 11 is a schematic sectional view showing a color liquid crystal projector as an example of a projection type color display device which is an embodiment of the electronic apparatus of the invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device, 10 ... TFT array substrate, 10a ... Image display area, 20 ... Counter substrate, 21 ... Common electrode, 50 ... Liquid crystal layer, 52 ... Sealing material , 52a: seal area, 70: storage capacity, 100: liquid crystal panel, 101: data line drive circuit, 102: external circuit connection terminal, 104: scan line drive circuit, 106 ... Upper and lower conductive material, 110... Image display area, 501... Inter-wiring capacitance, 503... Counter electrode potential line, 505. , 512: second conductive layer, 581, 582: contact hole, 600: dummy pattern

Claims (15)

An electro-optic material is sandwiched between a pair of element substrates and a counter substrate,
A counter electrode having a predetermined potential on the counter substrate;
On the element substrate, a plurality of pixel electrodes arranged to face the counter electrode, a plurality of signal lines and an electronic element for supplying an image signal to the plurality of pixel electrodes, and the plurality of pixel electrodes are connected to the plurality of pixel electrodes. And a counter electrode potential line for supplying the predetermined potential to the counter electrode via an upper / lower conductive material disposed between the element substrate and the counter substrate.
An electro-optical device, wherein an interwiring capacitance is constructed between the counter electrode potential line and the capacitance line on the element substrate. The inter-wiring capacitance includes a first conductive layer formed of a part of the counter electrode potential line or extending from the counter electrode potential line or connected to the counter electrode potential line, and a part of the capacitor line. And a second conductive layer extending from the capacitance line or connected to the capacitance line, and disposed opposite to each other via a dielectric film on the element substrate. 2. The electro-optical device according to 1. The counter electrode potential line and the first conductive layer are connected via one contact hole,
The electro-optical device according to claim 2, wherein the capacitance line and the second conductive layer are connected via another contact hole. 2. The device according to claim 1, wherein at least one of the pixel potential side capacitor electrode and the fixed potential side capacitor electrode constituting the storage capacitor is formed of the same layer as the first conductive layer or the second conductive layer. 4. The electro-optical device according to any one of claims 1 to 3. The electro-optical device according to claim 4, wherein the inter-wiring capacitance and the storage capacitance have the same laminated structure formed simultaneously in the same process at the time of manufacturing. The electro-optical device according to any one of claims 1 to 5, wherein the counter electrode potential line and the capacitor line are formed of the same conductive wire layer formed simultaneously in the same step during manufacturing. An image display area in which the plurality of pixel electrodes are arranged is defined on the element substrate, and a peripheral area is defined around the image display area. The inter-wiring capacitance is at least partially defined in the peripheral area. The electro-optical device according to any one of claims 1 to 6, wherein the electro-optical device is arranged in a region. The electro-optical device according to claim 7, wherein the inter-wiring capacitance is arranged in a region of the peripheral region facing the counter substrate. The element substrate and the counter substrate are bonded together with a sealing material along their edges in the peripheral region,
9. The electro-optical device according to claim 8, wherein the inter-wiring capacitance is at least partially disposed in a sealing area of the peripheral area where the sealing material exists. On the element substrate, further comprising a plurality of dummy patterns for maintaining the inter-substrate gap between the element substrate and the counter substrate at a predetermined value,
10. The inter-wiring capacitance is divided into a plurality or provided in a comb shape corresponding to a gap between the plurality of dummy patterns when viewed in plan on the element substrate. An electro-optical device according to claim 1. A peripheral drive circuit that drives the plurality of signal lines is arranged in an area along one side or a plurality of sides of the element substrate in the peripheral area,
11. The device according to claim 7, wherein the inter-wiring capacitance is at least partially arranged in a region along another side of the peripheral region different from the one or more sides. An electro-optical device according to the item. A plurality of external circuit connection terminals including a terminal for the counter electrode potential line are arranged in a region along one side of the element substrate in the peripheral region,
11. The device according to claim 7, wherein the inter-wiring capacitance is at least partially disposed in a region along another side of the peripheral region opposite to the one side. 12. Electro-optical device. The plurality of signal lines include a plurality of data lines to which the image signal is supplied, and a plurality of scanning lines to which a scanning signal is supplied while intersecting with the plurality of data lines.
11. The electronic device according to claim 7, wherein the electronic element includes a pixel switching thin film transistor that supplies the image signal from the data line to the pixel electrode in response to the supply of the scanning signal. 12. An electro-optical device according to claim 1. 14. The electro-optical device according to claim 13, wherein a capacitance value of the inter-wiring capacitance is equal to or greater than a total capacitance value of the plurality of data lines. An electronic apparatus comprising the electro-optical device according to claim 1.

Images