JP2004356499A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
JP2004356499A
JP2004356499A JP2003154307A JP2003154307A JP2004356499A JP 2004356499 A JP2004356499 A JP 2004356499A JP 2003154307 A JP2003154307 A JP 2003154307A JP 2003154307 A JP2003154307 A JP 2003154307A JP 2004356499 A JP2004356499 A JP 2004356499A
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Japan
Prior art keywords
pad
source
gate
pin
field
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JP2003154307A
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Japanese (ja)
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JP4231736B2 (en
Inventor
Koichi Kato
浩一 加藤
Masafumi Koyano
雅史 小谷野
Shigeaki Nitta
茂彰 新田
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Renesas Technology Corp
Sony Corp
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Renesas Technology Corp
Sony Corp
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Priority to JP2003154307A priority Critical patent/JP4231736B2/en
Publication of JP2004356499A publication Critical patent/JP2004356499A/en
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Publication of JP4231736B2 publication Critical patent/JP4231736B2/en
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device designed for a protection circuit for realizing long life of an Li<SP>+</SP>battery pack and for miniaturization. <P>SOLUTION: Power MOS FETs Q<SB>1</SB>and Q<SB>2</SB>formed in a semiconductor chip 3 to function the protection circuit for the Li<SP>+</SP>battery pack, a source pad, a gate pad, a gate pad, and a source pad are arranged sequentially from one direction. According to the pad arrangement, with respect to lead pins 6b of a lead frame 6; a source pin S<SB>1</SB>, a gate pin G<SB>1</SB>, a gate pin G<SB>2</SB>, and a source pin S<SB>2</SB>are sequentially from one pin. On a wiring pattern 8 on a mounting substrate 5; a source wiring pattern MS<SB>1</SB>, a gate wiring pattern MG<SB>1</SB>, a gate wiring pattern MG<SB>2</SB>, and a source wiring pattern MS<SB>2</SB>are arranged sequentially from one direction as a layout. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置の製造技術に関し、特に、Ｌｉイオン（以下、Ｌｉ＋と記す）電池保護回路向けのドレイン共通電界効果トランジスタ（以下、パワーＭＯＳＦＥＴ（Ｍｅｔａｌ Ｏｘｉｄａｔｉｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）と記す）を有する半導体装置に適用して有効な技術に関する。
【０００２】
【従来の技術】
ノートＰＣや携帯電話に代表される携帯機器では、電力を供給するバッテリーにエネルギー密度の高いＬｉ＋電池が一般に用いられている。このＬｉ＋電池にはスイッチング素子、例えばパワーＭＯＳＦＥＴが接続されており、充電と放電とを制御してＬｉ＋電池を制御している。
【０００３】
パワーＭＯＳＦＥＴに対しては損失に関わる電気的特性の改善と小型外形とが強く求められており、市場のニーズに対応するため、各社高性能なプロセス開発を進めている。
【０００４】
例えばオン時における定常損失を占めるおもな電気的特性であるオン抵抗は、これまでセルと呼ばれる構造単位を微細化することにより改善されてきた。しかしパワーＭＯＳＦＥＴは大電流容量が求められることから、その微細化にも限界があり、さらなるオン抵抗の低減を図るための様々な工夫がなされている。例えば上記セルの構造をプレーナ（Ｐｌａｎｅｒ）構造に代わりトレンチ（Ｕ−Ｇｒｏｏｖｅ）構造とすることにより、ＪＦＥＴ部の抵抗を理論的にゼロとすることができ、さらなる微細化が可能となる技術が提案されている（例えば、非特許文献１参照）。
【０００５】
【非特許文献１】
“８ピンＳＯＰパワーＭＯＳＦＥＴの製品系列拡充”、１９９７年１２月、［ 平成１５年５月１９日検索 ］、インターネット＜ＵＲＬ：ｈｔｔｐ：／／ｗｗｗ．ｎｅｃｅｌ．ｃｏｍ／Ｊａｐａｎｅｓｅ／ｂａｎｎｅｒ／ｔｅｃｈ／６０／ＤＴＪ６０ＬＵＺ．ｐｄｆ＞
【０００６】
【発明が解決しようとする課題】
本発明者は、Ｌ＋電池保護回路技術について検討した。図１４に、本発明者によって検討されたＬｉ＋電池保護回路の概要平面図を示す。
【０００７】
Ｌｉ＋電池保護回路では、充放電用の２つのパワーＭＯＳＦＥＴＱ１，Ｑ２が１つの半導体チップ２１に形成されており、この半導体チップ２１はリードフレーム２２のアイランド２２ａ上に搭載されてパッケージによって包まれている。リードフレーム２２のリードピン２２ｂは１ピンから順にソースピンＳ１、ゲートピンＧ１、ソースピンＳ２、ゲートピンＧ２のピン配置となっており、１つの半導体チップ２１に２素子が入る場合は、上記ピン配置が一般的に用いられている。さらに上記ピン配置に合わせてパワーＭＯＳＦＥＴＱ１，Ｑ２のパッド配置および実装基板２３上の配線パターン２４のレイアウトが決められている。
【０００８】
しかしながら、上記ピン配置を用いた場合、実装基板２３上のソースピンＳ２が接続される配線パターン２４の一部が細くなり、基板配線抵抗が増加することが明らかとなった。この基板配線抵抗の増加により配線損失が増加し、発熱によるＬｉ＋電池パックの短寿命化などの問題が生ずる。さらにソースピンＳ２が接続される配線パターン２４を引き出した後、基板配線抵抗を低減するためにこの配線パターン２４を太くする必要があり、実装基板２３の面積が増加するという問題もある。
【０００９】
本発明の目的は、Ｌｉ＋電池パックの長寿命化および小型化を実現することのできる技術を提供することにある。
【００１０】
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。
【００１１】
【課題を解決するための手段】
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。
【００１２】
本発明は、ドレインを共通とする第１パワーＭＯＳＦＥＴと第２のパワーＭＯＳＦＥＴとを備え、リードフレームのアイランド上に搭載された半導体チップにおいて、一方向から順に第１パワーＭＯＳＦＥＴの第１ソースパッド、第１ゲートパッド、第２パワーＭＯＳＦＥＴの第２ゲートパッド、第２ソースパッドが半導体チップの表面側に配置されており、第１パワーＭＯＳＦＥＴの第１ソースパッド、第１ゲートパッドおよび第２パワーＭＯＳＦＥＴの第２ゲートパッド、第２ソースパッドがそれぞれワイヤでリードフレームのリードピンに接続されて、リードピンを１ピンから順に第１ソースピン、第１ゲートピン、第２ゲートピン、第２ソースピンとするものである。
【００１３】
【発明の実施の形態】
以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。
【００１４】
図１に、本発明の一実施の形態であるＬｉ＋電池パックの回路図、図２に、本発明の一実施の形態であるＬｉ＋電池保護回路の概略平面図、図３に、図２に示したリードフレームおよびこれに搭載された半導体チップの拡大平面図を示す。
【００１５】
図１に示すように、Ｌｉ＋電池パック１では、Ｌｉ＋セル２にドレインＤを共通とした充放電用の２つのパワーＭＯＳＦＥＴＱ１，Ｑ２が接続されている。パワーＭＯＳＦＥＴＱ１，Ｑ２は１つの半導体チップ３に形成されて、１つのパッケージに包まれている。さらにパワーＭＯＳＦＥＴＱ１，Ｑ２には制御用ＩＣ４が接続されており、これらＬｉ＋セル２、半導体チップ３および制御用ＩＣ４は１つのＬｉ＋保護回路実装基板（以下単に実装基板と言う）５上に固定されている。なお図中、ＳはパワーＭＯＳＦＥＴＱ１，Ｑ２のソース、ＧはパワーＭＯＳＦＥＴＱ１，Ｑ２のゲートを示す。
【００１６】
図２および図３に示すように、半導体チップ３には、２つのパワーＭＯＳＦＥＴＱ１，Ｑ２が並べて形成されており、半導体チップ３はリードフレーム６のアイランド６ａ上に銀ペースト樹脂等を用いて接着されている。パワーＭＯＳＦＥＴＱ１のソースＳ、ゲートＧおよびパワーＭＯＳＦＥＴＱ２のソースＳ、ゲートＧは、半導体チップ３の表面側に形成されたソースパッドＰＳ１，ゲートパッドＰＧ１およびソースパッドＰＳ２、ゲートパッドＰＧ２にそれぞれ取り出されており、これらパッドは、ワイヤ７を用いてリードフレーム６のリードピン６ｂにそれぞれ電気的に接続されている。パワーＭＯＳＦＥＴＱ１，Ｑ２のドレインＤは、半導体チップ３の裏面側に取り出されて、リードフレーム６のアイランド６ａに電気的に接続されている。
【００１７】
さらに、半導体チップ３では、一方向から順にパワーＭＯＳＦＥＴＱ１のソースパッドＰＳ１、ゲートパッドＰＧ１、パワーＭＯＳＦＥＴＱ２のゲートパッドＰＧ２、ソースパッドＰＳ２のパッド配置となっており、このパッド配置に合わせて、リードフレーム６のリードピン６ａのピン配置および実装基板５上の配線パターン８のレイアウトが行われている。すなわち、リードフレーム６のリードピン６ｂでは、１ピンから順にソースピンＳ１、ゲートピンＧ１、ゲートピンＧ２、ソースピンＳ２のピン配置となり、実装基板５上の配線パターン８では、一方向からソース用配線パターンＭＳ１、ゲート用配線パターンＭＧ１、ゲート用配線パターンＭＧ２、ソース用配線パターンＭＳ２のレイアウトとなっている。
【００１８】
このように、パワーＭＯＳＦＥＴＱ１のソースパッドＰＳ１およびパワーＭＯＳＦＥＴＱ２のソースパッドＰＳ２を外側に、パワーＭＯＳＦＥＴＱ１のゲートパッドＰＧ１およびパワーＭＯＳＦＥＴＱ２のゲートパッドＰＧ２を内側に配置することで、リードフレーム６のソースピンＳ１，Ｓ２を外側に、ゲートピンＧ１，Ｇ２を内側に配置することができる。従って、ソースピンＳ１，Ｓ２を接続する配線パターン８のソース用配線パターンＭＳ１，ＭＳ２がゲート用配線パターンＭＧ１，ＭＧ２の外側に配置されて、そのレイアウトの自由度が増すことから、ソース用配線パターンＭＳ１，ＭＳ２を太く形成することができる。これにより、ソース用配線パターンＭＳ１，ＭＳ２の基板配線抵抗が低減し、配線損失を低減することができる。さらに配線パターン８のレイアウトが簡単となり、相対的に小さい面積で配線パターン８がレイアウトできるので、実装基板５の面積を相対的に小さくすることができる。
【００１９】
次に、本発明の一実施の形態であるパワーＭＯＳＦＥＴの実装基板への実装方法を図４〜図１３を用いて工程順に説明する。
【００２０】
図４は、半導体チップを搭載したリードフレームの要部平面図である。
【００２１】
ここでは、まずリードフレーム６を用意する。リードフレーム６は、半導体チップ３を搭載するアイランド６ａとリードピン６ｂとを備えており、導電材からなるフープ材をプレスまたはエッチングにより加工して一体形成したものである。またリードフレーム６は、実際には上記した各部によって構成される単位フレームを複数個連設した構成になっている。
【００２２】
次に、銀メッキされたアイランド６ａ上に銀ペースト樹脂等を載せて、ここに半導体チップ３を軽く押しつけて接着する。半導体チップ３は、マウンタ装置を使用して真空チャックでピックアップされ、コンピュータによる制御により、リードフレーム６のアイランド６ａ上の正しい位置に貼り付けられる。半導体チップ３は、パワーＭＯＳＦＥＴＱ１，Ｑ２を形成した単結晶シリコンである。
【００２３】
次に、図５は、続く実装工程における図４と同じ箇所の要部平面図である。
【００２４】
ここでは、ボンディング装置を使用して半導体チップ３の表面側に形成されたパワーＭＯＳＦＥＴＱ１のソースパッドＰＳ１、ゲートパッドＰＧ１およびパワーＭＯＳＦＥＴＱ２のソースパッドＰＳ２、ゲートパッドＰＧ２と、リードフレーム６のリードピン６ｂとをワイヤ７で電気的に接続する。ワイヤ７は、例えば直径３０μｍ程度の金細線で構成されている。ボンディング装置には、予めパワーＭＯＳＦＥＴＱ１のソースパッドＰＳ１、ゲートパッドＰＧ１およびパワーＭＯＳＦＥＴＱ２のソースパッドＰＳ２、ゲートパッドＰＧ２とリードフレーム６のリードピン６ｂとの配置情報が入力されており、両者の相対的位置関係を画像として取り込みデータ処理を行うことにより正確なボンディングが行われる。なおソース抵抗を低減するために、パワーＭＯＳＦＥＴＱ１のソースパッドＰＳ１およびパワーＭＯＳＦＥＴＱ２のソースパッドＰＳ２とリードピン６ｂとを接続するワイヤ７の数を相対的に多く設けている。
【００２５】
次に、図６は、続く実装工程における図４と同じ箇所の要部平面図である。
【００２６】
ここでは、半導体チップ３を搭載したリードフレーム６をモールド金型に装着し、温度を上げて液状化した樹脂９を圧送してモールド金型に流し込み、モールド成型する。これにより半導体チップ３は樹脂９で封止され、樹脂９からなるパッケージ１０により包まれる。続いてモールド金型からパッケージ（外部に露出したリードピン６ｂ等を含む）１０を取り出した後、余分な樹脂９やバリを取ってメッキし、パッケージ１０の表面に社名、製品名などをレーザ捺印する。
【００２７】
次に、図７は、続く実装工程における図４と同じ箇所の要部平面図、図８（ａ）および（ｂ）は、それぞれ図７のＡ−Ａ′線およびＢ−Ｂ′線における要部断面図である。また図９（ａ）および（ｂ）は、それぞれパッケージの表面図および裏面図、図１０（ａ）および（ｂ）は、それぞれ図９（ａ）のＸ方向およびＹ方向から見たパッケージの側面図である。
【００２８】
ここでは、パッケージ１０をリード先端カット金型に装着し、パッケージ１０から外部に露出したリードフレーム６の不要箇所を切断、除去した後、リードフレーム６から１個１個のパッケージ１０を分離する。これにより、半導体チップ３の組立が完了して、パワーＭＯＳＦＥＴＱ１，Ｑ２の製品１１が完成する。
【００２９】
その後、製品規格に基づいて半導体チップ３の機能・性能に関する特性検査、リードフレーム６の形状、捺印の明瞭さ、その他の外観状態、信頼性試験などを行い、製品１１の選別を行う。
【００３０】
次に、図１１は、続く実装工程における製品およびこれを実装する実装基板の要部側面図である。
【００３１】
ここでは、実装基板５の所望する配線パターン８上に半田ペースト１２を塗布した後、リードフレーム６のアイランド６ａおよびリードピン６ｂと実装基板５上の配線パターン８との位置合わせを行う。すなわち、前記図２に示したように、アイランド６ａとドレイン用配線パターン、ソースピンＳ１とソース用配線パターンＭＳ１、ゲートピンＧ１とゲート用配線パターンＭＧ１、ゲートピンＧ２とゲート用配線パターンＭＧ２、ソースピンＳ２とソース用配線パターンＭＳ２とを合わせて、実装基板５上に製品１１を載せる。
【００３２】
次に、図１２は、続く実装工程における図１１と同じ箇所の要部側面図、図１３は、続く実装工程における図１１と同じ箇所の要部側面図である。
【００３３】
ここでは、製品１１を載せた実装基板５をリフロー処理等により加熱して半田ペースト１２を溶かした後、常温に戻して半田ペースト１２を固めることにより、製品１１と実装基板５とを接着する。
【００３４】
このように、本実施の形態によれば、半導体チップ３に形成されたパワーＭＯＳＦＥＴＱ１のソースパッドＰＳ１およびパワーＭＯＳＦＥＴＱ２のソースパッドＰＳ２を外側に、パワーＭＯＳＦＥＴＱ１のゲートパッドＰＧ１およびパワーＭＯＳＦＥＴＱ２のゲートパッドＰＧ２を内側に配置することにより、リードフレーム６のリードピン６ｂのピン配置を変えて、実装基板５上の配線パターン８のソース用配線パターンＭＳ１，ＭＳ２を太く、かつ小面積でレイアウトすることができる。これにより実装基板５の基板配線抵抗が低減して、配線損失を低減することができるので、発熱によるＬｉ＋電池パック１の長寿命化を図ることができる。さらに実装基板５の小型化が可能となるので、Ｌｉ＋電池パック１の小型化を実現することができる。
【００３５】
以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。
【００３６】
例えば、前記実施の形態では、ノートＰＣや携帯電話等の長寿命化、小型化が要求される携帯機器に用いられるＬｉ＋電池パックの保護回路に適用した場合について説明したが、例えばニッケル水素電池等の他の電池パックの保護回路にも適用することができる。
【００３７】
【発明の効果】
本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。
【００３８】
Ｌｉ＋保護回路実装基板上の配線パターンの基板配線抵抗を低減し、実装基板の小型化を実現することができることから、Ｌｉ＋電池パックの長寿命化および小型化を実現することができる。
【図面の簡単な説明】
【図１】本発明の一実施の形態であるＬｉ＋電池パックの回路図である。
【図２】本発明の一実施の形態であるＬｉ＋電池保護回路の概略平面図である。
【図３】図２に示したリードフレームおよびこれに搭載された半導体チップの拡大平面図である。
【図４】本発明の一実施の形態であるパワーＭＯＳＦＥＴの実装工程中の半導体チップを搭載したリードフレームの要部平面図である。
【図５】図４に続くパワーＭＯＳＦＥＴの実装工程中の図４と同じ箇所の要部平面図である。
【図６】図５に続くパワーＭＯＳＦＥＴの実装工程中の図４と同じ箇所の要部平面図である。
【図７】図６に続くパワーＭＯＳＦＥＴの実装工程中の図４と同じ箇所の要部平面図である。
【図８】（ａ）は、図７のＡ−Ａ′線における要部断面図、（ｂ）は、図７のＢ−Ｂ′線における要部断面図である。
【図９】（ａ）は、パッケージの表面図、（ｂ）は、パッケージの裏面図である。
【図１０】（ａ）は、図９（ａ）のＸ方向から見たパッケージの側面図、（ｂ）は、図９（ａ）のＹ方向から見たパッケージの側面図である。
【図１１】図７〜図１０に続くパワーＭＯＳＦＥＴの実装工程中の製品およびこれを実装する実装基板の要部側面図である。
【図１２】図１１に続く実装工程中の図１１と同じ箇所の要部側面図である。
【図１３】図１２に続く実装工程中の図１１と同じ箇所の要部側面図である。
【図１４】本発明者によって検討されたＬｉ＋電池保護回路の概略平面図である。
【符号の説明】
１ Ｌｉ＋電池パック
２ Ｌｉ＋セル
３ 半導体チップ
４ 制御用ＩＣ
５ 実装基板
６ リードフレーム
６ａ アイランド
６ｂ リードピン
７ ワイヤ
８ 配線パターン
９ 樹脂
１０ パッケージ
１１ 製品
１２ 半田ペースト
２１ 半導体チップ
２２ リードフレーム
２２ａ アイランド
２２ｂ リードピン
２３ 実装基板
２４ 配線パターン
Ｑ１ パワーＭＯＳＦＥＴ
Ｑ２ パワーＭＯＳＦＥＴ
Ｓ ソース
Ｇ ゲート
Ｄ ドレイン
ＰＳ１ ソースパッド
ＰＧ１ ゲートパッド
ＰＳ２ ソースパッド
ＰＧ２ ゲートパッド
Ｓ１ ソースピン
Ｇ１ ゲートピン
Ｓ２ ソースピン
Ｇ２ ゲートピン
ＭＳ１ ソース用配線パターン
ＭＧ１ ゲート用配線パターン
ＭＳ２ ソース用配線パターン
ＭＧ２ ゲート用配線パターン[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device manufacturing technique, and more particularly to a common drain field effect transistor (hereinafter referred to as a power MOSFET (Metal Oxidation Semiconductor Field Effect Transistor)) for a Li ion (hereinafter referred to as Li + ) battery protection circuit. The present invention relates to a technique which is effective when applied to a semiconductor device having the same.
[0002]
[Prior art]
In a portable device such as a notebook PC or a mobile phone, a Li + battery having a high energy density is generally used as a battery for supplying power. The Li + is the cell switching element, for example, a power MOSFET is connected, controls the Li + battery by controlling charging and discharging.
[0003]
Power MOSFETs are strongly required to have improved electrical characteristics related to loss and a small external shape. To respond to market needs, various companies are developing high-performance processes.
[0004]
For example, the on-resistance, which is the main electrical characteristic that occupies a steady loss at the time of on-state, has been improved by miniaturizing a structural unit called a cell. However, since power MOSFETs require a large current capacity, miniaturization is limited, and various devices have been devised to further reduce the on-resistance. For example, a technique has been proposed in which the resistance of the JFET portion can be made theoretically zero by making the above cell structure a trench (U-groove) structure instead of a planar structure, thereby enabling further miniaturization. (For example, see Non-Patent Document 1).
[0005]
[Non-patent document 1]
“Expansion of product lineup of 8-pin SOP power MOSFET”, December 1997, [Searched on May 19, 2003], Internet <URL: http: // www. necel. com / Japanese / banner / tech / 60 / DTJ60LUZ. pdf>
[0006]
[Problems to be solved by the invention]
The inventor has studied L + battery protection circuit technology. FIG. 14 shows a schematic plan view of a Li + battery protection circuit studied by the present inventors.
[0007]
In the Li + battery protection circuit, two power MOSFETs Q 1 and Q 2 for charging and discharging are formed on one semiconductor chip 21, and this semiconductor chip 21 is mounted on an island 22 a of a lead frame 22 and packaged by a package. It is rare. The lead pins 22b of the lead frame 22 have a pin arrangement of a source pin S 1 , a gate pin G 1 , a source pin S 2 , and a gate pin G 2 in order from one pin. A pin arrangement is generally used. Further, the pad arrangement of the power MOSFETs Q 1 and Q 2 and the layout of the wiring pattern 24 on the mounting board 23 are determined in accordance with the above-mentioned pin arrangement.
[0008]
However, when using the pin arrangement, part of the wiring pattern 24 in which the source pin S 2 on the mounting board 23 is connected becomes thin, the substrate wiring resistance was found to increase. Due to the increase in the substrate wiring resistance, the wiring loss increases, and the heat generation causes a problem such as shortening the life of the Li + battery pack. After a further source pin S 2 is pulled out wiring pattern 24 connected, there is necessary to increase the wiring pattern 24 in order to reduce the substrate wiring resistance, there is a problem that the area of the mounting substrate 23 is increased.
[0009]
An object of the present invention is to provide a technology capable of realizing a longer life and a smaller size of a Li + battery pack.
[0010]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0012]
The present invention includes a first power MOSFET and a second power MOSFET having a common drain. In a semiconductor chip mounted on an island of a lead frame, a first source pad of the first power MOSFET is sequentially arranged from one direction. A first gate pad, a second gate pad of the second power MOSFET, and a second source pad are arranged on the front side of the semiconductor chip, and the first source pad, the first gate pad, and the second power MOSFET of the first power MOSFET are provided. The second gate pad and the second source pad are respectively connected to the lead pins of the lead frame by wires, and the lead pins are a first source pin, a first gate pin, a second gate pin, and a second source pin in order from pin 1. .
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
[0014]
FIG. 1 is a circuit diagram of a Li + battery pack according to one embodiment of the present invention, FIG. 2 is a schematic plan view of a Li + battery protection circuit according to one embodiment of the present invention, and FIG. 1 is an enlarged plan view of the lead frame shown in FIG. 1 and a semiconductor chip mounted thereon.
[0015]
As shown in FIG. 1, in the Li + battery pack 1, two power MOSFETs Q 1 and Q 2 for charging and discharging having a common drain D are connected to the Li + cell 2. The power MOSFETs Q 1 and Q 2 are formed on one semiconductor chip 3 and are wrapped in one package. Further, a control IC 4 is connected to the power MOSFETs Q 1 and Q 2 , and the Li + cell 2, the semiconductor chip 3 and the control IC 4 are mounted on a single Li + protection circuit mounting substrate (hereinafter simply referred to as a mounting substrate) 5. Fixed to. Note in the figure, S is the source, G power MOSFET Q 1, Q 2 denotes a gate of the power MOSFETQ 1, Q 2.
[0016]
As shown in FIGS. 2 and 3, two power MOSFETs Q 1 and Q 2 are formed side by side on the semiconductor chip 3. The semiconductor chip 3 is formed on the island 6 a of the lead frame 6 by using silver paste resin or the like. Glued. The source S of the power MOSFET Q 1, the gate G and the source S of the power MOSFET Q 2, the gate G, the source pad PS 1 is formed on the surface side of the semiconductor chip 3, the gate pad PG 1 and source pad PS 2, the gate pad PG 2 These pads are electrically connected to the lead pins 6b of the lead frame 6 using the wires 7, respectively. The drains D of the power MOSFETs Q 1 and Q 2 are taken out on the back surface side of the semiconductor chip 3 and are electrically connected to the island 6 a of the lead frame 6.
[0017]
Further, in the semiconductor chip 3, the source pad PS 1 of the power MOSFET Q 1 from one direction in order, the gate pad PG 1, the gate pad PG 2 power MOSFET Q 2, has a pad arrangement of the source pad PS 2, this pad arrangement In addition, the pin arrangement of the lead pins 6 a of the lead frame 6 and the layout of the wiring pattern 8 on the mounting board 5 are performed. In other words, the lead pins 6b of the lead frame 6 have a pin arrangement of a source pin S 1 , a gate pin G 1 , a gate pin G 2 , and a source pin S 2 in order from the first pin. The layout has a wiring pattern for use MS 1 , a wiring pattern for gate MG 1 , a wiring pattern for gate MG 2 , and a wiring pattern for source MS 2 .
[0018]
Thus, the source pad PS 2 of the source pad PS 1 and the power MOSFET Q 2 of the power MOSFET Q 1 on the outside, by arranging the gate pad PG 2 of the gate pad PG 1 and the power MOSFET Q 2 of the power MOSFET Q 1 on the inside, The source pins S 1 and S 2 of the lead frame 6 can be arranged outside, and the gate pins G 1 and G 2 can be arranged inside. Therefore, the source wiring patterns MS 1 , MS 2 of the wiring pattern 8 connecting the source pins S 1 , S 2 are arranged outside the gate wiring patterns MG 1 , MG 2 , thereby increasing the degree of freedom in the layout. Therefore, the source wiring patterns MS 1 and MS 2 can be formed thick. As a result, the substrate wiring resistance of the source wiring patterns MS 1 and MS 2 is reduced, and wiring loss can be reduced. Furthermore, the layout of the wiring pattern 8 is simplified, and the wiring pattern 8 can be laid out with a relatively small area, so that the area of the mounting substrate 5 can be relatively reduced.
[0019]
Next, a method for mounting a power MOSFET on a mounting substrate according to an embodiment of the present invention will be described in the order of steps with reference to FIGS.
[0020]
FIG. 4 is a plan view of a main part of a lead frame on which a semiconductor chip is mounted.
[0021]
Here, first, the lead frame 6 is prepared. The lead frame 6 includes an island 6a on which the semiconductor chip 3 is mounted and a lead pin 6b, and is formed integrally by processing a hoop material made of a conductive material by pressing or etching. In addition, the lead frame 6 is actually configured such that a plurality of unit frames constituted by the above-described respective parts are continuously provided.
[0022]
Next, a silver paste resin or the like is placed on the silver-plated island 6a, and the semiconductor chip 3 is lightly pressed and bonded thereto. The semiconductor chip 3 is picked up by a vacuum chuck using a mounter device, and is attached to a correct position on the island 6a of the lead frame 6 by control of a computer. The semiconductor chip 3 is a single crystal silicon on which power MOSFETs Q 1 and Q 2 are formed.
[0023]
Next, FIG. 5 is a plan view of a main part of the same place as in FIG. 4 in a subsequent mounting step.
[0024]
Here, the source pad PS 1 of the power MOSFET Q 1 formed on the surface side of the semiconductor chip 3 by using the bonding apparatus, the source pad PS 2 of the gate pad PG 1 and the power MOSFET Q 2, a gate pad PG 2, a lead frame 6 are electrically connected to the lead pins 6 b by wires 7. The wire 7 is made of, for example, a gold wire having a diameter of about 30 μm. The bonding apparatus, the source pad PS 1 in advance the power MOSFET Q 1, the source pad PS 2 of the gate pad PG 1 and the power MOSFET Q 2, the arrangement information is inputted to the lead pin 6b of the gate pad PG 2 and the lead frame 6, Accurate bonding is performed by capturing the relative positional relationship between the two as an image and performing data processing. Note in order to reduce the source resistance is provided relatively large number of wires 7 for connecting the source pad PS 2 and lead pin 6b of the source pad PS 1 and the power MOSFET Q 2 of the power MOSFET Q 1.
[0025]
Next, FIG. 6 is a plan view of an essential part of the same place as in FIG. 4 in a subsequent mounting process.
[0026]
Here, the lead frame 6 on which the semiconductor chip 3 is mounted is mounted on a mold, the resin 9 liquefied by raising the temperature is pressure-fed, poured into the mold, and molded. As a result, the semiconductor chip 3 is sealed with the resin 9 and wrapped in the package 10 made of the resin 9. Subsequently, after removing the package (including the externally exposed lead pins 6b) 10 from the mold, the excess resin 9 and burrs are removed and plated, and the surface of the package 10 is laser-printed with the company name, product name, and the like. .
[0027]
Next, FIG. 7 is a plan view of the same portion as FIG. 4 in a subsequent mounting process, and FIGS. 8A and 8B are main views along the line AA 'and the line BB' in FIG. 7, respectively. It is a fragmentary sectional view. 9A and 9B are a front view and a back view of the package, respectively, and FIGS. 10A and 10B are side views of the package as viewed from the X direction and the Y direction in FIG. 9A, respectively. FIG.
[0028]
Here, the package 10 is mounted on a die for cutting the lead end, and unnecessary portions of the lead frame 6 exposed to the outside from the package 10 are cut and removed, and then the individual packages 10 are separated from the lead frame 6. Thereby, the assembly of the semiconductor chip 3 is completed, and the product 11 of the power MOSFETs Q 1 and Q 2 is completed.
[0029]
Thereafter, based on the product standard, a characteristic test on the function and performance of the semiconductor chip 3, a shape of the lead frame 6, clarity of the seal, other appearance states, a reliability test, and the like are performed, and the products 11 are sorted.
[0030]
Next, FIG. 11 is a side view of a main part of a product and a mounting board for mounting the product in a subsequent mounting process.
[0031]
Here, after applying the solder paste 12 on the desired wiring pattern 8 of the mounting board 5, the island 6 a and the lead pins 6 b of the lead frame 6 are aligned with the wiring pattern 8 on the mounting board 5. That is, the as shown in Figure 2, the island 6a and the drain wiring pattern, the source pin S 1 and the source wiring pattern MS 1, the gate pin G 1 and the gate wiring pattern MG 1, gate pin G 2 and the gate wiring pattern The product 11 is mounted on the mounting board 5 by matching the MG 2 , the source pin S 2 and the source wiring pattern MS 2 .
[0032]
Next, FIG. 12 is a side view of a main part of the same place as in FIG. 11 in a subsequent mounting step, and FIG. 13 is a side view of a main part of the same place in FIG. 11 in a subsequent mounting step.
[0033]
Here, the product 11 and the mounting substrate 5 are bonded by heating the mounting substrate 5 on which the product 11 is mounted by reflow processing or the like to melt the solder paste 12, and then returning the temperature to normal temperature to solidify the solder paste 12.
[0034]
Thus, according to this embodiment, the source pad PS 2 of the source pad PS 1 and the power MOSFET Q 2 of the power MOSFET Q 1 formed on the semiconductor chip 3 on the outside, the gate pad PG 1 and the power of the power MOSFET Q 1 by disposing the gate pad PG 2 of MOSFET Q 2 inside, by changing the pin arrangement of the lead pin 6b of the lead frame 6, thick source wiring pattern MS 1, MS 2 of the wiring pattern 8 on the mounting substrate 5, and It can be laid out in a small area. As a result, the wiring resistance of the mounting substrate 5 is reduced, and the wiring loss can be reduced. Therefore, the life of the Li + battery pack 1 due to heat generation can be extended. Furthermore, since the mounting substrate 5 can be reduced in size, the Li + battery pack 1 can be reduced in size.
[0035]
As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. Needless to say, there is.
[0036]
For example, in the above-described embodiment, a case has been described in which the present invention is applied to a protection circuit of a Li + battery pack used for a portable device such as a notebook PC or a mobile phone that requires a long life and a small size. And the like for other battery pack protection circuits.
[0037]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0038]
Since the board wiring resistance of the wiring pattern on the Li + protection circuit mounting board can be reduced and the mounting board can be miniaturized, the life and size of the Li + battery pack can be prolonged.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a Li + battery pack according to an embodiment of the present invention.
FIG. 2 is a schematic plan view of a Li + battery protection circuit according to an embodiment of the present invention.
FIG. 3 is an enlarged plan view of the lead frame shown in FIG. 2 and a semiconductor chip mounted thereon.
FIG. 4 is a plan view of a main part of a lead frame on which a semiconductor chip is mounted during a power MOSFET mounting process according to an embodiment of the present invention;
5 is an essential part plan view of the same place as in FIG. 4 during a power MOSFET mounting step following FIG. 4;
6 is a fragmentary plan view of the same place as in FIG. 4 during a power MOSFET mounting step following FIG. 5;
7 is a fragmentary plan view of the same place as in FIG. 4 during a power MOSFET mounting step following FIG. 6;
8A is a cross-sectional view of a main part taken along line AA 'of FIG. 7, and FIG. 8B is a cross-sectional view of a main part taken along line BB' of FIG.
9A is a front view of a package, and FIG. 9B is a rear view of the package.
10A is a side view of the package as viewed from the X direction in FIG. 9A, and FIG. 10B is a side view of the package as viewed from the Y direction in FIG. 9A.
FIG. 11 is a side view of a main part of a product in a power MOSFET mounting process following FIG. 7 to FIG. 10 and a mounting substrate on which the product is mounted;
12 is an essential part side view of the same place as in FIG. 11 during a mounting step following FIG. 11;
13 is an essential part side view of the same place as in FIG. 11 during a mounting step following FIG. 12;
FIG. 14 is a schematic plan view of a Li + battery protection circuit studied by the present inventors.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Li + battery pack 2 Li + cell 3 Semiconductor chip 4 Control IC
5 mounting board 6 lead frame 6a island 6b lead pin 7 wire 8 wiring pattern 9 resin 10 package 11 product 12 solder paste 21 semiconductor chip 22 lead frame 22a island 22b lead pin 23 mounting board 24 wiring pattern Q 1 power MOSFET
Q 2 power MOSFET
S Source G Gate D Drain PS 1 Source pad PG 1 Gate pad PS 2 Source pad PG 2 Gate pad S 1 Source pin G 1 Gate pin S 2 Source pin G 2 Gate pin MS 1 Source wiring pattern MG 1 Gate wiring pattern MS 2 source wiring pattern MG 2 gate wiring pattern

Claims (5)

（ａ）第１電界効果トランジスタと第２電界効果トランジスタとを備え、その表面側に前記第１電界効果トランジスタの第１ソースパッドと第１ゲートパッドおよび前記第２電界効果トランジスタの第２ソースパッドと第２ゲートパッドとを有し、一方向から順に前記第１ソースパッド、前記第１ゲートパッド、前記第２ゲートパッド、前記第２ソースパッドが配置された半導体チップをリードフレームのアイランド上に搭載する工程と、
（ｂ）前記第１ソースパッド、前記第１ゲートパッド、前記第２ゲートパッドおよび前記第２ソースパッドをそれぞれワイヤにより前記リードフレームのリードピンに接続する工程とを有することを特徴とする半導体装置の製造方法。(A) a first field-effect transistor and a second field-effect transistor, and a first source pad and a first gate pad of the first field-effect transistor and a second source pad of the second field-effect transistor on the surface side And a second gate pad. A semiconductor chip having the first source pad, the first gate pad, the second gate pad, and the second source pad arranged in order from one direction is placed on an island of a lead frame. Mounting process,
(B) connecting the first source pad, the first gate pad, the second gate pad, and the second source pad to lead pins of the lead frame by wires, respectively. Production method. （ａ）第１電界効果トランジスタと第２電界効果トランジスタとを備え、その表面側に前記第１電界効果トランジスタの第１ソースパッドと第１ゲートパッドおよび前記第２電界効果トランジスタの第２ソースパッドと第２ゲートパッドとを有し、一方向から順に前記第１ソースパッド、前記第１ゲートパッド、前記第２ゲートパッド、前記第２ソースパッドが配置された半導体チップをリードフレームのアイランド上に搭載する工程と、
（ｂ）前記第１ソースパッド、前記第１ゲートパッド、前記第２ゲートパッドおよび前記第２ソースパッドをそれぞれワイヤにより前記リードフレームのリードピンに接続する工程とを有し、
前記リードフレームのリードピンを１ピンから順に第１ソースピン、第１ゲートピン、第２ゲートピン、第２ソースピンとすることを特徴とする半導体装置の製造方法。(A) a first field-effect transistor and a second field-effect transistor, and a first source pad and a first gate pad of the first field-effect transistor and a second source pad of the second field-effect transistor on the surface side And a second gate pad. A semiconductor chip having the first source pad, the first gate pad, the second gate pad, and the second source pad arranged in order from one direction is placed on an island of a lead frame. Mounting process,
(B) connecting each of the first source pad, the first gate pad, the second gate pad, and the second source pad to a lead pin of the lead frame by a wire;
A method for manufacturing a semiconductor device, wherein the lead pins of the lead frame are a first source pin, a first gate pin, a second gate pin, and a second source pin in order from one pin. （ａ）第１電界効果トランジスタと第２電界効果トランジスタとを備え、その表面側に前記第１電界効果トランジスタの第１ソースパッドと第１ゲートパッドおよび前記第２電界効果トランジスタの第２ソースパッドと第２ゲートパッドとを有し、一方向から順に前記第１ソースパッド、前記第１ゲートパッド、前記第２ゲートパッド、前記第２ソースパッドが配置された半導体チップをリードフレームのアイランド上に搭載する工程と、
（ｂ）前記第１ソースパッド、前記第１ゲートパッド、前記第２ゲートパッドおよび前記第２ソースパッドをそれぞれワイヤにより前記リードフレームのリードピンに接続する工程と、
（ｃ）前記半導体チップを樹脂で封止した後、前記リードフレームの不要箇所を除去する工程と、
（ｄ）前記リードフレームのリードピンを実装基板上の配線パターンに接続する工程とを有し、
前記リードフレームのリードピンを１ピンから順に第１ソースピン、第１ゲートピン、第２ゲートピン、第２ソースピンとし、前記第１および第２ソースピンが接続されるソース用配線パターンが相対的に太く形成されることを特徴とする半導体装置の製造方法。(A) a first field-effect transistor and a second field-effect transistor, and a first source pad and a first gate pad of the first field-effect transistor and a second source pad of the second field-effect transistor on the surface side And a second gate pad. A semiconductor chip having the first source pad, the first gate pad, the second gate pad, and the second source pad arranged in order from one direction is placed on an island of a lead frame. Mounting process,
(B) connecting the first source pad, the first gate pad, the second gate pad, and the second source pad to respective lead pins of the lead frame by wires;
(C) removing unnecessary portions of the lead frame after sealing the semiconductor chip with resin;
(D) connecting a lead pin of the lead frame to a wiring pattern on a mounting board;
The lead pins of the lead frame are a first source pin, a first gate pin, a second gate pin, and a second source pin in order from one pin, and the source wiring pattern to which the first and second source pins are connected is relatively thick. A method for manufacturing a semiconductor device, characterized by being formed. （ａ）第１電界効果トランジスタと第２電界効果トランジスタとを備え、その表面側に前記第１電界効果トランジスタの第１ソースパッドと第１ゲートパッドおよび前記第２電界効果トランジスタの第２ソースパッドと第２ゲートパッドとを有し、一方向から順に前記第１ソースパッド、前記第１ゲートパッド、前記第２ゲートパッド、前記第２ソースパッドが配置された半導体チップをリードフレームのアイランド上に搭載する工程と、
（ｂ）前記第１ソースパッド、前記第１ゲートパッド、前記第２ゲートパッドおよび前記第２ソースパッドをそれぞれワイヤにより前記リードフレームのリードピンに接続する工程とを有し、
前記リードフレームのリードピンを１ピンから順に第１ソースピン、第１ゲートピン、第２ゲートピン、第２ソースピンとし、前記半導体チップの裏面側を前記第１および第２電界効果トランジスタの共通のドレインとすることを特徴とする半導体装置の製造方法。(A) a first field-effect transistor and a second field-effect transistor, and a first source pad and a first gate pad of the first field-effect transistor and a second source pad of the second field-effect transistor on the surface side And a second gate pad. A semiconductor chip having the first source pad, the first gate pad, the second gate pad, and the second source pad arranged in order from one direction is placed on an island of a lead frame. Mounting process,
(B) connecting each of the first source pad, the first gate pad, the second gate pad, and the second source pad to a lead pin of the lead frame by a wire;
The lead pins of the lead frame are referred to as a first source pin, a first gate pin, a second gate pin, and a second source pin in order from one pin, and the back side of the semiconductor chip is connected to a common drain of the first and second field effect transistors. A method of manufacturing a semiconductor device. （ａ）第１電界効果トランジスタと第２電界効果トランジスタとを備え、その表面側に前記第１電界効果トランジスタの第１ソースパッドと第１ゲートパッドおよび前記第２電界効果トランジスタの第２ソースパッドと第２ゲートパッドとを有し、一方向から順に前記第１ソースパッド、前記第１ゲートパッド、前記第２ゲートパッド、前記第２ソースパッドが配置された半導体チップをリードフレームのアイランド上に搭載する工程と、
（ｂ）前記第１ソースパッド、前記第１ゲートパッド、前記第２ゲートパッドおよび前記第２ソースパッドをそれぞれワイヤにより前記リードフレームのリードピンに接続する工程とを有し、
前記リードフレームのリードピンを１ピンから順に第１ソースピン、第１ゲートピン、第２ゲートピン、第２ソースピンとし、前記第１および第２電界効果トランジスタは電池パックの保護回路として機能することを特徴とする半導体装置の製造方法。(A) a first field-effect transistor and a second field-effect transistor, and a first source pad and a first gate pad of the first field-effect transistor and a second source pad of the second field-effect transistor on the surface side And a second gate pad. A semiconductor chip having the first source pad, the first gate pad, the second gate pad, and the second source pad arranged in order from one direction is placed on an island of a lead frame. Mounting process,
(B) connecting each of the first source pad, the first gate pad, the second gate pad, and the second source pad to a lead pin of the lead frame by a wire;
The lead pins of the lead frame are referred to as a first source pin, a first gate pin, a second gate pin, and a second source pin in order from one pin, and the first and second field-effect transistors function as a protection circuit of a battery pack. Manufacturing method of a semiconductor device.
JP2003154307A 2003-05-30 2003-05-30 Manufacturing method of semiconductor device Expired - Fee Related JP4231736B2 (en)

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JP2006196756A (en) * 2005-01-14 2006-07-27 Sharp Corp Method for designing integrated circuit package and its manufacturing method
JP2006295594A (en) * 2005-04-12 2006-10-26 Matsushita Electric Ind Co Ltd Transistor circuit
JP2006324320A (en) * 2005-05-17 2006-11-30 Renesas Technology Corp Semiconductor device
US9654026B2 (en) 2012-08-10 2017-05-16 Mitsubishi Electric Corporation Three-level power converting apparatus with reduced conduction loss
CN113161303A (en) * 2021-03-03 2021-07-23 江苏苏益电器股份有限公司 System-in-package method and structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196756A (en) * 2005-01-14 2006-07-27 Sharp Corp Method for designing integrated circuit package and its manufacturing method
US7458054B2 (en) 2005-01-14 2008-11-25 Sharp Kabushiki Kaisha Method for designing integrated circuit package and method for manufacturing same
JP2006295594A (en) * 2005-04-12 2006-10-26 Matsushita Electric Ind Co Ltd Transistor circuit
JP2006324320A (en) * 2005-05-17 2006-11-30 Renesas Technology Corp Semiconductor device
US9654026B2 (en) 2012-08-10 2017-05-16 Mitsubishi Electric Corporation Three-level power converting apparatus with reduced conduction loss
CN113161303A (en) * 2021-03-03 2021-07-23 江苏苏益电器股份有限公司 System-in-package method and structure

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