JP2004356472A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for reducing the resistance of a gate electrode of gate wiring or the resistances of both of them, and for controlling a threshold voltage even in a CMIS circuit and to provide a method for manufacturing the semiconductor device. <P>SOLUTION: This semiconductor device is provided with an FET having a silicon layer constituted of a source area 2a, a channel area 2 and a drain area 2b formed so as to be projected to an embedded oxide layer 1 and a gate electrode 4 covering the channel area 2 through a gate insulating film 3 from three directions, an inter-layer insulating film 5 where the silicon layer is embedded so that the projecting directional face of the gate electrode 4 can be exposed and gate wiring 6 electrically connected to the exposed projecting directional face of the gate electrode 4. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an electrode wiring structure of a field effect transistor and a method of forming the same.
[0002]
[Prior art]
MISFETs (metal-insulator-semiconductor field-effect transistors) used in semiconductor integrated circuits have simultaneously achieved high-density integration and an increase in driving force by miniaturization of element dimensions, particularly, reduction in gate length. However, it is becoming difficult to establish a technology that satisfies the problems of miniaturization, high speed, and low power consumption in a planar-type element that follows the conventional trend. In recent years, FinFET has been actively studied as a technique for achieving such a task.
[0003]
In the conventional planar FET, a gate electrode is formed above a channel formed on the surface of a single crystal Si via a gate insulating film. In a FinFET, a channel formed on a substrate is formed by a gate insulating film. There has been reported an example in which a structure having a double gate sandwiching both sides from the lateral direction via an intermediary layer is mainly formed of an SOI layer.
[0004]
For example, a hard mask having a two-layer structure of a silicon oxide film and a silicon nitride film is formed on an SOI (Si) layer on a buried oxide film, and the SOI layer in an opening of the hard mask is etched to form a source region. A semiconductor layer region forming a channel region-drain region is formed. Thereafter, sacrificial oxidation is performed to remove etching damage and reduce the thickness of the channel layer, and the sacrificial oxide layer is further removed.
Thereafter, a gate oxide film is formed by thermal oxidation or the like, a conductive film such as polysilicon is formed, and a gate electrode is formed by patterning. By this method, a fine gate electrode having a gate length of 10 nm is formed. Normally, when a fine gate electrode is formed, polysilicon or amorphous silicon developed with the finest processing technology is used (for example, see Non-Patent Document 1).
[0005]
[Non-patent document 1]
Bin Yu, Leland Chang, et al, "FinFET Scaling to 10 nm Gate Length," IEDM.
Tech. Dig. , Dec. 2002, pp 251-254
[0006]
[Problems to be solved by the invention]
Conventionally, a salicide method is used to prevent an increase in resistance of a gate wiring. However, in a device of a generation in which a gate length of 10 nm or less is used, it is necessary to further reduce the resistance of a gate electrode and a wiring.
[0007]
When a metal film is used for a gate electrode, oxidation resistance and chemical resistance are required, and there is a problem that a patterning technique is not yet established as compared with a proven polysilicon patterning technique.
[0008]
When a metal film or a metal silicide film is formed on the gate electrode, the threshold voltage needs to be optimized because both the PMIS and the NMIS FET are provided as in the CMIS circuit. There is a problem that the threshold voltage cannot be controlled.
[0009]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device capable of reducing the resistance of a gate electrode and / or a gate wiring, and a method of manufacturing the same.
[0010]
It is another object of the present invention to provide a semiconductor device capable of controlling a threshold voltage in a CMIS circuit and a method for manufacturing the same.
[0011]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes a silicon layer serving as a source region, a channel region, and a drain region formed so as to protrude above a substrate; an insulating film formed on a surface of the silicon layer; A FET having a gate electrode covering from three directions through a film,
An interlayer insulating film burying the silicon layer so that a surface of the gate electrode in a protruding direction is exposed;
A gate wiring electrically connected to a surface of the exposed gate electrode in a protruding direction.
[0012]
A first silicon layer serving as a source region, a channel region, and a drain region formed so as to protrude above the substrate; a first insulating film formed on a surface of the first silicon layer; A first gate electrode covering the channel region of the first silicon layer from three directions with the first insulating film interposed therebetween;
A second silicon layer serving as a source region, a channel region, and a drain region formed so as to protrude above the substrate; a second insulating film formed on a surface of the second silicon layer; A second gate electrode covering the channel region of the silicon layer from three directions with the second insulating film interposed therebetween;
An interlayer insulating film for burying the FET in the NMIS region and the FET in the PMIS region such that the protruding surfaces of the first and second gate electrodes are exposed;
A gate line electrically connected to the exposed surface of the first gate electrode in the protruding direction and a gate line electrically connected to the surface of the second gate electrode in the protruding direction.
[0013]
A method of manufacturing a semiconductor device according to the present invention includes a first step of patterning a silicon layer on a substrate to form an FET having a source region, a channel region, and a drain region projecting on the substrate,
A second step of forming an insulating film on the patterned silicon layer surface,
A third step of forming a gate electrode covering the three directions of the channel region with the insulating film interposed therebetween;
A fourth step of forming an interlayer insulating film,
A fifth step of flattening the interlayer insulating film and exposing a surface of the gate electrode in a protruding direction from the interlayer insulating film;
A sixth step of forming and patterning a conductive film to form a gate wiring electrically connected to the exposed surface of the gate electrode in the protruding direction.
[0014]
A first step of patterning a silicon layer on the substrate to form a silicon layer of an NMIS region and a PMIS region having a source region, a channel region, and a drain region projecting on the substrate;
A second step of forming an insulating film on the patterned silicon layer surface,
A third step of forming a gate electrode made of polysilicon or amorphous silicon covering the three directions of the channel region via the insulating film;
A fourth step of forming an interlayer insulating film,
A fifth step of flattening the interlayer insulating film and exposing a surface of the gate electrode in a protruding direction from the interlayer insulating film;
One gate electrode of the NMIS region or the PMIS region is covered with a silicide prevention film, and the other gate electrode is further covered with a first metal film. A sixth step of reacting polysilicon or amorphous silicon to turn the other gate electrode into a metal silicide;
The silicide prevention film is removed, the other gate electrode in the NMIS region or the PMIS region is covered with a silicide prevention film, and the second gate film is made of a second metal film of a type different from the first metal film. A seventh step of covering said gate electrode and reacting said second metal film with polysilicon or amorphous silicon of said one gate electrode by heat treatment to convert said one gate electrode to metal silicide;
An eighth step of forming and patterning a conductive film to form a gate wiring electrically connected to the exposed surface of each gate electrode in the protruding direction.
[0015]
A first step of patterning a silicon layer on the substrate to form a silicon layer of an NMIS region and a PMIS region having a source region, a channel region, and a drain region projecting on the substrate;
A second step of forming an insulating film on the patterned silicon layer surface,
A third step of forming a dummy gate electrode made of polysilicon or amorphous silicon covering the three directions of the channel region via the insulating film;
A fourth step of forming an interlayer insulating film,
A fifth step of flattening the interlayer insulating film and exposing a surface of the dummy gate electrode in a projecting direction from the interlayer insulating film;
One dummy gate electrode of the NMIS region FET or PMIS region is covered with a first etching mask, the other dummy gate electrode is removed, the first etching mask is removed, and the other dummy gate electrode is removed. A sixth step of burying the first metal film in the removed portion to form a gate electrode;
Covering the other dummy gate electrode in the NMIS region or PMIS region with a second etching mask, removing the one dummy gate electrode, removing the second etching mask, and removing the one gate electrode A seventh step of burying a second metal film of a type different from the first metal film in the portion thus formed to form a gate electrode;
An eighth step of forming and patterning a conductive film to form a gate wiring electrically connected to the exposed surface of each gate electrode in the protruding direction.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a sectional view (a) and a plan view (b) showing a first embodiment of a semiconductor device according to the present invention, and the sectional view (a) shows an AA section of the plan view (b). I have.
[0017]
As shown in FIG. 1B, fin-type silicon (Si) having a source region 2a, a channel region 2, and a drain region 2b protruding is formed on a buried oxide layer 1 (substrate). As shown in FIG. 1A, the periphery (surface in three directions) of the channel region 2 is made of polysilicon or amorphous silicon via a gate insulating film 3 and a hard mask 10 formed on the channel region 2. Gate electrode 4 is formed. The gate electrode 4 is embedded in the interlayer insulating film 5, the upper surface is exposed from the interlayer insulating film 5, and a gate wiring 6 made of a metal connected to the exposed surface of the gate electrode 4 is formed on the interlayer insulating film 5. I have. Note that a silicon substrate may be used instead of the buried oxide layer 1.
[0018]
According to this configuration, since the gate electrode 4 and the gate wiring 6 connected to the gate electrode 4 can be formed independently, the resistance of the gate wiring 6 can be arbitrarily reduced.
[0019]
In addition, since the interlayer insulating film 5 is flattened and the gate wiring 6 can be formed on the flattened interlayer insulating film 5, patterning of the gate wiring 6 can be easily performed.
[0020]
2 and 3 are cross-sectional views illustrating a manufacturing process for manufacturing the semiconductor device of the present embodiment. The manufacturing method will be described with reference to FIG.
[0021]
First, a hard mask having a two-layer structure of a silicon oxide film 26 and a silicon nitride film 27 is formed on the silicon layer 25 on the buried oxide film 1, and the silicon layer 25 at the opening of the hard mask is etched to obtain a source. A semiconductor layer region forming a region-channel region-drain region is formed. FIG. 2B shows the formed semiconductor layer region.
[0022]
Next, as shown in FIG. 2A, a photoresist 28 corresponding to the source region-channel region-drain region is formed on the silicon nitride film 27, and as shown in FIG. Using the resist 28 as a mask, the silicon oxide film 26, the silicon nitride film 27, and the silicon layer 25 are etched to form a source region, a channel region, and a drain region.
[0023]
Next, as shown in FIG. 2C, sacrificial oxidation is performed to form a sacrificial oxide layer 29 in order to remove etching damage and reduce the thickness of the channel layer. As described above, the sacrificial oxide layer 29 is removed.
[0024]
Next, as shown in FIG. 2E, a gate oxide film 3 is formed by thermal oxidation or the like. As described above, a fine fin-type gate electrode having a gate length of 10 nm is formed by a method similar to the method described in Non-Patent Document 1.
[0025]
Next, as shown in FIG. 3A, a polysilicon film or an amorphous silicon film is formed around the channel region 2 via the gate oxide film 3 and the hard mask 10 (the silicon oxide film 26 in FIG. 2) by CVD. The gate electrode 4 is formed by forming the gate electrode 4 by patterning to a width L of the channel region 2 of 50 to 100 nm.
[0026]
The width L is a value obtained by adding the thickness of the silicon layer, which is the channel region 2, twice the thickness of the gate insulating film 3, and twice the thickness of the gate electrode 4, in consideration of the lithography overlay accuracy. The value is obtained by adding twice the value. The width L and the value (height) in the vertical direction are gate length values. For example, if the thickness of the silicon layer is 10 nm, the thickness of the gate insulating film 3 is 1.7 nm, the thickness of the polysilicon film is 50 nm, and the overlay accuracy of lithography is 30 nm, L is set to 173.4 nm.
[0027]
Next, as shown in FIG. 3B, a silicon oxide film serving as an interlayer insulating film 5 is formed by a CVD method or the like, and is planarized by a CMP method (chemical mechanical polishing method) to expose the upper surface of the gate electrode 4. Let it.
[0028]
Next, as shown in FIG. 3C, a metal film, for example, W (tungsten), an Al-Cu alloy (aluminum-copper alloy), or Cu is formed by sputtering or CVD, and is patterned. A low-resistance gate wiring 6 made of a metal film is formed.
[0029]
When a metal film is formed in FIG. 3C, a TiN (titanium nitride) film, a laminated film of TiN and Ti, a TaN (tantalum nitride) film, or a TaN And a stacked film of Ta and Ta.
[0030]
In FIG. 3A, an alloy of silicon and germanium may be used instead of polysilicon and amorphous silicon.
[0031]
As described above, in the manufacturing method according to the present embodiment, the gate electrode 4 and the gate wiring 6 connected to the gate electrode 4 are formed independently, so that the resistance of the gate wiring 6 can be arbitrarily reduced. it can.
[0032]
Further, since the interlayer insulating film 5 is flattened and the gate wiring 6 is formed on the flattened interlayer insulating film 5, patterning of the gate wiring 6 can be easily performed.
[0033]
In this embodiment, an example in which the fin-type FET is formed on the buried oxide layer 1 has been described, but the fin-type FET may be formed on a silicon substrate.
[0034]
Embodiment 2 FIG.
In the first embodiment, polysilicon or amorphous silicon is used for the gate electrode 4. However, depletion of polysilicon or amorphous silicon hinders improvement in transistor performance. Therefore, in order to prevent depletion, the gate electrode 4 is made of metal silicide instead of polysilicon or amorphous silicon.
[0035]
FIG. 4 is a cross-sectional view showing a manufacturing process for manufacturing the semiconductor device of the present embodiment.
A manufacturing method in the case where polysilicon is used for the gate electrode 4 will be described with reference to FIG.
[0036]
After the steps up to FIG. 3B as in the first embodiment, as shown in FIG. 4A, the metal film 7, for example, cobalt, nickel, titanium, tantalum, vanadium, platinum, Alternatively, these alloy films are formed to a thickness of 10 to 30 nm by, for example, a PVD method.
[0037]
Next, heat treatment is performed. The heat treatment is performed, for example, by heating at 400 to 600 ° C. for 60 seconds in a nitrogen gas or inert gas atmosphere. By this heat treatment, the metal film 7 and the polysilicon 8 react to form a metal silicide film 9.
[0038]
Since the metal film 7 does not cause a silicidation reaction in a region not in contact with the polysilicon 8, the metal film 7 remains as the metal film 7. Therefore, an acid, for example, a mixed solution of sulfuric acid and hydrogen peroxide or hydrochloric acid and hydrogen peroxide The unreacted metal film 7 is removed by the mixed solution of the above. As a result, the polysilicon 8 is replaced with the metal silicide 9 as shown in FIG.
[0039]
Thereafter, as shown in FIG. 4C, a metal film, for example, W (tungsten), an Al—Cu alloy (aluminum-copper alloy), or Cu (copper) is formed by a sputtering method or a CVD method. By patterning, a low-resistance gate wiring 6 made of a metal film is formed.
[0040]
Embodiment 3 FIG.
In the first and second embodiments, for example, when patterning is performed on polysilicon, since the polysilicon is formed on the channel region 2, the lithography is performed on the height of the channel region 2, for example, on a step of 50 to 60 nm. Will be applied. Such a step makes it difficult to pattern the polysilicon.
[0041]
FIG. 5 is a cross-sectional view showing a manufacturing process for manufacturing the semiconductor device of the present embodiment.
As shown in FIG. 5A, after the polysilicon 8 is formed thick so as to bury the channel region 2, it is planarized by the CMP method. The thickness of the polysilicon 8 is larger than at least the sum of the channel region 2 and the hard mask 10. For example, when the channel region 2 is 50 nm and the hard mask 10 is 30 nm, the thickness of the polysilicon 8 is 150 nm.
[0042]
Next, as shown in FIG. 5B, a photoresist 11 is formed on the planarized polysilicon 8 by a lithography technique, and the polysilicon 8 is patterned using the photoresist 11 as a mask. At this time, a hard mask of a silicon oxide film or a silicon nitride film may be formed on the polysilicon 8 and a photoresist may be formed thereon.
[0043]
Next, as shown in FIG. 5C, a silicon oxide film is formed by a CVD method, planarized by a CMP method, and an interlayer insulating film 5 is formed so that the upper surface of the polysilicon 8 is exposed.
[0044]
In the subsequent steps, a gate wiring is formed as in the first embodiment. Alternatively, the gate wiring is formed after the polysilicon 8 is converted into metal silicide as in the second embodiment.
[0045]
According to the present embodiment, the lithography technique can be applied on the planarized polysilicon 8, so that the polysilicon 8 can be easily patterned.
[0046]
Embodiment 4 FIG.
In the present embodiment, a metal film is used instead of polysilicon in order to prevent depletion in polysilicon or the like of the gate electrode 4 and reduce resistance.
[0047]
In the second embodiment, metal silicide is used instead of polysilicon. However, by using a metal film, the resistance can be further reduced.
[0048]
FIG. 6 is a cross-sectional view showing a manufacturing process for manufacturing the semiconductor device of the present embodiment. After forming the polysilicon 8 as shown in FIG. 5C, the polysilicon 8 is removed by a dry etching method as shown in FIG. 6A. At this time, since the purpose is to remove the polysilicon 8, the anisotropic etching is not required and the isotropic etching may be used.
[0049]
Next, as shown in FIG. 6B, a metal film 12 composed of a two-layer film of a TiN film 12a and a W film 12b is formed on the region from which the polysilicon 8 has been removed and on the interlayer insulating film 5 by the CVD method. Embed.
[0050]
Since W has poor adhesion to the interlayer insulating film 5 made of a silicon oxide film, a TiN film 12a is formed below the W film 12b as an adhesion layer. Further, since TiN does not react with the gate insulating film 3 made of a silicon oxide film, the gate insulating film 3 does not deteriorate.
As a base film of the W film, other than TiN, any metal or metal compound which has good adhesion to a silicon oxide film and does not react with the gate insulating film 3 can be used.
[0051]
Next, as shown in FIG. 6C, the metal film 12 is patterned by lithography to form a gate wiring.
[0052]
In this embodiment, the step of removing the polysilicon 8 after the step of FIG. 5C has been described. However, as shown in FIG. 7A, after the step of FIG. The gate electrode 4 made of silicon may be removed. Subsequent steps are the same as those in FIG. 6, and the gate electrode 4 and the gate wiring 6 shown in FIG. 7B are obtained.
[0053]
Embodiment 5 FIG.
In the first to fourth embodiments, a thermal oxide film is used as the gate insulating film 3. In the present embodiment, a high-dielectric-constant film is used for further effective thinning of the gate insulating film.
[0054]
FIG. 8 is a cross-sectional view showing a step of forming the high dielectric constant film of the present embodiment. After the step of FIG. 6A or the step of FIG. 7A, as shown in FIG. 8A, the gate oxide film 3 made of a silicon oxide film is removed using, for example, hydrofluoric acid.
[0055]
Next, as shown in FIG. 8B, an insulating film having a high dielectric constant, for example, a high dielectric constant film 13 such as a hafnium oxide film, an alumina film, a hafnium silicon oxide film, or a tantalum oxide film is formed by a CVD method. Form.
[0056]
Thereafter, the gate electrode 4 and the gate wiring 6 are formed by the steps shown in FIGS. 6B and 6C.
[0057]
In the present embodiment, since the high dielectric constant film 13 is used for the gate insulating film, the gate insulating film can be effectively thinned.
[0058]
Embodiment 6 FIG.
In the first to fifth embodiments, the hard mask 10 is left. In the present embodiment, the hard mask 10 is removed, the upper part of the channel region 2 is also surrounded by the gate electrode 4, the electric field of the channel is controlled, and the performance of the transistor is improved.
[0059]
FIG. 9 is a cross-sectional view illustrating the manufacturing process of the present embodiment. As shown in FIG. 9A, in the step of FIG. 5C, an interlayer insulating film 14 made of a silicon nitride film is formed by a CVD method instead of a silicon oxide film, and is planarized by a CMP method. The upper surface of the gate electrode 4 is exposed.
[0060]
Next, as shown in FIG. 9B, the gate electrode 4, the hard mask 10, and the gate insulating film 3 made of polysilicon are removed with hydrofluoric acid or the like.
[0061]
Next, as shown in FIG. 9C, a gate insulating film 15 made of a silicon oxide film or a high dielectric constant film is formed by a CVD method.
[0062]
Thereafter, the gate electrode 4 and the gate wiring 6 made of a metal film are formed by the steps shown in FIGS. 6B and 6C.
[0063]
Embodiment 7 FIG.
In the first to sixth embodiments, the gate electrode 4 made of polysilicon is formed while the hard mask 10 is left. However, the gate electrode 4 made of polysilicon may be formed after the hard mask 10 is removed.
[0064]
FIG. 10 is a cross-sectional view showing a step after the hard mask 10 of the present embodiment is removed. After the step of FIG. 2D, the hard mask 10 is removed by a dry etching method.
[0065]
Next, as shown in FIG. 10A, a gate insulating film 3 is formed by a thermal oxidation method or a CVD method, and then a polysilicon film is formed by a CVD method, and the polysilicon film is formed by a combination of lithography and etching. Is formed.
[0066]
Next, as shown in FIG. 10B, an interlayer insulating film 5 made of a silicon oxide film and a gate wiring 6 are formed in the same manner as in the steps of FIGS. 3B and 3C.
[0067]
According to the present embodiment, the upper portion of channel region 2 can be surrounded by gate electrode 4 in a simpler process than in the sixth embodiment.
[0068]
Embodiment 8 FIG.
In a CMIS circuit including N-type and P-type MIS transistors, if the same metal is used for the gate electrodes of the N-type and P-type MIS transistors, the work functions of the gate electrodes of both transistors become the same. The threshold value of each MIS transistor cannot be optimized.
[0069]
The present embodiment provides a manufacturing method capable of controlling a threshold voltage of a gate electrode made of metal silicide in a circuit having both a PMIS and an NMIS FET of a CMIS circuit.
[0070]
11 and 12 are cross-sectional views illustrating the manufacturing steps of the present embodiment. First, after forming the PMIS region and the NMIS region FET in the process of FIG. 3 or FIG. 5, as shown in FIG. 11A, the upper surface of the PMIS region gate electrode 4 is covered and the NMIS region gate electrode 4 is formed. Anti-silicide film 16 is formed such that the upper surface of is exposed. The silicide prevention film 16 is formed, for example, by forming a silicon oxide film to a thickness of 50 nm by a normal pressure CVD method and removing an NMIS region of the silicon oxide film formed by lithography and dry etching or wet etching.
[0071]
Next, as shown in FIG. 11B, for example, a cobalt film is formed to a thickness of 10 to 15 nm as a first metal film 17 by a PVD method.
[0072]
Next, by performing a heat treatment of heating at 400 to 600 ° C. for 60 seconds, the polysilicon of the gate electrode 4 in the NMIS region reacts with the cobalt of the first metal film 17, as shown in FIG. As described above, the gate electrode in the NMIS region is the first metal silicide 18 made of a cobalt silicide film, and the unreacted cobalt film and the silicide prevention film 16 are selectively removed by using a mixed solution of sulfuric acid and hydrogen peroxide. I do. At this time, the PMIS region gate electrode 4 is prevented from reacting with the cobalt of the first metal film 17 by the silicide prevention film 16.
[0073]
The first metal film 17 may be made of nickel, platinum, other than cobalt.
[0074]
Next, as shown in FIG. 12A, the silicide prevention film 16 is formed so as to cover the first metal silicide 18 in the NMIS region and expose the upper surface of the gate electrode 4 in the PMIS region. The silicide prevention film 16 is formed, for example, by forming a silicon oxide film to a thickness of 50 nm by a normal pressure CVD method and removing the silicon oxide film in the PMIS region of the silicon oxide film formed by lithography and dry etching or wet etching. I do.
[0075]
Next, a second metal film, for example, a titanium film is formed to a thickness of 10 to 15 nm by a PVD method, and is subjected to a heat treatment of heating at 600 to 800 ° C. for 60 seconds to form polysilicon of the gate electrode 4 and the second metal film. Then, as shown in FIG. 12B, the gate electrode 4 is made to be a second metal silicide 19 made of titanium silicide. At this time, the first metal silicide 18 in the NMIS region is prevented from reacting with titanium in the second metal film by the silicide prevention film 16.
[0076]
Note that the second metal film can be made of tantalum or tungsten in addition to titanium.
[0077]
The silicide prevention film 16 may be a compound such as a silicon nitride film or titanium nitride (TiN), in addition to a silicon oxide film. In the case of TiN, after the metal film is silicided, it can be removed simultaneously in the step of selectively removing the metal film.
[0078]
Next, the unreacted titanium film and the silicide prevention film 16 are selectively removed with a mixed solution of sulfuric acid and hydrogen peroxide.
[0079]
Next, as shown in FIG. 12C, the gate wiring 6 is formed in the same manner as in the first embodiment.
[0080]
As described above, according to the present embodiment, the gate electrodes made of different materials can be formed in the NMIS region PMIS region, so that the first metal silicide film and the second metal silicide film having different work functions can be formed. By arbitrarily selecting the gate electrodes of the NMIS and PMIS FETs, the threshold voltage of each conductivity type FET can be controlled.
[0081]
Embodiment 9 FIG.
13 and 14 are cross-sectional views showing the manufacturing steps of the present embodiment. In the eighth embodiment, the case where the metal silicide film is used as the gate electrode of the NMIS and PMIS FETs is described. In the present embodiment, a metal film is used instead of the metal silicide film.
[0082]
First, after forming the FETs in the PMIS region and the NMIS region in the process of FIG. 3 or FIG. 5, as shown in FIG. 13A, the upper surface of the gate electrode 4 in the PMIS region is covered and the gate electrode 4 in the NMIS region is formed. An etching mask made of a photoresist 20 is formed by lithography so that the upper surface of the substrate is exposed, and the dummy gate electrode in the NMIS region is removed by etching.
[0083]
Next, after removing the photoresist 20, as shown in FIG. 13B, a first metal film 21 for NMIS is formed by sputtering or CVD. For example, tantalum is formed as the first metal film 21. As the first metal film 21, besides tantalum, hafnium, magnesium, zirconium, or aluminum can be used.
[0084]
Next, as shown in FIG. 13C, the first metal film 21 is left only in the gate electrode portion of the NMIS region by the CMP method or the etch-back method.
[0085]
Next, as shown in FIG. 14A, a photoresist is formed by lithography so as to cover the upper surface of the first metal film 21 (gate electrode) in the NMIS region and expose the upper surface of the gate electrode portion in the PMIS region. An etching mask made of 20 is formed, and the gate electrode portion in the PMIS region is removed by an etching method.
[0086]
Next, the photoresist 20 is removed, a second metal film 22 for PMIS, for example, tungsten is formed by sputtering or CVD, and as shown in FIG. By the method, the second metal film 22 is left only in the gate electrode portion in the PMIS region.
[0087]
The second metal film 22 can be made of ruthenium, rhenium, or platinum in addition to tungsten.
[0088]
Next, as shown in FIG. 14C, the gate wiring 6 is formed in the same manner as in the first embodiment.
[0089]
As described above, according to the present embodiment, the gate electrodes made of different materials can be formed in the NMIS region and the PMIS region, so that the first metal film and the second metal film having different work functions can be formed by NMIS. Also, by arbitrarily selecting the gate electrode of the PMIS FET, the threshold voltage of each conductivity type FET can be controlled.
[0090]
Embodiment 10 FIG.
This embodiment is different from the ninth embodiment in that a high dielectric constant film is formed as a gate insulating film.
[0091]
15 to 17 are cross-sectional views illustrating the manufacturing steps of the present embodiment. First, after forming FETs in the PMIS region and the NMIS region in the process of FIG. 3 or FIG. 5, as shown in FIG. 15A, the upper surface of the gate electrode 8 in the PMIS region is covered, An etching mask made of the photoresist 20 is formed by lithography so that the upper surface is exposed, the dummy gate electrode in the NMIS region is removed by etching, and the gate insulating film in the gate electrode portion is wet-etched with hydrofluoric acid or the like. It is removed by dry etching using HF gas.
[0092]
Next, after the photoresist 20 is removed, as shown in FIG. 15B, a hafnium oxide film is formed to a thickness of 10 to 50 nm by a CVD method to form a first gate insulating film 23. .
[0093]
The first gate insulating film 23 can be made of zirconium oxide, tantalum oxide, aluminum oxide, or a compound of these and silicon, in addition to hafnium oxide.
[0094]
Further, the first gate insulating film 23 may be a laminated film of a high dielectric constant film and a silicon oxide film formed by a thermal oxidation method or a plasma oxidation method.
[0095]
Next, a first metal film for NMIS is formed by a sputtering method or a CVD method, and as shown in FIG. 15C, only a gate electrode portion of the NMIS region is formed by a CMP method or an etch-back method. The first metal film 21 is left.
[0096]
Next, an etching mask made of a photoresist 20 is formed by lithography so as to cover the upper surface of the first metal film 21 in the NMIS region and expose the upper surface of the gate electrode 4 in the PMIS region. As shown, the gate electrode 4 in the PMIS region is removed by an etching method, and the gate insulating film in the gate electrode portion is removed by wet etching with hydrofluoric acid or the like or dry etching with HF gas.
[0097]
Next, the photoresist 20 is removed, and as shown in FIG. 16B, a hafnium oxide film is formed to a thickness of 10 to 50 nm by a CVD method to form a second gate insulating film 24.
[0098]
Note that the second gate insulating film 24 can be made of zirconium oxide, tantalum oxide, aluminum oxide, or a compound of these and silicon, in addition to hafnium oxide.
[0099]
Further, the second gate insulating film 24 may be a laminated film of a high dielectric constant film and a silicon oxide film formed by a thermal oxidation method or a plasma oxidation method.
[0100]
Next, a second metal film 22 for PMIS, for example, tungsten is formed by sputtering or CVD, and a dummy in the PMIS region is formed by CMP or etch-back as shown in FIG. The second metal film 22 is left only in the gate electrode portion.
[0101]
The second metal film 22 can be made of ruthenium, rhenium, or platinum in addition to tungsten.
[0102]
Next, as shown in FIG. 17, the gate wiring 6 is formed in the same manner as in the first embodiment.
[0103]
In this embodiment, since the first gate insulating film 23 and the second gate insulating film 24 are made of a high dielectric constant film, the first and second gate insulating films 23 and 24 can be effectively thinned. Will be possible.
[0104]
【The invention's effect】
According to the semiconductor device of the present invention, the source region, the silicon layer that becomes the channel region and the drain region formed so as to protrude above the substrate, the insulating film formed on the surface of the silicon layer, and the channel region An FET having a gate electrode covering from three directions with the insulating film interposed therebetween;
An interlayer insulating film burying the silicon layer so that a surface of the gate electrode in a protruding direction is exposed;
Since a gate wiring electrically connected to the exposed surface of the gate electrode in the protruding direction is provided, the resistance of the gate wiring can be arbitrarily reduced.
[0105]
A first silicon layer serving as a source region, a channel region, and a drain region formed so as to protrude above the substrate; a first insulating film formed on a surface of the first silicon layer; A first gate electrode covering the channel region of the first silicon layer from three directions with the first insulating film interposed therebetween;
A second silicon layer serving as a source region, a channel region, and a drain region formed so as to protrude above the substrate; a second insulating film formed on a surface of the second silicon layer; A second gate electrode covering the channel region of the silicon layer from three directions with the second insulating film interposed therebetween;
An interlayer insulating film for burying the FET in the NMIS region and the FET in the PMIS region such that the protruding surfaces of the first and second gate electrodes are exposed;
A gate wiring electrically connected to the surface of the exposed first gate electrode in the protruding direction, and a gate wiring electrically connected to the surface of the second gate electrode in the protruding direction. In addition, the resistance of the gate wiring can be arbitrarily reduced.
[0106]
According to the method for manufacturing a semiconductor device of the present invention, a first step of patterning a silicon layer on a substrate to form an FET having a source region, a channel region, and a drain region projecting on the substrate,
A second step of forming an insulating film on the patterned silicon layer surface,
A third step of forming a gate electrode covering the three directions of the channel region with the insulating film interposed therebetween;
A fourth step of forming an interlayer insulating film,
A fifth step of flattening the interlayer insulating film and exposing a surface of the gate electrode in a protruding direction from the interlayer insulating film;
Forming a conductive film and patterning it to form a gate wiring electrically connected to the exposed surface of the gate electrode in the protruding direction. Can be arbitrarily reduced.
[0107]
A first step of patterning a silicon layer on the substrate to form a silicon layer of an NMIS region and a PMIS region having a source region, a channel region, and a drain region projecting on the substrate;
A second step of forming an insulating film on the patterned silicon layer surface,
A third step of forming a gate electrode made of polysilicon or amorphous silicon covering the three directions of the channel region via the insulating film;
A fourth step of forming an interlayer insulating film,
A fifth step of flattening the interlayer insulating film and exposing a surface of the gate electrode in a protruding direction from the interlayer insulating film;
One gate electrode of the NMIS region or the PMIS region is covered with a silicide prevention film, and the other gate electrode is further covered with a first metal film. A sixth step of reacting polysilicon or amorphous silicon to turn the other gate electrode into a metal silicide;
The silicide prevention film is removed, the other gate electrode in the NMIS region or the PMIS region is covered with a silicide prevention film, and the second gate film is made of a second metal film of a type different from the first metal film. A seventh step of covering said gate electrode and reacting said second metal film with polysilicon or amorphous silicon of said one gate electrode by heat treatment to convert said one gate electrode to metal silicide;
An eighth step of forming a conductive film and patterning the same to form a gate wiring electrically connected to the exposed surface of each gate electrode in the protruding direction. The resistance of the gate electrode can be arbitrarily reduced.
[0108]
A first step of patterning a silicon layer on the substrate to form a silicon layer of an NMIS region and a PMIS region having a source region, a channel region, and a drain region projecting on the substrate;
A second step of forming an insulating film on the patterned silicon layer surface,
A third step of forming a dummy gate electrode made of polysilicon or amorphous silicon covering the three directions of the channel region via the insulating film;
A fourth step of forming an interlayer insulating film,
A fifth step of flattening the interlayer insulating film and exposing a surface of the dummy gate electrode in a projecting direction from the interlayer insulating film;
One dummy gate electrode of the NMIS region FET or PMIS region is covered with a first etching mask, the other dummy gate electrode is removed, the first etching mask is removed, and the other dummy gate electrode is removed. A sixth step of burying the first metal film in the removed portion to form a gate electrode;
Covering the other dummy gate electrode in the NMIS region or PMIS region with a second etching mask, removing the one dummy gate electrode, removing the second etching mask, and removing the one gate electrode A seventh step of burying a second metal film of a type different from the first metal film in the portion thus formed to form a gate electrode;
An eighth step of forming a conductive film and patterning the same to form a gate wiring electrically connected to the exposed surface of each gate electrode in the protruding direction. The resistance of the gate electrode can be arbitrarily reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment.
FIG. 2 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment;
FIG. 3 is a sectional view illustrating a manufacturing step of the semiconductor device of First Embodiment;
FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment.
FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device of the third embodiment.
FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device of the fourth embodiment.
FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device of the fourth embodiment.
FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device of the fifth embodiment.
FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device of the sixth embodiment.
FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device of the seventh embodiment.
FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device of the eighth embodiment.
FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device of the eighth embodiment.
FIG. 13 is a sectional view showing a manufacturing step of the semiconductor device of the ninth embodiment;
FIG. 14 is a sectional view illustrating a manufacturing step of the semiconductor device of the ninth embodiment;
FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device of the tenth embodiment.
FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device of the tenth embodiment.
FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device of the tenth embodiment.
[Explanation of symbols]
1 buried oxide layer, 2 channel region, 2a source region,
2b drain region, 3,15 gate insulating film, 4 gate electrode,
5,14 interlayer insulating film, 6 gate wiring, 7,12 metal film,
8 polysilicon, 9 metal silicide, 10 hard mask,
11, 20, 24, 28 photoresist, 12a TiN film, 12b W film,
13 high dielectric constant film, 16 silicide prevention film, 17, 21 first metal film,
18 first metal silicide, 19 second metal silicide,
22 second metal film, 23 first gate insulating film, 24 second gate insulating film,
25 silicon, 26 silicon oxide film, 27 silicon nitride film,
29 Sacrificial oxide film.

Claims (23)

A silicon layer serving as a source region, a channel region, and a drain region formed so as to protrude above the substrate; an insulating film formed on the surface of the silicon layer; and covering the channel region from three directions via the insulating film. FET having a gate electrode,
An interlayer insulating film burying the silicon layer so that a surface of the gate electrode in a protruding direction is exposed;
A semiconductor device comprising: a gate wiring electrically connected to a surface of the exposed gate electrode in a protruding direction. 2. The semiconductor device according to claim 1, wherein said gate electrode is made of silicon or an alloy of silicon and germanium. 2. The semiconductor device according to claim 1, wherein said gate electrode is made of metal silicide. 2. The semiconductor device according to claim 1, wherein said gate electrode is made of a metal. A first silicon layer serving as a source region, a channel region, and a drain region formed so as to protrude above the substrate; a first insulating film formed on a surface of the first silicon layer; A first gate electrode covering the channel region of the silicon layer from three directions with the first insulating film interposed therebetween;
A second silicon layer serving as a source region, a channel region, and a drain region formed so as to protrude above the substrate; a second insulating film formed on a surface of the second silicon layer; A second gate electrode covering the channel region of the silicon layer from three directions with the second insulating film interposed therebetween;
An interlayer insulating film for burying the FET in the NMIS region and the FET in the PMIS region such that the protruding surfaces of the first and second gate electrodes are exposed;
A gate line electrically connected to the exposed surface of the first gate electrode in the protruding direction and a gate line electrically connected to the surface of the second gate electrode in the protruding direction. Semiconductor device. 6. The semiconductor device according to claim 5, wherein said first gate electrode and said second gate electrode are made of metal silicides having different work functions. 6. The semiconductor device according to claim 5, wherein said first gate electrode and said second gate electrode are made of metals having different work functions. 6. The semiconductor device according to claim 1, wherein said insulating film is a high dielectric constant film. A first step of patterning a silicon layer on a substrate to form an FET having a source region, a channel region, and a drain region protruding above the substrate;
A second step of forming an insulating film on the patterned silicon layer surface,
A third step of forming a gate electrode covering the three directions of the channel region with the insulating film interposed therebetween;
A fourth step of forming an interlayer insulating film,
A fifth step of flattening the interlayer insulating film and exposing a surface of the gate electrode in a protruding direction from the interlayer insulating film;
Manufacturing a semiconductor device, comprising: forming a conductive film and patterning the same to form a gate wiring electrically connected to the exposed surface of the gate electrode in the protruding direction. Method. The gate electrode formed in the third step is made of polysilicon or amorphous silicon, and after the fifth step and before the sixth step, a metal film is formed and heat treatment is performed. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the gate electrode is made of metal silicide by reacting amorphous silicon with the metal film. After the second step and before the third step, a film of polysilicon or amorphous silicon for embedding the FET is formed, and the formed polysilicon or amorphous silicon is planarized. 10. The method according to claim 9, wherein the gate electrode is formed by patterning the flattened polysilicon or amorphous silicon. After the fifth step and before the sixth step, the polysilicon or the amorphous silicon is removed, and a conductive film is formed on the removed portion and on the interlayer insulating film. Item 12. The method for manufacturing a semiconductor device according to item 11. The gate electrode formed in the third step is made of polysilicon or amorphous silicon. After the fifth step and before the sixth step, the polysilicon or amorphous silicon is removed, and the removed portion and the interlayer are removed. 10. The method according to claim 9, wherein a conductive film is formed on the insulating film. Removing the insulating film when removing the polysilicon or the amorphous silicon, and forming a new insulating film on the patterned silicon layer surface before forming a conductive film on the removed portion. 14. The method of manufacturing a semiconductor device according to claim 12, wherein: An etching mask film is formed on the silicon layer before the first step, and the silicon layer is patterned together with the etching mask film in the first step. After the fifth step, the sixth layer is formed. Before the step, the gate electrode, the patterned etching mask film and the insulating film are removed, a new insulating film is formed on the surface of the patterned silicon layer, and a conductive film is formed on the removed portion and the interlayer insulating film. The method for manufacturing a semiconductor device according to claim 9, wherein a conductive film is formed. 16. The method according to claim 12, wherein the conductive film is a metal film. The method according to claim 15, wherein the interlayer insulating film is a silicon nitride film. After forming an etching mask film on the silicon layer before the first step, patterning the silicon layer together with the etching mask film in the first step, and etching the silicon layer before the second step. 10. The method according to claim 9, wherein the mask film is removed. A first step of patterning a silicon layer on the substrate to form a silicon layer of an NMIS region and a PMIS region having a source region, a channel region, and a drain region protruding above the substrate;
A second step of forming an insulating film on the patterned silicon layer surface,
A third step of forming a gate electrode made of polysilicon or amorphous silicon covering the three directions of the channel region via the insulating film;
A fourth step of forming an interlayer insulating film,
A fifth step of flattening the interlayer insulating film and exposing a surface of the gate electrode in a protruding direction from the interlayer insulating film;
One gate electrode of the NMIS region or the PMIS region is covered with a silicide prevention film, and the other gate electrode is further covered with a first metal film. A sixth step of reacting polysilicon or amorphous silicon to turn the other gate electrode into a metal silicide;
The silicide prevention film is removed, the other gate electrode in the NMIS region or the PMIS region is covered with a silicide prevention film, and the second gate film is made of a second metal film of a type different from the first metal film. A seventh step of covering said gate electrode and reacting said second metal film with polysilicon or amorphous silicon of said one gate electrode by heat treatment to convert said one gate electrode to metal silicide;
An eighth step of forming a conductive film and patterning to form a gate wiring electrically connected to the exposed surface of each gate electrode in the protruding direction. Production method. 20. The method according to claim 19, wherein the silicide prevention film is a silicon oxide film, a silicon nitride film, or a TiN film. A first step of patterning a silicon layer on the substrate to form a silicon layer of an NMIS region and a PMIS region having a source region, a channel region, and a drain region protruding above the substrate;
A second step of forming an insulating film on the patterned silicon layer surface,
A third step of forming a dummy gate electrode made of polysilicon or amorphous silicon covering the three directions of the channel region via the insulating film;
A fourth step of forming an interlayer insulating film,
A fifth step of flattening the interlayer insulating film and exposing a surface of the dummy gate electrode in a projecting direction from the interlayer insulating film;
One dummy gate electrode of the NMIS region FET or PMIS region is covered with a first etching mask, the other dummy gate electrode is removed, the first etching mask is removed, and the other dummy gate electrode is removed. A sixth step of burying the first metal film in the removed portion to form a gate electrode;
Covering the other dummy gate electrode in the NMIS region or PMIS region with a second etching mask, removing the one dummy gate electrode, removing the second etching mask, and removing the one gate electrode A seventh step of burying a second metal film of a type different from the first metal film in the portion thus formed to form a gate electrode;
An eighth step of forming a conductive film and patterning to form a gate wiring electrically connected to the exposed surface of each gate electrode in the protruding direction. Production method. In the sixth step and the seventh step, after the gate electrode is removed, the insulating film is removed, and before the first and second metals are buried, a new insulating film is patterned by silicon. 22. The method for manufacturing a semiconductor device according to claim 21, wherein the semiconductor device is formed on a layer surface. 23. The method according to claim 13, wherein the new insulating film is a high dielectric constant film.

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