JP2004356333A - Laminated electronic component and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated electronic component wherein cracks and delamination can be prevented in an interface between a capacity section which consists of alternately laminated ceramic layers and internal conductors and develops an electrostatic capacity, and a non-capacity section which is formed around the capacity section and includes internal conductors in less number than in the capacity section or includes no internal conductor at all in the lamination direction; and also to provide its manufacturing method. <P>SOLUTION: In a rectangular parallelepiped electronic component body 1 which is formed by alternately laminating ceramic layers 5 and internal conductors 7, a portion 17 having a conductor space factor lower than that of a central part 15 is formed in a peripheral region 13 other than the connection terminals 11 of the internal conductors 7 with the external electrode 3. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０１１８】
表１の結果から、外部電極との接続端以外の周辺領域に、この内部導体の中央部よりも導体占有率の低い部分を設けた試料Ｎｏ．２〜１０では、クラックおよびデラミネーションの発生率が、焼成後および耐熱衝撃試験後（２２５℃）で、それぞれ０個／５０００個以下、０個／５００個以下であった。また、２８０℃においても５個／５００個以下であった。また、積層セラミックコンデンサの内部導体の周縁領域の内部応力は−５０ＭＰａ（−は圧縮方向を表す）以上であった。また、静電容量は４．７μＦ以上、静電容量のばらつきは１．５％以下であった。
【０１１９】
特に、導体占有率の低い部分を内部導体の角部に設けた試料Ｎｏ．２〜４、７〜９では、クラックおよびデラミネーションの発生率が、焼成後および耐熱衝撃試験後（２２５℃）で、それぞれ０個／５０００個以下、０個／５００個以下であった。また、２８０℃においても２個／５００個以下であった。また、積層セラミックコンデンサの内部導体の周縁領域の内部応力は−２０ＭＰａ（−は圧縮方向を表す）以上、静電容量は４．７μＦ以上、静電容量のばらつきは１．３％以下となりさらに改善できた。
【０１２０】
特に、静電容量のばらつきについては、上記した製法２の逐次積層により作製した試料が小さかった。また、内部導体の導体占有率の低い部分を作製する方法として、セラミックパターンを導体パターンの周縁領域に乗り上げて作製した試料の方が、スクリーン印刷を用いて直接作製した試料よりもクラックやデラミネーションの発生割合が低かった。
【０１２１】
一方、外部電極との接続端以外の周辺領域に、この内部導体の中央部よりも導体占有率の低い部分を設けなかった試料Ｎｏ．１では、静電容量は４．７５μＦと高かったものの、クラックおよびデラミネーションの発生率が、焼成後で２０個／５０００個、耐熱衝撃試験後（２２５℃）で２０個／５００個、また、２８０℃においても５０個／５００個であった。また、積層セラミックコンデンサの内部導体の周縁領域の内部応力は−３００ＭＰａ（−は圧縮方向を表す）であった。静電容量は４．７５μＦと高かったが、静電容量のばらつきが２％と大きかった。
【０１２２】
【発明の効果】
以上詳述したとおり、本発明によれば、セラミック層を薄層化して積層数を増加させた場合においても、内部導体の外部電極との接続端以外の周縁領域に、この内部導体の中央部よりも導体占有率の低い部分を設けることにより、内部導体の周縁領域においては、この内部導体の金属膜内にセラミック層が入り込み、このためセラミック層と内部導体とが積層方向に強固に密着されるとともに、内部導体中に入り込むセラミック層のために内部導体の周縁領域では中央部から端部にかけて内部導体の熱膨張係数を漸次その周縁のセラミック層に近づけた状態に形成できる。つまり、この界面部分の熱膨張係数はセラミック層と内部導体の熱膨張係数の中間の値となる。
【０１２３】
こうしてセラミック層と内部導体とが交互に積層され静電容量を発現する容量部と、この容量部の周囲に形成され内部導体数が容量部よりも少ないか若しくは積層方向に全く介在しない非容量部との界面部分において、積層によって累積したセラミック層と内部導体との熱膨張係数差に起因する歪みを緩和できることから界面部分におけるクラックやデラミネーションを抑制することができる。
【図面の簡単な説明】
【図１】本発明の積層型電子部品の概略断面図である。
【図２】本発明の電子部品本体の内部の平面図である。
【図３】本発明の積層型電子部品を一括積層にて製造するための工程図である。
【図４】セラミックグリーンシート上の導体パターン周囲に形成された本発明のセラミックパターンを示す概略平面図である。
【図５】導体パターンに隣接して形成されたセラミックパターンの断面図である。
【図６】本発明の、導体パターンを形成した後にセラミックパターンを形成し、逐次積層を行い、積層型電子部品を製造するための工程図である。
【図７】図６の積層型電子部品の製法において、キャリアフィルムのついたセラミックグリーンシートを用い、重ね合わせ後に剥離する工程を具備する工程図である。
【符号の説明】
１ 電子部品本体
３ 外部電極
５ セラミック層
７ 内部導体
１１ 接続端
１３、３４、５６ 周縁領域
１５ 中央部
１７ 導体占有率の低い部分
１８ 非接続端
１９、３７ 角部
３１、５３ａ、５３ｂ セラミックグリーンシート
３３、５５ 導体パターン
３５、５９ セラミックパターン
３９、６３ 母体積層体
４０、６０ 乗り上げ部分[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer electronic component and a method of manufacturing the same, and more particularly, to a multilayer electronic component such as a wiring board and a multilayer ceramic capacitor in which ceramic layers and internal conductors are formed in a thin multilayer.
[0002]
[Prior art]
A multilayer ceramic capacitor, which is one of the representative products of multilayer electronic components, has a structure in which ceramic layers exhibiting dielectric properties and internal conductors are alternately laminated, and each internal conductor is sandwiched between ceramic layers. Has become.
[0003]
In recent years, there has been an increasing demand for a multilayer ceramic capacitor to have a small size and a high capacity. For this reason, ceramic layers and internal conductors have been made thinner and the number of stacked layers has been increased.
[0004]
By the way, the ceramic layer and the internal conductor constituting the multilayer ceramic capacitor as described above have a difference in the sintering temperature and the coefficient of thermal expansion. ₃ When the sintering temperature is about 1300 ° C., the ceramic layer and the internal conductor are different materials, and it is difficult to obtain an adhesive strength. There is a problem that cracks and delamination (delamination) occur between the inner conductor and the inner conductor. It is known that such cracks and delaminations are further increased in a mounting process such as soldering and in a process subjected to thermal stress such as a thermal shock test.
[0005]
In order to solve such a problem, for example, according to Patent Literature 1 below, by adding unfired ceramic powder (common material) of substantially the same quality as the ceramic layer to the conductor paste, the thermal expansion coefficient of the internal conductor is reduced. The generation of these defects is prevented by bringing the adjacent ceramic layers close to the ceramic layers and connecting the adjacent ceramic layers with the common material via the internal conductors.
[0006]
[Patent Document 1]
JP-A-10-172855
[0007]
[Problems to be solved by the invention]
However, according to the method disclosed in Patent Document 1, even if cracks and delamination on the laminated surface of the ceramic layer and the internal conductor can be suppressed, when the number of laminated ceramic layers is increased by further reducing the number of laminated ceramic layers, Since the number of boundaries between the internal conductor and the internal conductor increases, the ceramic layer and the internal conductor are alternately laminated to exhibit a capacitance, and the number of internal conductors formed around the capacitance portion is smaller than the capacitance. At the interface with the non-capacitance part that is less or not interposed in the stacking direction at all, the strain caused by the difference in the thermal expansion coefficient between the ceramic layer and the internal conductor accumulated by the stacking becomes large. It was still difficult to suppress delamination.
[0008]
In addition, in order to increase the effective area of the internal conductor in such a high-capacity multilayer ceramic capacitor, a denser metal film is required over the entire formation surface, and thus the effective area of the internal conductor will be increased. The cracks and delaminations at the above-mentioned interface due to the thermal stress caused by the difference in thermal expansion coefficient between the ceramic layer and the internal conductor became more remarkable.
[0009]
Therefore, according to the present invention, even when the number of laminations is increased by reducing the thickness of the dielectric layer, the capacitance layer in which the ceramic layers and the internal conductors are alternately laminated to exhibit the capacitance, and the periphery of the capacitance portion are provided. It is an object of the present invention to provide a multilayer electronic component capable of suppressing the occurrence of cracks and delaminations at an interface with a non-capacitance portion in which the number of formed internal conductors is smaller than the capacitance portion or not interposed at all in the stacking direction, and a method for producing the same. I do.
[0010]
[Means for Solving the Problems]
A laminated electronic component according to the present invention includes: a rectangular parallelepiped electronic component body formed by alternately laminating a substantially rectangular ceramic layer and an internal conductor; and an internal conductor provided at an end of the electronic component body. And a pair of external electrodes alternately connected to each other, wherein a peripheral area other than a connection end of the internal conductor with the external electrode has a conductor occupancy ratio higher than that of the central portion of the internal conductor. A low portion is provided. Hereinafter, the conductor occupancy in the present invention refers to the effective area of the internal conductor. For example, when the ceramic layer partially enters the internal conductor and penetrates in the thickness direction, the effective area (conductor occupancy) of the internal conductor is reduced.
[0011]
According to such a configuration, even when the number of stacked ceramic layers is increased by reducing the thickness of the ceramic layer, the conductor occupies the peripheral region other than the connection end of the internal conductor with the external electrode more than the central portion of the internal conductor. Providing the low-rate portion makes it easier for the ceramic layer to enter the metal film of the internal conductor in the peripheral region of the internal conductor. For this reason, the ceramic layer and the internal conductor are firmly adhered to each other in the laminating direction, and the thermal expansion coefficient of the internal conductor is gradually increased from the center to the end in the peripheral region of the internal conductor by the ceramic layer penetrating into the internal conductor. It can be formed close to the ceramic layer. In other words, the coefficient of thermal expansion at the interface has an intermediate value between the coefficients of thermal expansion of the ceramic layer and the internal conductor.
[0012]
For this reason, a capacitance portion in which ceramic layers and internal conductors are alternately laminated to exhibit capacitance, and a non-capacitance formed around the capacitance portion and having fewer internal conductors than the capacitance portion or not intervening in the lamination direction at all. In the interface portion with the portion, the strain caused by the difference in the thermal expansion coefficient between the ceramic layer and the internal conductor accumulated by the lamination can be reduced, so that cracks and delamination at the interface portion can be suppressed.
[0013]
In the above-mentioned multilayer electronic component, it is preferable that a portion having a low conductor occupancy of the internal conductor is provided at a corner of a non-connection end with the external electrode. In a multilayer electronic component in which a metal film serving as an internal conductor is formed almost on the entire surface of a ceramic layer, such as a multilayer ceramic capacitor, and such ceramic layers are stacked in multiple layers, the ceramic layer accumulated by the stacking and the internal Since the thermal stress due to the difference in thermal expansion coefficient from the conductor is concentrated at the peripheral region of the inner conductor, particularly at the corners, and becomes the largest, the ceramic layer enters the film surface of the inner conductor as described above and occupies the conductor. By forming a portion having a low rate, cracks and delamination can be more effectively suppressed.
[0014]
In the multilayer electronic component, it is desirable that the conductor occupancy of the portion where the conductor occupancy of the internal conductor is low is 70% or less. That is, by setting the conductor occupancy of the portion where the conductor occupancy of the internal conductor is low to 70% or less, the thermal expansion coefficient of the internal conductor can be made close to that of the ceramic layer.
[0015]
In the multilayer electronic component, it is preferable that the conductor occupancy of the internal conductor other than the portion having a low conductor occupancy is 75% or more. The laminated electronic component of the present invention can improve the peripheral portion of the internal conductor as described above to suppress defects such as cracks and delamination occurring in the component. It is preferable to increase the conductor occupancy of the portion so that the original function of the multilayer electronic component can be maximized.
[0016]
In the multilayer electronic component, when the width of the non-connection end of the internal conductor with the external electrode is W0 and the maximum width along the non-connection end of a portion where the conductor occupancy of the internal conductor is low is W1, It is desirable to satisfy the relationship of /W0≧0.01. The effect of the present invention can be obtained if the width of the portion where the conductor occupancy of the internal conductor is low is at least equal to or greater than the ratio of the width of the non-connection end where the portion is formed.
[0017]
In the multilayer electronic component, when the area of the ceramic layer is A0 and the area occupied by the internal conductor with respect to the ceramic layer is A1, it is desirable that the relationship of A1 / A0 ≧ 0.6 is satisfied. If the structure in which the conductor occupancy of the internal conductor is low is provided in the peripheral region of the internal conductor as in the present invention, even if the area occupied by the internal conductor with respect to the ceramic layer is high as described above, Cracks and delamination occurring in the multilayer electronic component can be further suppressed.
[0018]
In the multilayer electronic component, the thickness of the internal conductor is desirably 2 μm or less. In the present invention, when the thickness of the internal conductor is reduced as described above, the ceramic layer can enter the peripheral region of the internal conductor, and delamination can be suppressed by reducing the step due to the thickness.
[0019]
In the multilayer electronic component, the thickness of the ceramic layer is desirably 4 μm or less. According to the present invention, cracks and delamination can be suppressed even in a multilayer electronic component in which the thickness of the ceramic layer is small and a step due to the thickness of the internal conductor appears remarkably.
[0020]
In the multilayer electronic component, when the thickness of the ceramic layer is t1 and the thickness of the internal conductor is t2, it is desirable that the relationship of t2 / t1 ≧ 0.2 is satisfied. That is, the structure of the internal conductor of the present invention can be suitably used even when the thickness of the internal conductor is larger than the thickness of the ceramic layer.
[0021]
In the multilayer electronic component, the number of layers is desirably 100 or more. In the present invention, even when the number of layers of the ceramic layer and the internal conductor is increased and the strain due to the difference in thermal expansion coefficient between the ceramic layer and the internal conductor accumulated by the lamination is increased, the thermal Stress can be reduced, and thereby cracks and delamination can be suppressed.
[0022]
The method for manufacturing a multilayer electronic component according to the present invention is directed to a base laminate including a substantially rectangular conductor pattern and a ceramic pattern at least around the conductor pattern inside a green laminate in which a plurality of ceramic green sheets are laminated. Forming a body, forming the electronic component body molded body by cutting the mother laminate at substantially the center in the long side direction of the conductor pattern, and firing the electronic component body molded body. A method for manufacturing a laminated electronic component, wherein the ceramic pattern is formed so as to ride on a peripheral region of the conductor pattern.
[0023]
According to such a manufacturing method, in the peripheral region of the conductor pattern in the mother laminate after pressing, the ceramic pattern formed beforehand on the conductor pattern after pressing is pressed, and the ceramic pattern is formed in the conductor pattern after pressing. By entering, the adhesion between the conductor pattern and the ceramic green sheet in this region can be easily increased. Further, according to such a manufacturing method, a region in which the conductor pattern and the ceramic pattern are mixed can be easily formed, and as described above, after firing, the intermediate value of the coefficient of thermal expansion between the internal conductor and the ceramic layer can be reduced. It can easily form the part having.
[0024]
In the method of manufacturing a multilayer electronic component, it is preferable that a portion of the ceramic pattern riding on the conductor pattern is a corner of the conductor pattern. As described above, the strain due to the difference in thermal expansion coefficient between the ceramic layer and the internal conductor accumulated by the lamination is concentrated particularly at the corners of the peripheral region of the internal conductor, and since it is the largest portion, before firing, It is more preferable to form a riding portion of the ceramic pattern at a corner of the conductor pattern.
[0025]
In the manufacturing method of the laminated electronic component, when the width of the conductor pattern in the cutting direction is WG0 and the maximum width of the ceramic pattern at the corner of the conductor pattern in the same direction is WG1, WG1 / WG0 ≧ 0.01. It is desirable to satisfy the following relationship.
[0026]
By setting the proportion of the portion of the ceramic pattern riding on the conductor pattern to be at least the proportion described above, the adhesion between the conductor pattern and the ceramic green sheet can be further increased, and, after firing, the coefficient of thermal expansion In the peripheral region of the inner conductor, a portion having a thermal expansion coefficient intermediate between the inner conductor and the ceramic layer can be formed more, thereby reducing distortion caused by the difference in thermal expansion coefficient between the ceramic layer and the inner conductor accumulated by lamination. it can.
[0027]
In the manufacturing method of the multilayer electronic component, when the area of the ceramic green sheet in the molded body of the electronic component body is AG0 and the area of the conductor pattern formed on the ceramic green sheet is AG1, AG1 / AG0 ≧ 0.6 It is desirable to satisfy the following relationship. According to the present invention, as described above, even when the area occupied by the conductor pattern is increased, a multilayer electronic component capable of suppressing cracks and delamination can be easily formed.
[0028]
In the above-mentioned multilayer electronic component, the matrix laminate includes: (a) printing a conductive paste on a main surface of the ceramic green sheet to form a plurality of conductive patterns at predetermined intervals; and (b) forming the ceramic green sheet. Forming a ceramic pattern by printing a ceramic paste on at least a peripheral portion of the conductor pattern on the main surface of (c); and (c) laminating a ceramic green sheet on which the conductor pattern and the ceramic pattern are formed. It is desirable to be manufactured through. That is, since the manufacturing method of the present invention is a manufacturing method in which a conductor pattern is formed on a ceramic green sheet and then a ceramic pattern is formed on the periphery of the conductor pattern, a step due to the thickness of the conductor pattern on the ceramic green sheet is formed. The ceramic pattern can be easily formed, and by laminating such ceramic green sheets at a time, the ceramic pattern riding on the peripheral region of the conductor pattern can enter the surface of the conductor pattern, and at the same time, the ceramic pattern can be climbed. The portion can be easily made flush with the thickness of the conductor pattern.
[0029]
In the method of manufacturing a multilayer electronic component, the mother laminate is formed by (a) placing a ceramic green sheet on a support; and (b) printing a conductor paste on a main surface of the ceramic green sheet to form a conductor. Forming a plurality of patterns at predetermined intervals; (c) forming a ceramic pattern by printing a ceramic paste on at least a peripheral portion of the conductor pattern on the main surface of the ceramic green sheet; and (d). It may be manufactured by including a step of superposing another ceramic green sheet on the upper surface of the ceramic green sheet on which the conductor pattern is formed, and a step of repeating steps (e), (b) to (d). desirable.
[0030]
Further, in the present invention, by adopting the sequential laminating method as described above, the ceramic pattern riding on the peripheral area of the conductor pattern can be more easily inserted into the plane of the conductor pattern and made even.
[0031]
In the above-mentioned multilayer electronic component, it is preferable that the conductor pattern has a substantially rectangular shape in plan view, particularly a substantially rectangular shape, and that the ceramic paste be printed in a long side direction of the conductor pattern. By setting the printing direction to the long-side direction of the conductor pattern in this way, particularly, it is possible to print on the corners of the conductor pattern with high dimensional accuracy and high thickness accuracy.
[0032]
In the multilayer electronic component, it is desirable that the ends of the conductor pattern and the ceramic pattern are in contact with each other on an inclined surface. By forming an inclined surface in the peripheral region of the conductor pattern and forming the ceramic pattern on the inclined surface in a state where the ceramic pattern rides on the surface, the step due to the thickness of the conductor pattern can be gradually changed and at the same time, the ceramic in the plane of the conductor pattern can be formed. The degree of entry of the pattern can also be gradually changed.
[0033]
In the multilayer electronic component, the thickness of the ceramic pattern riding on the peripheral region of the conductor pattern is smaller than the thickness of the conductor pattern, and the conductor pattern and the ceramic pattern have substantially the same thickness except for the ceramic pattern riding on the ceramic pattern. Is desirable. By setting the thickness of the conductor pattern and the ceramic pattern in such a relationship, it is possible to eliminate a step due to the thickness of the conductor pattern on the ceramic green sheet and to reduce an excessive step due to the ceramic pattern riding on the conductor pattern. It is possible to suppress excessive deformation at the time of laminating press.
[0034]
In the method for manufacturing a laminated electronic component, it is preferable that the thickness of the conductor pattern is 2 μm or less, the thickness of the ceramic green sheet is 5 μm or less, and the number of layers is 200 or more.
[0035]
BEST MODE FOR CARRYING OUT THE INVENTION
The multilayer electronic component of the present invention is applied to, for example, a multilayer ceramic capacitor as shown in FIG.
[0036]
FIG. 1 is a schematic sectional view of the multilayer electronic component of the present invention. This multilayer ceramic capacitor is formed by forming external electrodes 3 on both ends of an electronic component body 1. The electronic component body 1 is formed by alternately stacking ceramic layers 5 and internal conductors 7, and a cover ceramic layer 9 made of the same material as the ceramic layer 5 is formed on both surfaces in the stacking direction.
[0037]
The ceramic layer 5 and the cover ceramic layer 9 are made of a sheet-shaped ceramic sintered body, for example, BaTiO ₃ Of ceramic green sheets mainly composed of
[0038]
Further, the thickness of the ceramic layer 5 is preferably 4 μm or less, particularly 3 μm or less, and more preferably 2 μm or less in terms of increasing the capacitance of the multilayer ceramic capacitor. In particular, it is preferable that the thickness be 0.7 μm or more from the viewpoint of securing the insulating property of the ceramic layer 5.
[0039]
The internal conductor 7 is made of a metal film obtained by sintering a conductive paste film. As the conductive paste, for example, a base metal such as Ni, Co, or Cu is used. The inner conductor 7 is a substantially rectangular metal film having a base metal as a main component, and particularly a substantially rectangular metal film. The odd-numbered first, third, fifth,... , One end of which is exposed at one end face of the multilayer body 1, and the second, fourth, sixth,... It is exposed on the other end face of the component body 1. Note that the external electrode 3 and the internal conductor 7 need not necessarily be made of the same material.
[0040]
In the present invention, the ratio of the thickness t1 of the ceramic layer 5 to the thickness t2 of the internal conductor 7, t2 / t1, is 0.5 or more, particularly 0.6 or more. In particular, it can be suitably used in a case where accumulation of steps due to the internal conductor 7 becomes remarkable with 300 layers or more, further, 400 layers or more.
[0041]
FIG. 2 is a plan view of the inside of the electronic component body 1. In the internal conductor 7 constituting the multilayer electronic component of the present invention, a portion 17 having a lower conductor occupancy than the central portion 15 of the internal conductor 7 is provided in a peripheral region 13 other than the connection end 11 with the external electrode 3. This is very important. That is, the present invention is characterized in that there are more discontinuous portions on the peripheral region 13 side than the central portion 15 in the plane of the internal conductor 7.
[0042]
In the peripheral region 13 in the plane of the internal conductor 7, a portion 17 having a lower conductor occupancy of the internal conductor 7 than the side margin portion side is provided at a corner portion 19 at a non-connection end with the external electrode 3. Is desirable.
[0043]
The conductor occupancy of the portion 17 having a low conductor occupancy of the internal conductor 7 is set to 70 because the difference in thermal expansion coefficient between the ceramic layer 5 and the ceramic layer 5 is changed stepwise while securing the capacitance of the internal conductor 7. %, Particularly preferably 60% or less, more preferably 50% or less, and the lower limit is more preferably 30% or more, particularly preferably 40% or more. Further, in the present invention, it is preferable that the change in the conductor occupancy between the internal conductor 7 and the ceramic layer 5 is formed gradually.
[0044]
On the other hand, the conductor occupancy of the central portion 15 which is the internal conductor 7 other than the portion 17 having a low conductor occupancy is 75% or more, particularly 80% or more, as the internal conductor 7 for expressing the capacitance. More desirable.
[0045]
In the internal conductor 7 according to the present invention, the width of the non-connection end 21 of the internal conductor 7 with the external electrode 3 is set to W0, and the portion 17 of the internal conductor 7 where the conductor occupancy is low along the non-connection end 21. The ratio W1 / W0 when W1 (W1a + W1b = W1 in FIG. 2) is set to be large, while maintaining the effective area of the internal conductor 7 high, the adhesion force between the inner conductor 7 and the ceramic layer 5 in the peripheral region of the internal conductor 7 is improved. From the viewpoint of increasing the value, it is more preferably 0.01 or more, particularly 0.05 or more, and further preferably 0.08 or more.
[0046]
Further, in the present invention, in terms of increasing the effective area of the internal conductor 7, the internal conductor 7 has a ratio when the area of the ceramic layer 5 is A0 and the area occupied by the internal conductor 7 with respect to the ceramic layer 5 is A1. A1 / A0 is more preferably 0.6 or more, particularly 0.65 or more, and even more preferably 0.7 or more.
[0047]
In addition, as in the present invention, the ceramic layer 5 is inserted into the peripheral region of the internal conductor 7 to form the portion 17 having a low conductor occupancy, and the thickness of the internal conductor 7 is 2 μm or less because the step is suppressed. In particular, it is desirable that the thickness be 1 μm or less.
[0048]
An example in which the manufacturing method of the multilayer electronic component of the present invention is applied to a multilayer ceramic capacitor will be described in detail.
[0049]
(Production method 1)
FIG. 3 is a process chart for manufacturing the multilayer electronic component of the present invention by batch lamination.
[0050]
As shown in FIG. 3A, first, a ceramic green sheet 31 constituting a multilayer ceramic capacitor is formed by applying ceramic slurry on a carrier film 32.
[0051]
The thickness of the ceramic green sheet 31 is desirably 5 μm or less, particularly 4 μm or less, and more desirably 3 μm or less, because the size and the capacity of the multilayer ceramic capacitor are increased.
[0052]
Next, as shown in FIG. 3B, a plurality of conductor patterns 33 are formed at predetermined intervals by printing a conductor paste on one main surface of the ceramic green sheet 31.
[0053]
Further, the thickness of the conductor pattern 33 is 2 μm or less, particularly 1.5 μm, for ease of riding when printing the ceramic paste in the manufacturing method of the present invention, and for reducing the step due to the thickness. It is more desirable that: Thereafter, as shown in FIG. 3C, a ceramic paste is printed around the conductor pattern 33 by printing a ceramic paste so as to substantially eliminate a step due to the thickness of the conductor pattern 33.
[0054]
FIG. 4 is a schematic plan view showing the ceramic pattern 35 of the present invention formed around the conductor pattern 33 on the ceramic green sheet 31.
[0055]
As shown in FIG. 4, the conductor pattern 33 has a substantially rectangular shape in plan view, particularly a substantially rectangular shape, and is preferably arranged in tandem in the long side direction.
[0056]
FIG. 5 is a sectional view of the ceramic pattern 35 formed adjacent to the conductor pattern 33. The peripheral region 34 of the conductor pattern 33 preferably has an inclined surface because it is easy to insert the ceramic pattern into the peripheral region 34 of the conductor pattern 33.
[0057]
As shown in FIG. 4, the ceramic pattern 35 is printed in the direction of the long side of the substantially rectangular conductive pattern 33 (arrow in FIG. 4). In this case, it is important that the ceramic pattern 35 is formed so as to ride on the peripheral region 34 of the conductor pattern 33, and in particular, the portion of the ceramic pattern 35 that rides on the conductor pattern 33 is a corner of the conductor pattern 33. It is desirably 37.
[0058]
Further, in the present invention, the thickness of the ceramic pattern 35 running on the peripheral region 34 of the conductor pattern 33 is smaller than the thickness of the conductor pattern 33 and the thickness of the It is preferable that the conductor pattern 33 and the ceramic pattern 35 have substantially the same thickness except for the ceramic pattern 35.
[0059]
Furthermore, the ratio WG1 / when the width of the conductor pattern 33 in the cutting direction is WG0, and the maximum width of the overlapping ceramic pattern 35 at the corner 37 of the conductor pattern 33 in the same direction is WG1 (WG1a + WG1b = WG1 in the figure). WG0 is preferably 0.01 or more, particularly 0.05 or more, and more preferably 0.1 or more.
[0060]
Furthermore, the area of the ceramic green sheet in the electronic component body molded body is AG0 (within the broken line frame), and the area of the conductor pattern formed on the ceramic green sheet is AG1 (the conductor pattern within the broken line frame, including the riding portion). In this case, the ratio AG1 / AG0 is preferably 0.6 or more, more preferably 0.65 or more, and even more preferably 0.7 or more.
[0061]
Next, as shown in FIGS. 3 (d-1) and 3 (d-2), a plurality of ceramic green sheets 31 on which the conductor patterns 33 and the ceramic patterns 35 are formed are laminated, and the conductor patterns 33 and A predetermined number of ceramic green sheets 31 to which the ceramic pattern 35 is not applied are stacked and heated under pressure to form a base laminate 39.
[0062]
In the base laminate 39, a plurality of substantially rectangular conductive patterns 33 of the present invention are interposed between the ceramic green sheets 31 in isolation, and partially overlap the conductive pattern 33, and the rest is adjacent to the ceramic pattern. 35 are formed.
[0063]
The conductor pattern 33 is formed such that the end margin side 33a is alternately shifted for each layer in the laminating direction. In other words, the conductor patterns 33 that are opposed to each other with the ceramic green sheet 31 interposed therebetween have different end margin sides 33a, and the end margin sides 33a are alternately shifted when viewed in the laminating direction. FIG. 3D-1 is a sectional view of the side margin side 33b, and FIG. 3D-2 is a sectional view of the end margin side 33a.
[0064]
The present invention can be suitably used when the number of stacked ceramic green sheets 31 on which the conductor patterns 33 and the ceramic patterns 35 are formed is 100 or more layers, which greatly affects the degassing property.
[0065]
Referring to FIG. 4, the multilayer electronic component of the present invention is formed in such a manner that a ceramic pattern 35 rides on a peripheral region 34 of a conductor pattern 33 formed on a ceramic green sheet 31, and a plurality of such ceramic green sheets 31 are provided. It is formed by laminating and heating and pressing. In this case, when heating and pressing are performed due to an extra riding portion 40 in the height direction of the ceramic pattern 35 on the peripheral region 34 of the conductor pattern 35. Then, a local pressure is applied to the riding portion 40 of the ceramic pattern 35, and accordingly, the peripheral region 34 of the conductor pattern 33 on the lower layer side of the riding portion 40 of the ceramic pattern 35 is perpendicular to the pressing direction. extend. For this reason, the conductor pattern 33 that has been made thinner is sheared and becomes discontinuous, and the ceramic pattern 35 enters the plane of the conductor pattern 33 that is thus discontinued. As described above, in the present invention, the ceramic pattern 35 is formed on the conductor pattern 33 so as to ride on the conductor pattern 33. Since this is an area that has little effect as deformation to 33, deformation of the mother laminate 39 after lamination and the molded electronic component body after cutting can be suppressed, and delamination and cracking of the laminated electronic component after firing can be prevented. .
[0066]
At this time, it goes without saying that the lamination conditions are selected such that the ceramic green sheet 31, the conductor pattern 35 and the ceramic pattern 35 are firmly adhered.
[0067]
In the present invention, in addition to the method of forming the riding portion 40 of the ceramic pattern 35 on a part of the conductor pattern 33 as in the method described above, a resist process is performed on a screen when the conductor pattern 33 and the ceramic pattern 35 are printed. Alternatively, a method of forming a printed film in which the ceramic pattern 35 enters the plane of the conductor pattern 33 can be adopted.
[0068]
Next, the base laminate 39 is cut at a predetermined position to produce a laminate molded body. End margin sides 33a of the conductor pattern 33 are alternately exposed one by one in the laminating direction on opposing side surfaces of the laminated molded body.
[0069]
Thereafter, firing is performed under a predetermined atmosphere under a temperature condition to form a multilayer ceramic capacitor.
[0070]
The method for producing the above-described ceramic laminate will be described with reference to specific examples.
[0071]
First, a ceramic slurry is applied on a carrier film 32, and a ceramic green sheet 31 is formed by a slip casting method. As the carrier film 32 used here, for example, a carrier film 32 made of a PET film is used. In order to improve the releasability of the thinned ceramic green sheet 31, the surface thereof is coated with a silicon resin and a release treatment is performed. It is desirable to have been.
[0072]
As the ceramic slurry, for example, a mixture of ceramic powder, a binder made of polyvinyl butyral resin, and toluene and ethyl alcohol as a solvent for dissolving the binder is preferably used. As another binder, an acrylic resin may be used in terms of dispersibility with ceramic powder or a solvent, strength of the ceramic green sheet 31, and binder removal.
[0073]
As the ceramic material, specifically, BaTiO ₃ -MnO-MgO-Y ₂ O ₃ And the like can be used because such ceramic powders have reduction resistance. Further, glass powder may be added thereto.
[0074]
The conductive paste is composed of a metal particle, an organic solvent composed of a mixture of an aliphatic hydrocarbon and a higher alcohol, an organic binder composed of ethyl cellulose soluble in the organic solvent, and a poorly soluble organic solvent. And an organic binder made of an epoxy resin.
[0075]
As the metal particles contained in the conductor paste, base metal particles having an average particle size of 0.05 to 0.5 μm are used. Base metals include Ni, Co, Cu, Ag, and Pd, and Ni is preferable because the firing temperature of the metal matches the firing temperature of a general insulator and the cost is low.
[0076]
As the binder composition of the ceramic paste, both a ceramic paste having the same composition or a different composition as the conductor paste on which the conductor pattern 3 is formed can be applied. The ceramic paste desirably has the same composition as the conductor paste, because the rate of volatilization of the binder from the surface of the ceramic paste is matched.
[0077]
As the ceramic powder composition used for the ceramic slurry, both the powder composition of the ceramic green sheet 31 and the ceramic paste having a different powder composition can be applied. However, the adhesion between the ceramic green sheet 31 and the ceramic pattern 35 is increased, and the firing shrinkage is increased. It is desirable that the ceramic paste has the same powder composition as the ceramic slurry forming the ceramic green sheet 31 because the ratios are matched.
[0078]
The ceramic pattern 35 in the present invention is desirably formed of a ceramic powder having an average particle diameter smaller than that of the ceramic powder constituting the ceramic green sheet 31. Thereby, the shrinkage rate of the ceramic layer 5 around the conductor pattern 33 during sintering can be increased, the compressive stress on the internal conductor 7 can be increased, the internal stress can be increased, and cracks and delamination can be further suppressed.
[0079]
(Production method 2)
FIG. 6 is a process diagram of the present invention for forming a ceramic pattern after forming a conductor pattern and sequentially performing lamination to produce a laminated electronic component.
[0080]
Next, another manufacturing method of the present invention will be described in detail with reference to FIG. The ceramic slurry, the conductive paste, the ceramic paste, and the ceramic green sheets 31, the conductive patterns 33, and the ceramic patterns 35 formed from these compositions are the same as those used in the above-described manufacturing method 1.
[0081]
As shown in FIG. 6A, first, a plurality of ceramic green sheets 53a are placed on a support body 51, and an electrodeless portion 54a having a predetermined thickness serving as a margin portion of the multilayer ceramic capacitor is formed.
[0082]
Next, as shown in FIG. 6B, a plurality of rectangular conductor patterns 55 are formed at equal intervals by printing a conductor paste on one main surface of the uppermost layer of the stacked ceramic green sheets 53a. I do.
[0083]
Thereafter, as shown in FIG. 6 (c), the conductor pattern 15 rides around the peripheral area 56 of the conductor pattern 55 as shown in FIG. 2 of the manufacturing method 1 as shown in FIG. The ceramic pattern 59 is formed by printing a ceramic paste so as to substantially eliminate a step due to the thickness of the conductor pattern 55.
[0084]
Also in this case, it is important that the ceramic pattern 59 is formed so as to ride on the peripheral region 56 of the conductor pattern 55 arranged in cascade in the printing direction of the ceramic paste, similarly to the manufacturing method 1.
[0085]
Here, the conductor pattern 55 and the ceramic pattern 59 formed on the ceramic green sheet 53a have the same shape, arrangement, and thickness as those of the conductor pattern 33, the ceramic pattern 35, and the riding portion 60 manufactured in the above-described manufacturing method 1. Formed. That is, the pattern arrangement is as shown in FIG.
[0086]
In this manufacturing method, similarly to the manufacturing method 1, the screen for printing the conductor pattern 55 and the ceramic pattern 59 is subjected to resist processing, and the printed film in which the ceramic pattern 59 enters the plane of the conductor pattern 55 is formed. It goes without saying that a forming method can be adopted.
[0087]
Next, as shown in FIG. 6 (d), on the upper surface side of the ceramic green sheet 53a on which the conductor pattern 55 and the ceramic pattern 59 are formed as described above, the conductor pattern 55 and the ceramic pattern 59 are covered. Another ceramic green sheet 53b is overlapped, and the conductor pattern 55 and the ceramic pattern 59 are brought into close contact with the ceramic green sheet 53b.
[0088]
Thereafter, the steps of FIGS. 6B to 6D are repeated so as to obtain a desired number of laminations, and finally, the layers are formed again in the step of FIG. 6A using the ceramic green sheets 53a. The non-electrode portion 54b having the same thickness is formed to form the base laminate 63.
[0089]
Note that, as described above, the present invention is a method in which, after the ceramic green sheets 53a or 53b are overlaid, the conductor pattern 55 and the ceramic pattern 59 are sequentially formed on the upper surface thereof by screen printing. In this regard, compared to the method of preparing a plurality of ceramic green sheets 53a and 53b in which the conductor patterns 55 and the ceramic patterns 59 are formed in advance and laminating them at once, displacement during lamination is less likely to be included. Since the positional accuracy of the conductor pattern 55 and the ceramic pattern 59 in 63 is only required to be the positional deviation of only the printing accuracy, the laminating accuracy is improved, the capacitance variation can be reduced, and the side margin and the end margin can be reduced. Can respond to miniaturization of the multilayer ceramic capacitor.
[0090]
FIG. 7 is a process diagram including a step of using a ceramic green sheet provided with a carrier film in the method of manufacturing the laminated electronic component of FIG.
[0091]
In the manufacturing method of the present invention, as shown in FIG. 7, the ceramic green sheets 53a and 53b are preferably formed by laminating the carrier film 32. In this case, the ceramic green sheets 53a with the carrier film 32 are provided. , 53b, the carrier film 32 is peeled off. According to this method, since the ceramic green sheets 53a and 53b are supported by the carrier film 32, even when the ceramic green sheets 53a and 53b are overlaid on the upper surface side of the conductor pattern 55 or the ceramic pattern 59 and then pressurized and heated, the ceramic green sheets 53a and 53b are adhered. Elongation and deformation of the green sheets 53a and 53b can also be suppressed. Further, in this method, since the ceramic green sheets 53a and 53b are not adsorbed, defects of the ceramic green sheets 53a and 53b can be prevented.
[0092]
FIG. 6E1 is a cross-sectional view on the side margin side of the mother laminate 63, and FIG. 6E2 is a cross-sectional view on the end margin side. As shown in FIG. 6, after cutting the base laminate 63 at a dotted line portion C to form a laminate, the laminate is fired under a predetermined atmosphere and temperature conditions to form an external conductor. Forming a multilayer ceramic capacitor having a ceramic layer and an internal electrode layer.
[0093]
Further, according to this manufacturing method, cracks and delamination occurring in the electronic component main body and the fired electronic component main body 1 can be suppressed, and the formation accuracy of the conductor pattern 55 and the ceramic pattern 59 is improved. Variations in capacitance can be reduced, and even if the number of layers is increased, the accuracy of forming the conductive pattern 55 is not affected.
[0094]
【Example】
(Production method 1)
A multilayer ceramic capacitor, which is one of multilayer electronic components, was manufactured as follows.
[0095]
The ceramic green sheet is made of BaTiO ₃ A ceramic slurry is prepared by adding an organic resin component such as polyvinyl butyral to a ceramic composition containing as a main component and mixing for a predetermined time, and then, the ceramic slurry is formed into a belt-like shape made of polyester using a die coater method. A film was formed on a carrier film. The thickness was adjusted to 2.5 μm.
[0096]
The conductive paste was prepared by adding ceramic powder as a co-material to Ni powder having a particle diameter of 0.2 μm, adding a vehicle such as ethyl cellulose to the conductor composition, and kneading the mixture.
[0097]
As for the ceramic paste, a part of the ceramic slurry for the ceramic green sheet is formed of BaTiO. ₃ Was ground to a particle size smaller than that of the ceramic powder of the ceramic green sheet and reduced to 0.1 μm, and was prepared in the same manner as a conductive paste.
[0098]
Next, the above-mentioned conductor paste was printed in a conductor pattern on the main surface of the obtained ceramic green sheet using a screen printing device and dried. The thickness of the conductor pattern was 1.4 μm. The conductor pattern was adjusted so that the ratio of the occupied area of the internal conductor to the ceramic layer after firing was 0.7.
[0099]
Further, a ceramic paste was printed on the periphery including the peripheral region of the conductor pattern formed on the ceramic green sheet by screen printing and dried, thereby producing a ceramic green sheet on which the ceramic pattern was applied together with the conductor pattern. The slope of the ceramic pattern was adjusted by the viscosity of the ceramic paste and the slope of the resist. The thickness of the ceramic pattern was formed to be substantially the same as the thickness of the conductor pattern.
[0100]
At this time, the riding portion of the ceramic pattern was formed at a location shown in Table 1.
[0101]
The change in the conductor occupancy in the portion where the conductor occupancy was low was adjusted by the area of the ceramic pattern overlapping the conductor pattern and the amount of ceramic paste applied.
[0102]
Next, 260 ceramic green sheets were laminated, and 10 ceramic green sheets each serving as a cover ceramic layer were laminated on the upper and lower layers to form a temporary laminated molded body. Is subjected to a laminating press at a temperature of 100 ° C. and a pressure of 20 MPa, and a ceramic green sheet coated with a conductor pattern and ceramic green sheets made of the same material as the upper and lower ceramic green sheets are laminated and brought into close contact to obtain a base laminate. Was.
[0103]
(Production method 2)
Next, a sample was prepared using the sequential laminating method which is the above-mentioned manufacturing method 2. A plurality of the obtained ceramic green sheets are placed on a support, and a conductor pattern having the shape of the present invention is printed on the main surface of the support using a screen printing device. A ceramic pattern was formed around the area including the region. In this case, the ceramic paste was printed in the long side direction of the rectangular conductor pattern formed in a tandem arrangement. The thickness of the conductor pattern was 1.4 μm, as in Production Method 1. Also in this case, the slope of the ceramic pattern was adjusted by the viscosity of the ceramic paste and the slope of the resist. The thickness of the ceramic pattern was formed to be substantially the same as the thickness of the conductor pattern.
[0104]
Next, the ceramic green sheet is again superimposed on the upper surface of the ceramic green sheet on which the ceramic pattern of the present invention is applied together with the conductor pattern, and this is repeated by the same number of layers as in the production method 1 to exhibit the capacitance. A layer was formed. Furthermore, ten ceramic green sheets each having no conductor pattern and no ceramic pattern formed thereon were laminated, and the first press was performed to form a base laminate. In each of the above steps, a method was used in which the carrier film was peeled off every time the ceramic green sheets were stacked.
[0105]
In the present embodiment, as a method of forming a portion having a low conductor occupancy in the peripheral region of the internal conductor, separately from the above-described method, when forming a conductor pattern and a ceramic pattern, the above-described pattern is used. A sample in which both patterns were formed directly using such a printing screen was also prepared.
[0106]
Next, the matrix laminate produced by Production Method 1 and Production Method 2 was cut into a lattice to obtain a molded electronic component body. One end of the conductor pattern was alternately exposed on both end surfaces of the electronic component body.
[0107]
Next, the electronic component main body was heated to 250 ° C. in the air or 500 ° C. in an oxygen / nitrogen atmosphere of 0.1 Pa to perform a binder removal treatment.
[0108]
Furthermore, 10% of the molded body of the electronic component after de-buying. ^-7 Baking at 1250 ° C. for 2 hours in an oxygen / nitrogen atmosphere of Pa, ^-2 A reoxidation treatment was performed at 900 ° C. for 4 hours in an oxygen-nitrogen atmosphere of Pa to obtain an electronic component body. Next, a Cu paste was baked at 900 ° C. on the end surface of the electronic component body, and further, Ni / Sn plating was performed to form external electrodes connected to internal conductors.
[0109]
The external dimensions of the multilayer ceramic capacitor thus obtained were 0.8 mm in width and 1.6 mm in length. There were no steps due to the internal conductor, and the internal conductor 7 was flat without being curved.
[0110]
At this time, the thickness of the ceramic layer constituting the laminated ceramic capacitor after firing was 2 μm, and the thickness of the internal conductor was 1.2 μm. The number of layers is shown in Table 1.
[0111]
(Evaluation)
The conductor occupancy of the internal conductor was determined by polishing the fired sample in parallel with the internal conductor, selecting five arbitrary 0.1 mm square locations from the center of the internal conductor, and photographing them by microscopic observation. It was determined as a value per unit area. On the other hand, as for the portion where the conductor occupancy is low in the peripheral region of the inner conductor, all the portions formed on the inner conductor were photographed by the same method as described above, and the value per unit area was obtained. Table 1 shows the conductor occupancy of the portion where the conductor occupancy is low. The center was 0.95.
[0112]
Table 1 also shows W1 / W0, which is the ratio of the width of the portion where the conductor occupancy is low. This was also determined by measuring a fired sample polished in parallel with the internal conductor.
[0113]
Next, with respect to the multilayer ceramic capacitor obtained after firing, 5000 samples were observed with a 40 × binocular microscope, and the presence or absence of cracks on the end face of the multilayer ceramic capacitor was evaluated. Further, each of 500 samples was polished from the end face and side face of the multilayer ceramic capacitor, and the presence or absence of cracks and delamination around the inner conductor including the peripheral area was evaluated.
[0114]
Further, using the multilayer ceramic capacitor obtained as described above, a thermal shock resistance test was performed based on JIS standards. For each of the 500 samples, the temperature (ΔT = 225 ° C.) and the number of samples in which cracks occurred at the temperature (ΔT = 280 ° C.) were evaluated.
[0115]
In addition, the internal stress in the peripheral region of the internal conductor of the multilayer ceramic capacitor was measured by a parallel tilt method based on the X-ray diffraction method with respect to the stacking direction of the multilayer ceramic capacitor.
[0116]
The capacitance was measured using an LCR meter (HP-4284A) under the conditions of a frequency of 1 kHz and a voltage of 0.5V. In this case, the variation in capacitance (CV value: standard deviation × 100 / average value) was also obtained. Table 1 summarizes the above results.
[0117]
[Table 1]

[0118]
From the results in Table 1, it is found that the sample No. in which a portion having a lower conductor occupancy than the central portion of the internal conductor was provided in the peripheral region other than the connection end with the external electrode. In Nos. 2 to 10, cracks and delaminations were 0/5000 or less and 0/500 or less after firing and after the thermal shock test (225 ° C.), respectively. Also, at 280 ° C., the number was 5/500 or less. Further, the internal stress of the peripheral region of the internal conductor of the multilayer ceramic capacitor was -50 MPa (-represents a compression direction) or more. The capacitance was 4.7 μF or more, and the variation in capacitance was 1.5% or less.
[0119]
In particular, the sample No. in which the portion having a low conductor occupancy was provided at the corner of the internal conductor. In Nos. 2 to 4 and 7 to 9, cracks and delaminations were 0/5000 or less and 0/500 or less after firing and after the thermal shock test (225 ° C), respectively. Also, at 280 ° C., the ratio was 2/500 or less. Further, the internal stress of the peripheral region of the internal conductor of the multilayer ceramic capacitor is -20 MPa (-indicates a compression direction) or more, the capacitance is 4.7 μF or more, and the variation of the capacitance is 1.3% or less, which is further improved. did it.
[0120]
In particular, regarding the variation in the capacitance, the sample manufactured by the sequential lamination of the above-mentioned manufacturing method 2 was small. In addition, as a method of manufacturing a portion where the conductor occupancy of the internal conductor is low, a sample formed by riding a ceramic pattern on the peripheral region of the conductor pattern is more likely to crack or delamination than a sample directly formed by screen printing. The rate of occurrence was low.
[0121]
On the other hand, in the sample No. in which a portion having a lower conductor occupancy than the central portion of the internal conductor was not provided in a peripheral region other than the connection end with the external electrode. In Example 1, although the capacitance was as high as 4.75 μF, the rate of occurrence of cracks and delaminations was 20/5000 after firing, 20/500 after the thermal shock test (225 ° C.), and Even at 280 ° C., the number was 50/500. The internal stress in the peripheral region of the internal conductor of the multilayer ceramic capacitor was -300 MPa (-represents a compression direction). The capacitance was as high as 4.75 μF, but the variation in capacitance was as large as 2%.
[0122]
【The invention's effect】
As described in detail above, according to the present invention, even when the number of laminations is increased by making the ceramic layer thinner, the central portion of the inner conductor is provided in the peripheral region other than the connection end of the inner conductor with the external electrode. By providing a portion having a lower conductor occupancy ratio, in the peripheral region of the inner conductor, the ceramic layer enters the metal film of the inner conductor, so that the ceramic layer and the inner conductor are firmly adhered in the laminating direction. In addition, due to the ceramic layer entering the internal conductor, the thermal expansion coefficient of the internal conductor in the peripheral region of the internal conductor from the central portion to the end portion can be formed so as to gradually approach the peripheral ceramic layer. In other words, the coefficient of thermal expansion at the interface has an intermediate value between the coefficients of thermal expansion of the ceramic layer and the internal conductor.
[0123]
In this way, a capacitance portion in which the ceramic layers and the internal conductors are alternately laminated to exhibit capacitance, and a non-capacitance portion formed around the capacitance portion and having fewer internal conductors than the capacitance portion or not interposed at all in the laminating direction. At the interface with the ceramic layer and the internal conductor, the strain caused by the difference in thermal expansion coefficient between the ceramic layer and the internal conductor can be reduced, so that cracks and delamination at the interface can be suppressed.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view of a multilayer electronic component of the present invention.
FIG. 2 is a plan view of the inside of the electronic component body of the present invention.
FIG. 3 is a process chart for manufacturing the multilayer electronic component of the present invention by batch lamination.
FIG. 4 is a schematic plan view showing a ceramic pattern of the present invention formed around a conductor pattern on a ceramic green sheet.
FIG. 5 is a cross-sectional view of a ceramic pattern formed adjacent to a conductor pattern.
FIG. 6 is a process diagram of the present invention for forming a ceramic pattern after forming a conductor pattern, sequentially performing lamination, and manufacturing a laminated electronic component.
FIG. 7 is a process diagram including a step of peeling after superposition using a ceramic green sheet with a carrier film in the method of manufacturing the laminated electronic component of FIG.
[Explanation of symbols]
1 Electronic component body
3 External electrodes
5 ceramic layer
7 inner conductor
11 Connection end
13, 34, 56 Peripheral area
15 Central part
17 Low conductor occupancy
18 Non-connection end
19, 37 corner
31, 53a, 53b Ceramic green sheet
33, 55 conductor pattern
35, 59 Ceramic pattern
39, 63 Matrix laminate
40, 60 riding part

Claims (22)

A rectangular parallelepiped electronic component body formed by alternately laminating a substantially rectangular ceramic layer and an internal conductor, and a pair of external electrodes provided at ends of the electronic component body and connected to the internal conductor alternately A multilayer electronic component comprising: a portion having a lower conductor occupancy than a central portion of the internal conductor in a peripheral region other than a connection end of the internal conductor with the external electrode. Laminated electronic components. The multilayer electronic component according to claim 1, wherein a portion of the internal conductor having a low conductor occupancy is provided at a corner of a non-connection end with the external electrode. 3. The multilayer electronic component according to claim 1, wherein the conductor occupancy of a portion where the conductor occupancy of the internal conductor is low is 70% or less. The multilayer electronic component according to any one of claims 1 to 3, wherein the conductor occupancy of the internal conductor other than the portion having a low conductor occupancy is 75% or more. When the width of the non-connection end of the internal conductor with the external electrode is W0, and the maximum width of the portion of the internal conductor having a low conductor occupancy along the non-connection end is W1, W1 / W0 ≧ 0.01 The multilayer electronic component according to claim 1, wherein the relationship satisfies a relationship. The relationship of A1 / A0 ≧ 0.6 is satisfied when the area of the ceramic layer is A0 and the area occupied by the internal conductor with respect to the ceramic layer is A1. Laminated electronic components. 7. The multilayer electronic component according to claim 1, wherein the thickness of the internal conductor is 2 μm or less. 8. The multilayer electronic component according to claim 1, wherein the thickness of the ceramic layer is 4 μm or less. 9. The multilayer electronic component according to claim 1, wherein a relationship of t2 / t1 ≧ 0.2 is satisfied when a thickness of the ceramic layer is t1 and a thickness of the internal conductor is t2. . 10. The multilayer electronic component according to claim 1, wherein the number of layers is 100 or more. Forming a matrix laminate including a substantially rectangular conductor pattern and a ceramic pattern at least around the conductor pattern inside a green laminate in which a plurality of ceramic green sheets are laminated; and A step of forming the electronic component body molded body by cutting the substantially at the center in the long side direction of the conductor pattern, and a step of firing the electronic component body molded body, a method of manufacturing a laminated electronic component, A method of manufacturing a laminated electronic component, wherein the ceramic pattern is formed so as to ride on a peripheral region of the conductor pattern. The method of manufacturing a multilayer electronic component according to claim 11, wherein a portion of the ceramic pattern that rides on the conductor pattern is a corner of the conductor pattern. When the width of the conductor pattern in the cutting direction is WG0, and the maximum width of the overlapping ceramic patterns at the corners of the conductor pattern in the same direction is WG1, the relationship of WG1 / WG0 ≧ 0.01 is satisfied. The method for producing a multilayer electronic component according to claim 11. When the area of the ceramic green sheet in the molded body of the electronic component is AG0, and the area of the conductor pattern formed on the ceramic green sheet is AG1, the relationship of AG1 / AG0 ≧ 0.6 is satisfied. A method for producing a multilayer electronic component according to any one of claims 11 to 13. The mother laminate is
(A) printing a conductive paste on the main surface of the ceramic green sheet to form a plurality of conductive patterns at predetermined intervals;
(B) printing a ceramic paste on at least a peripheral portion of the conductor pattern on a main surface of the ceramic green sheet to form a ceramic pattern;
15. The method of manufacturing a multilayer electronic component according to claim 11, wherein the method is performed through: (c) laminating a ceramic green sheet on which the conductor pattern and the ceramic pattern are formed. The mother laminate is
(A) placing a ceramic green sheet on a support;
(B) printing a conductive paste on the main surface of the ceramic green sheet to form a plurality of conductive patterns at predetermined intervals;
(C) printing a ceramic paste on at least a peripheral portion of the conductor pattern on a main surface of the ceramic green sheet to form a ceramic pattern;
(D) superposing another ceramic green sheet on the upper surface of the ceramic green sheet on which the conductor pattern is formed;
16. The method for manufacturing a multilayer electronic component according to claim 11, wherein the manufacturing method includes: (e) repeating steps (b) to (d). The multilayer electronic component according to any one of claims 11 to 16, wherein the conductor pattern has a substantially rectangular shape in plan view, and the ceramic paste is printed toward a long side direction of the conductor pattern. Recipe. The method according to any one of claims 11 to 17, wherein ends of the conductive pattern and the ceramic pattern are in contact with each other on an inclined surface. 12. The ceramic pattern, wherein the thickness of the ceramic pattern running on the peripheral region of the conductive pattern is smaller than the thickness of the conductive pattern, and the conductive pattern and the ceramic pattern have substantially the same thickness except for the raised ceramic pattern. 19. The method for producing a multilayer electronic component according to any one of the above-mentioned items. 20. The method for manufacturing a multilayer electronic component according to claim 11, wherein the thickness of the conductive pattern is 2 μm or less. 21. The method for manufacturing a multilayer electronic component according to claim 11, wherein the thickness of the ceramic green sheet is 5 μm or less. 22. The method for manufacturing a multilayer electronic component according to claim 11, wherein the number of layers is 100 or more.

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