JP2004341312A - Display device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device, which makes driving transistor operate in their saturation areas for high-gradation display and low-gradation display and reduces variance in threshold voltage among the transistors, as a display device equipped with semiconductor elements having polycrystalline silicon films and amorphous silicon films, and its driving method. <P>SOLUTION: The current capability of a driving transistor is increased so that the transistor operates in a wide saturation area. Consequently, even when the high-gradation display is performed, Vgs is prevented from rising and the saturation area as an operating range can be held wide. Further, each pixel is equipped with a circuit (turn-^on period control circuit) which controls a turn-on period so that its turn-on period can individually be varied. Conventionally, (1) Vgs is preferably made large before to reduce the influence of variance in the threshold voltage as to electric characteristics of a transistor and Vgs is preferably small for widening the operation range of a saturation area as to characteristics of a light emitting element. Further, (2) reduction of the influence of variance in the threshold voltage and widening of operation range in the saturation area for prevention against a decrease in luminance due to deterioration of a light emitting element are in a trade-off relation. Such the problem as above can be solved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display device having a self-luminous light emitting element and a driving method thereof. In particular, it relates to a pixel configuration of a display device.
[0002]
[Prior art]
In recent years, research and development of a display device using a light-emitting element (self-light-emitting element) has been promoted. Such display devices are widely used as display screens of mobile phones and monitors of personal computers, taking advantage of advantages such as high image quality, thinness, and light weight. In particular, such a display device has characteristics such as fast response speed, low voltage, and low power consumption driving suitable for displaying a moving image, and thus has a wide range of applications, including a new generation of mobile phones and personal digital assistants (PDAs). Applications are expected.
[0003]
The light-emitting element is also called an organic light-emitting diode (Organic Light Emitting Diode: OLED), in which an anode, a cathode, and a layer containing an organic compound (hereinafter, referred to as an organic compound layer) are interposed between the anode and the cathode. It has a structure. There is a fixed relationship between the amount of current flowing through the light emitting element and the luminance of the light emitting element, and the light emitting element emits light at a luminance corresponding to the amount of current flowing through the organic compound layer.
[0004]
As a driving method for displaying a multi-tone image on a display device using a light-emitting element, there are an analog driving method (analog gradation method) and a digital driving method (digital gradation method). The difference between the two methods lies in the method of controlling the light emitting element in each state of light emission and non-light emission of the light emitting element.
[0005]
The analog driving method is a method of obtaining a gray scale by continuously controlling the magnitude of a current flowing through a light emitting element. The digital driving method is a method in which the light-emitting element is driven only in two states: an ON state (a state where luminance is almost 100%) and an OFF state (a state where luminance is almost 0%).
[0006]
However, since the digital driving method can display only two gradations as it is, a driving method of displaying a multi-gradation image in combination with the time gradation method or the area gradation method has been proposed. For example, in the time gray scale display, one frame is divided into several sub-frames, each light emitting time is weighted, and gray scale display is performed by selection. The area gray scale method is a method in which a sub-pixel is provided in a pixel, a light emitting area thereof is weighted, and a gray scale display is performed by selection.
[0007]
When a signal is input to a pixel, a voltage input method is often used. The voltage input method is a method in which a voltage is input to a gate electrode of a driving element as a video signal to be input to a pixel, and the luminance of the light-emitting element is controlled using the driving element.
[0008]
For a driving method of the display device, a multi-gradation display method, and the like as described above, refer to Non-Patent Document 1.
[0009]
[Non-patent document 1]
“Material Technology and Device Fabrication in Organic EL Display”, Technical Information Association, January 2002, p. 179-196
[0010]
[Problems to be solved by the invention]
In the case of using the above-described voltage input method, if the current characteristics of a transistor for driving (supplying current) a light-emitting element (hereinafter, referred to as a driving transistor) vary, the luminance of the light-emitting element also varies. Was. In particular, when performing low gray scale display in the case of the analog gray scale method, the influence of the variation in the electrical characteristics of the driving transistor becomes large. This is because the current characteristics of the transistor are determined depending on (Vgs-Vth). Therefore, when low-gradation display is performed, Vgs is small, and the influence of Vth is relatively large. Vth of a transistor is a threshold voltage, and greatly varies depending on a film formation condition, a manufacturing process such as a film thickness, and the like. In particular, in a semiconductor device having a polycrystalline silicon film that has undergone a crystallization step, Vth varies due to crystal grain boundaries and orientation as one factor.
[0011]
Specific description is made using the transistor and the light-emitting element illustrated in FIG. FIG. 11B illustrates the Ids-Vds characteristics of the light-emitting element and the transistor in the case of performing low-gradation display, and the intersection is the operating point. As shown in FIG. 11B, when low-gradation display is performed, a current value (Ids) supplied from the transistor to the light-emitting element is small, Vgs is small, and the transistor is relatively susceptible to a variation in Vth. You can see that it's gone. As a result, in a display device having a transistor and a light-emitting element, luminance unevenness occurs, which causes quality deterioration. In order to reduce the influence of the threshold voltage as described above, it is conceivable that the transistor is designed to have a smaller channel size W / L and operate with an increased Vgs.
[0012]
On the other hand, even when the voltage-current characteristics of the light-emitting element change, the transistor is operated in a saturation region so that a constant current flows to the light-emitting element. As shown in FIG. 11C, the saturation region is in the range of Vds> (Vgs−Vth), and the source / drain current does not change even when the source-drain voltage of the transistor changes. Therefore, a constant current can always be supplied to the light emitting element.
[0013]
However, when performing high gradation display, the saturation region of the transistor has become narrow. FIG. 11C shows transistor characteristics and Ids-Vds characteristics of light-emitting element characteristics in high gradation display. FIG. 11C shows that as the light-emitting element deteriorates, the light-emitting element characteristics shift to a lower voltage side and Vds decreases. As a result, it has been considered that a saturation region, which is an operation range of the transistor, is narrowed, and the transistor operates in a linear region.
[0014]
In order to solve such a problem in the high gradation display, it is preferable to widen the operation range of the saturation region. For example, it is conceivable to increase the voltage between α and β shown in FIG. As a result, even if the light emitting element deteriorates, it can operate in the saturation region. However, in this case, since the voltage is increased, power consumption is increased. As another method, it is conceivable that the channel size W / L of the transistor is designed to be larger and Vgs is reduced.
[0015]
In view of these, from the viewpoint of the electrical characteristics of the transistor, it is preferable to design the channel size W / L to be small and increase Vgs in order to reduce the influence of the variation in the threshold voltage. In order to extend the operation range of the saturation region, it was preferable to design the channel size W / L to be large so that Vgs becomes small. As described above, there is a trade-off between reducing the influence of the variation in the threshold voltage and widening the range of operation in the saturation region in order to prevent a decrease in luminance due to deterioration of the light emitting element.
[0016]
Therefore, the present invention relates to a display device including a semiconductor element having a polycrystalline silicon film or an amorphous silicon film, wherein a driving transistor operates in a saturation region in high gradation display and low gradation display, and It is an object to provide a display device in which the variation in threshold voltage of the display device is reduced and a driving method thereof.
[0017]
[Means for Solving the Problems]
In view of the above problems, the present invention is characterized by increasing the current capability of a driving transistor so as to operate in a wide saturation region. As a result, even when high gradation display is performed, it is possible to prevent Vgs from increasing and to maintain a wide saturation region as an operation range. Further, in the present invention, each pixel is provided with a circuit (lighting period control circuit) for controlling the lighting period so as to individually change the lighting period of each pixel. Then, when performing low gradation display, control is performed so as to shorten the lighting period of the light emitting element. Note that the lighting period control circuit may be provided at a position where the light emitting element can be controlled to emit no light in a predetermined period. As a result, when low gradation display is performed, operation can be performed with Vgs increased. Since Vgs is large as described above, the influence of variations in threshold voltage can be reduced.
[0018]
That is, according to the present invention, the saturation region can be widened even when performing high gradation display, and the effect of Vth variation can be reduced even when performing low gradation display. In order to realize this, the W / L of the transistor is designed, and the lighting period of each pixel is changed according to the size of the gradation.
[0019]
As a specific design policy, W / L may be increased. For example, in order to operate in a saturation region, the length of L is preferably several hundreds to several tens μm. That is, the current capability of the driving transistor may be increased. As another method, the crystallinity of the driving transistor may be increased. For example, the crystallinity may be increased using a continuous wave laser.
[0020]
In the present invention, a plurality of driving transistors may be arranged in parallel. Note that the transistor may be formed using a polycrystalline silicon thin film transistor, an amorphous silicon thin film transistor, or another transistor. That is, the present invention is not limited to a transistor structure.
[0021]
In the case where an amorphous silicon thin film transistor is used, it is preferable that the amorphous silicon thin film transistor be entirely formed using an n-channel thin film transistor. In the case of using only one polarity as described above, a bootstrap circuit or the like may be used, and the description of Japanese Patent Application No. 2002-327498 may be referred to.
[0022]
As described above, the W / L of the driving transistor can be designed so as to secure a wide saturation region according to the present invention. As a result, a wide saturation region serving as an operation region of the transistor can be ensured, and the lighting period control circuit is less likely to be affected by variations even in low gradation display, so that accurate display can be performed.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below with reference to the drawings. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and description thereof will not be repeated.
[0024]
(Embodiment 1)
In this embodiment mode, a pixel configuration which performs a driving method in which an analog signal, particularly, an analog voltage is input as a video signal will be described.
[0025]
FIG. 1 shows an active matrix pixel configuration including a signal line 10, a scanning line 11, and a light emitting element 12. An n-channel switching transistor Tr14 connected to the signal line 10 and the scanning line 11 is provided. When the transistor Tr14 is selected by the scanning line 11 and turned on, an analog voltage is input from the signal line 10 so as to have a desired luminance. Is done. Based on the input analog voltage, charges are accumulated in the capacitor Cs16 arranged between the Tr 14 and the power supply line 15. Cs16 plays a role of holding the gate-source voltage of the p-channel type driving transistor Tr15. Thereafter, when Tr17 is turned on, the light emitting element 12 is supplied with a current based on the charge stored in Cs16, and emits light at a predetermined luminance.
[0026]
At this time, in the present invention, the W / L of Tr17 is set so as to secure a wide saturation region. Therefore, even when the light-emitting element is affected by deterioration over time, the driving transistor can be prevented from operating in the linear region.
[0027]
When low gradation display is performed in such a pixel configuration, the lighting period of the light emitting element is controlled to be short by the lighting period control circuit 18. That is, the lighting period control circuit 18 has a circuit configuration for controlling a lighting period (also referred to as a light emitting period) of the light emitting element. That is, the lighting period control circuit discharges the electric charge held in Cs16 at a predetermined timing, prevents current from flowing to Tr17, and controls the lighting period of the light emitting element. Note that the lighting period control circuit may be arranged at any position where the lighting period of the light emitting element can be controlled, and is connected to both ends of Cs16 in FIG. Further, in the present invention, since the lighting period control circuit is provided for each pixel, the charge held in Cs16 can be discharged for each pixel. Note that a period during which the light-emitting element does not emit light by the lighting period control circuit is referred to as an erasing operation period.
[0028]
Therefore, when designing the W / L of the transistor so as to secure a wider saturation region, an erasing operation period is provided to control the current supply to the light emitting element, thereby preventing | Vgs | of the Tr 17 from decreasing. , Low gradation display can be performed.
[0029]
Therefore, even if the W / L of the driving transistor is designed so that a wide saturation region can be ensured, a low gradation display can be performed accurately, and when a high gradation display is performed, a saturation region which is an operation range is wide. Can be secured.
[0030]
In the present invention, the lighting period control circuit may be arranged so as to control the time for supplying a predetermined current to the light emitting element. For example, as shown in FIG. Such an arrangement is also conceivable.
[0031]
In the case where the lighting period control circuit is provided as shown in FIG. 1B, an erasing operation period can be provided regardless of the characteristics of the driving transistor Tr17, particularly, the threshold voltage Vth. That is, even if the characteristics of Tr17 are normally on, in which a current flows when the voltage is set to zero, the lighting period control circuit short-circuits the connection between the light emitting element and Tr17. An operation period can be provided, and low gradation display can be performed.
[0032]
Note that, in the present invention, the case of a p-channel type driving transistor has been described, but an n-channel type transistor may be used. In order to further simplify the manufacturing process, the polarity of the transistor can be all n-channel or p-channel.
[0033]
As described above, according to the present invention, even when the W / L of a transistor is designed so as to secure a wide saturation region, low gradation display can be accurately performed by providing a lighting period control circuit for each pixel. Make it possible. The configuration and polarity of the lighting period control circuit and the transistor included in the pixel, and the pixel configuration and the arrangement of the lighting period control circuit are not limited to those in FIG.
[0034]
(Embodiment 2)
In this embodiment, a specific example of a pixel structure in which a lighting period control circuit is provided at both ends of a capacitor as illustrated in FIG. 1A will be described with reference to FIGS.
[0035]
The pixel illustrated in FIG. 2A includes a switching transistor Tr14 connected to the signal line 10 and the scanning line 11, a capacitor Cs16 connected to the switching transistor Tr14, a switching transistor, and a gate connected to the switching transistor Cs16. It has a driving transistor Tr17 to which an electrode is connected and a light emitting element 12 connected to the driving transistor Tr17. A lighting period control circuit 18 having transistors Tr22 and Tr23 connected in series is provided at both ends of the capacitive element Cs16. The gate electrode of Tr22 is connected to the erasing signal line 20, and the gate electrode of Tr23 is used for erasing. It is connected to the scanning line 21. In this embodiment, Trs 14, 22, and 23 are n-channel transistors, and Tr17 is a p-channel transistor.
[0036]
The operation of such a pixel configuration will be described. When the Tr 14 is selected by the scanning line 11 and turned on, an analog voltage corresponding to each gradation is input from the signal line 10. Electric charges are accumulated in Cs16 based on this analog voltage, and when the driving transistor Tr17 is turned on, a predetermined current is supplied to the light emitting element to emit light.
[0037]
Then, in the case of the low gradation display, the electric charge accumulated in Cs16 is discharged after a predetermined period, and the light emitting element does not emit light. Specifically, control is performed so that both Tr22 and Tr23 are turned on, and a low gradation display is performed. At this time, the analog voltage input from the signal line has a magnitude corresponding to the lighting period.
[0038]
Next, the operation of the Trs 22 and 23 will be described. When the light emitting element is turned off, the erasing scanning line 21 is selected, and the Tr 23 of each pixel connected to the same erasing scanning line is turned on. At this time, an erasing signal is input from the erasing signal line 20. Specifically, a High signal is input to Tr22 included in a pixel displaying low gradation display, and Tr22 is turned on. That is, both Tr22 and Tr23 are turned on, and the electric charge of Cs16 is discharged. As a result, the light emitting element does not emit light, and low gradation display can be performed. That is, only the pixels in which both Tr22 and Tr23 are turned on can be turned off. Therefore, the lighting period can be controlled for each pixel.
[0039]
Actual pixels are arranged in a matrix, and scanning lines are sequentially selected and analog voltages are input. Therefore, the timing at which the erasing scanning line 21 is selected is later than the timing at which the scanning line 11 is selected, and is sequentially selected. The timing at which the erasing scanning line is selected can be set by a practitioner according to the length of the lighting period.
[0040]
FIG. 2B is a timing chart in which the timing for selecting the erasing scanning line is n × T (0 <n <1). As time elapses, the scanning lines of each row are sequentially selected, the Tr 14 is turned on for each column, and an analog voltage is supplied from the signal line 10. Thereafter, charges based on the analog voltage are accumulated in Cs16, and Tr17 is turned on. After that, the light emitting elements 12 start emitting light with luminance according to the respective analog voltages.
[0041]
Then, after n × T, the erasing scanning lines of each row are sequentially selected, and Tr23 is turned on for each column. However, the number of pixels that are actually desired to be erased, that is, for which low gradation display is desired, varies from column to column. Therefore, an erasing signal is input to the Tr 22 via the erasing signal line 20 only for the pixels for which low gradation display is desired. As a specific erasing signal, a High signal is input from the erasing signal line 20, whereby the n-channel Tr 22 is turned on. That is, in synchronization with the timing at which the erasing scanning line 21 is selected, the light emitting element 12 of the pixel to which the erasing signal is input from the erasing signal line 20 becomes non-light emitting, and low gradation display is performed.
[0042]
Next, low gray scale display, the timing of selecting a scanning line and an erasing scanning line, and the like will be described with reference to specific numbers of gradations.
[0043]
For example, in the case of performing 64-gradation display, in one frame period T, a scanning line is selected, and an analog voltage of each gradation is input from a signal line to a pixel. In the low gradation area of the first to eighth gradations, the lighting period is shortened.
[0044]
When the erasing operation is started after (1/8) T, the erasing scanning line is selected after (1/8) T after the scanning line is selected. For example, when displaying two gradations, a video signal corresponding to 2 ÷ (÷) = 16 gradations is input. At this time, since the lighting period is (1/8) T, display of two gradations is actually performed. Similarly, when displaying eight gradations, a video signal corresponding to 8 ÷ (１ ／) = 64 gradations is input. Since the lighting period is (1/8) T, display of eight gradations is actually performed. When displaying nine or more gradations, a video signal of the same gradation is input. At this time, since the lighting period is T, the display is performed with the gradation as it is.
[0045]
The low-gradation display may be appropriately determined by the practitioner. However, when the 64-gradation display is performed as in this example and the erasing operation is started after (1 / N) T, the low-gradation display is performed with a low gradation of 64 / N or less. It is preferable that the key display is performed. Of course, even in the case of displaying 64 / N gradations or more, the display can be performed by shortening the lighting period by the lighting period control circuit. However, for example, when displaying 9 gray levels, it is necessary to input 72 gray levels (9 gray levels × 8), which is not preferable since an analog voltage of 64 gray levels or more is input.
[0046]
That is, it is preferable that the gradation range of the low gradation display be set in consideration of the erasing operation timing (the length of the lighting period) so as not to exceed the maximum gradation determined by the specification of the display device.
[0047]
FIG. 15 shows an example of a top view of a pixel corresponding to the circuit diagram of FIG. Tr17 may be designed to have a large W / L. In order to operate in the saturation region, the length of L is preferably several hundreds to several tens of μm, and the length of W is preferably several μm. Therefore, the semiconductor film is formed in a rectangular shape, and the area of the gate metal is further increased.
[0048]
Even when low gradation display is performed using such a driving transistor Tr17, the lighting period can be shortened by the lighting period control circuit, and accurate gradation display in which the influence of Vth variation is reduced. It can be performed.
[0049]
As described above, the W / L of the transistor can be designed to secure a wide saturation region. As a result, even when Vgs becomes large, low gradation display can be performed by providing the lighting period control circuit. . That is, according to the present invention, it is possible to achieve both the reduction of the influence of the variation in the threshold voltage and the widening of the range of operation in the saturation region in order to prevent a decrease in luminance due to deterioration of the light emitting element.
[0050]
(Embodiment 3)
In this embodiment, an example in which a lighting period control circuit is arranged at both ends of a capacitor as shown in FIG. 1A and the length of a lighting period is further increased, unlike the second embodiment, This will be described with reference to FIG.
[0051]
The transistors included in the lighting period control circuit 18 illustrated in FIG. 3A are Tr22, 23, 24, and 25. The gate electrodes of the Trs 22 and 24 are connected to the first and second erase signal lines 20a and 20b, respectively. The gate electrodes of Trs 23 and 25 are connected to the first and second erasing scanning lines 21a and 21b, respectively. In this embodiment, Trs 22, 23, 24, and 25 are n-channel transistors.
[0052]
In this manner, when there are two scanning lines for erasing and two signal lines for erasing, as shown in FIG. 3B, a case where the lighting period is n × T and a case after m × T can be provided. . That is, the first erase operation starts after n × T, and the second erase operation starts after m × T. That is, there are three types of lighting periods: T, n × T, and m × T.
[0053]
For example, a specific number of gradations will be described. For example, when displaying two gradations, a video signal corresponding to 2 ÷ (÷) = 16 gradations is input. At this time, since the lighting period is (1/8) T, display of two gradations is actually performed. Similarly, when displaying eight gradations, a video signal corresponding to 8 ÷ (１ ／) = 64 gradations is input. Since the lighting period is (1/8) T, display of eight gradations is actually performed. When displaying nine gradations, a video signal corresponding to 9 相当 (１ ／) T = 36 gradations is input. At this time, since the lighting period is (1/4) T, display of 9 gradations is actually performed. Similarly, when displaying 16 gradations, a video signal corresponding to 16 ÷ (1/4) = 64 gradations is input. Since the lighting period is (1/4) T, 16 gray scales are actually displayed. When displaying 17 or more gradations, a video signal of the same gradation is input. At this time, since the lighting period is T, the display is performed with the gradation as it is.
[0054]
According to the present invention, a plurality of erasing operations can be provided according to an erasing scanning line, an erasing signal line, and a transistor connected to each. The practitioner can appropriately set the timing and the number of the erasing operations.
[0055]
Note that there is a concern that the aperture ratio may decrease as the number of wirings and transistors increases. However, a reduction in the aperture ratio can be prevented by designing the layout of the wiring and the transistor and employing a top emission method in which the light-emitting element emits light in a direction opposite to that of the transistor. Note that the top emission method can be applied to any pixel configuration of the present invention.
[0056]
(Embodiment 4)
In this embodiment mode, a pixel configuration in which a lighting period control circuit is provided at both ends of a capacitor as shown in FIG. 1A is shown. A specific example of Tr different from those in Embodiment Modes 2 and 3 is shown in FIG. This will be described with reference to FIG.
[0057]
As shown in FIG. 4, a transistor Tr26 connected to the erasing signal line 20, a transistor Tr22 whose gate electrode is connected to the drain electrode of Tr26, and a transistor Tr22 connected in series with Tr22, and the gate electrode connected to the erasing scanning line 21 , An erasing Cs27 provided between the power supply line 15 and the gate electrode of the Tr23 connected to the power supply line 15. In this embodiment, Trs 22, 23, and 26 are n-channel transistors.
[0058]
The operation of this pixel configuration will be described. First, Tr14 and Tr26 are simultaneously selected by the scanning line 11, and an analog voltage and an erasing signal are input from the signal line 10 and the erasing signal line 20, respectively. At this time, based on the erase signal, electric charges are accumulated in the erase Cs 27, and the Tr 22 is turned on. After a predetermined period has elapsed in this state, when Tr23 is turned on by the erasing scanning line 21, the capacitive element Cs16 is discharged, the light emitting element does not emit light, and low gradation display can be performed.
[0059]
Specifically, a High signal is input from the erasing signal line 21 to the Tr 26 of the pixel performing low-gradation display, and the erasing Cs 27 holds a state where the Tr 22 is turned on. On the other hand, a Low signal is input to the Tr 26 of the pixel performing the high gradation display, and the erasing Cs 27 holds the state where the Tr 22 is turned off. After a predetermined period elapses in this state, the erasing scanning lines are sequentially selected, and when both the Trs 22 and 23 are turned on, the light emitting elements do not emit light. That is, in the present embodiment, the control is performed by selecting the erasing scanning line at the erasing timing.
[0060]
As in the first to third embodiments, an analog voltage corresponding to each gradation is input to the Tr 14 from the signal line 10, a charge corresponding to the analog voltage is accumulated in the capacitor Cs 16, and light is emitted when the Tr 17 is turned on. The element 12 emits light at a desired luminance.
[0061]
With the lighting period control circuit of the present embodiment, there is no need to synchronize the erasing signal from the erasing signal line with the timing at which the erasing scanning line is selected. Can be.
[0062]
(Embodiment 5)
In this embodiment, a pixel configuration in which a lighting period control circuit is provided as illustrated in FIG. 1B will be described with reference to FIGS.
[0063]
FIG. 5 shows a light emitting element 12 provided at an intersection of a signal line 10 and a scanning line 11, a driving transistor 17 connected to the light emitting element 12 via a lighting period control circuit 18, and a signal line 10 And a switching transistor Tr14 connected to the scanning line 11 and a capacitor 16 which holds an analog voltage input through the Tr14 and is provided between the gate electrode of the Tr17 and the power supply line 15. The configuration is shown. The lighting period control circuit 18 includes transistors Tr32 connected to the scanning line 11 and the erasing signal line 20, connected to the transistors Tr32 and Tr17, and connected to the gates of the transistors Tr30 and 31 in parallel with each other. It has an erasing scanning line 21 connected thereto, and an erasing capacitive element Cs17 connected to the Tr 32 and the power supply line 15. In this embodiment, Tr30 and 31 are p-channel transistors, and Tr32 is an n-channel transistor.
[0064]
The operation of such a pixel configuration will be described. Note that an operation in which an analog voltage is input from the signal line and the light emitting element 12 emits light at a predetermined luminance based on the charge held in the Cs 16 is the same as in Embodiments 1 to 4.
[0065]
First, the case of low gradation display will be described. When the scanning line 11 is selected, Tr32 is turned on simultaneously with Tr14. Then, an erasing signal is input from the erasing signal line 20, and the charge is held in the erasing capacitance element Cs27. That is, a High signal is input as an erasing signal, and a charge that turns off Tr31 is accumulated in Cs27. At this time, Tr17 is turned on, and the light emitting element 12 emits light at a predetermined luminance based on the electric charge accumulated in Cs16. Next, in the erasing operation, when the erasing scanning line 21 is sequentially selected and a High signal is input, the p-channel type Tr 31 is turned off, and the light emitting element does not emit light.
[0066]
On the other hand, when performing high-gradation display, the charge that turns on Tr31 is held in Cs27. Therefore, even when the erasing scanning line 21 is selected, a High signal is input, and the Tr 30 is turned off, the light emitting element emits light.
[0067]
By arranging the lighting period control circuit between the light emitting element 12 and the driving transistor Tr17 in this manner, the light emitting element does not emit light accurately even if the characteristics of Tr17 are normally on.
[0068]
In FIG. 5, Tr14 and Tr27 are connected to a common scanning line, but they may be connected to different scanning lines. In this case, as in Embodiment 2, the light emitting element does not emit light when the timing at which the erasing signal line and the erasing scanning line are selected is synchronized.
[0069]
(Embodiment 6)
Although the case of the voltage input method has been described so far, the present invention can be applied to the case of the current input method. The current input method is a method in which a current (also referred to as a signal current) is supplied to a light-emitting element as a video signal to control the luminance of the light-emitting element. In the case of the current input method, multi-gradation is displayed by the value of the signal current flowing to the light emitting element. Therefore, in this embodiment, a case will be described in which the lighting period control circuit is used as a video signal and is applied to a current input type pixel to which an analog current is supplied.
[0070]
FIG. 6 shows an example of a pixel of the current input type, which is provided between a switch Sw41 connected to the signal line 10, a driving transistor Tr17 connected to the Sw41, and a gate electrode of the Tr17 and the power supply line 15. The capacitance element Cs16, the lighting period control circuit 18 provided at both ends of Cs16, Sw42 connected to the light emitting element 12, the gate electrode of Tr17, Cs16, the lighting period control circuit 18, and Sw43 provided between Sw42 Have.
[0071]
In the case of such a current input type pixel, when performing low gradation display, a very small current is input from a signal line. Then, there is a possibility that an accurate current value cannot be supplied due to wiring resistance of a signal line or the like. However, by providing the lighting period control circuit as in the present invention, the lighting period can be controlled by supplying a current larger than a predetermined current value, the writing speed is improved, and accurate low gradation display is performed. It becomes possible.
[0072]
FIG. 7 shows a pixel configuration of a current input method different from that of FIG. The switch Sw41 connected to the signal line 10, the transistor Tr35 connected to Sw41, Tr36 forming a current mirror with Tr35, a common gate electrode of Tr35 and Tr36, Sw44 connected to Sw41, and Tr35. It has a capacitor Cs16 connected to the common gate electrode of Tr36, the power supply line 15, a lighting period control circuit 18 connected to both ends of Cs16, and a light emitting element 12 connected to Tr36.
[0073]
In a pixel configuration having such a current mirror circuit, when low gradation display is performed, there is a concern that the current input through the signal line 10 becomes extremely small as in FIG. However, by providing the lighting period control circuit as in the present invention, a large current value can be supplied even in the case of performing low gradation display.
[0074]
As described above, the lighting period control circuit of the present invention can be applied to any current input type pixel, and the lighting period control circuit may adopt any of the structures of Embodiments 1 to 5.
[0075]
(Embodiment 7)
In this embodiment, an overall structure including pixels to which the lighting period control circuit in FIG. 2 is applied will be described.
[0076]
FIG. 8 includes Sw804 and 805 connected to wirings to which an erase signal and a video signal are input, respectively, and a shift register 800 for controlling on / off of Sw804 and 805. Then, the video signal is input to the signal line 10 via Sw805.
[0077]
An initialization power supply line 808 and an initialization signal line 809 are provided, and Sw806 is provided between the initialization power supply line 808 and Sw804. The selection shift register 802 includes a flip-flop circuit and the like, and has a function of controlling the scanning lines 11 to be sequentially selected. The erase shift register 801 also has a flip-flop circuit and the like, and has a function of controlling the erase scan lines 21 to be sequentially selected. However, an AND circuit 807 to which a pulse width signal is input is provided between the erase shift register 801 and the erase scan line 21.
[0078]
Next, the reason for providing the AND circuit will be described. In the pixel configuration shown in FIG. 2, when the signal for turning on the Tr 22 is input to the erasing signal line 20 when the erasing scanning line 21 is selected, the charge of the capacitive element Cs16 is discharged. That is, if the signal to be erased in the previous row is held as it is in the erasing signal line 20, the charge of Cs16 is discharged, and the erasing signal line 20 is turned off after the erasing scanning line 21 is selected. Even if a signal is input, the charge does not return. Therefore, when an erasing scanning line in a certain row is selected, it is necessary to initialize the potentials of the erasing signal lines in all columns at one end so that the charge of the capacitor Cs16 is not discharged. Therefore, an AND circuit 807 to which a pulse width signal is input is provided. Further, an initialization power supply line 808 and an initialization signal line 809 are provided, and an initialization signal is set to be input before the erasing scanning line 21 is selected.
[0079]
A timing chart of such an operation will be described. FIG. 9 shows that the pixels in the (i + 1) -th row, the first column, the i-th row, the j-th column, the i-th row (j + 1) -th column, and the (i + 1) -row (j + 1) -th column perform low gradation display, that is, the lighting period Here is an example of a case where is shortened. First, the timing at which the i-th row, the (i + 1) -th row, the erase scanning line is selected, and the timing at which the initialization signal line is selected will be described. A pulse width signal is input from the erasing shift register 801 to one terminal of the AND circuit 807. Then, another pulse width signal is input to the other terminal of the AND circuit 807. The AND circuit outputs a High signal only when a High signal is input from both terminals. Therefore, the selection of the erasing scanning line is controlled so that the timing of selecting the initialization signal line and the timing of non-selection of the erasing scanning line are synchronized by the timing of inputting a Low signal as another pulse width signal. . As a result, before the erase scanning line of each row is selected, a High signal is input from the initialization signal line, and a period is provided in which the erase scan line for initializing the potential of the erase signal line is not selected. be able to.
[0080]
In addition, an erasing signal input to each pixel performing low gradation display, the first column, the j-th column, and the (j + 1) -th column will be described. The erase signal is written in order from the erase signal line when erasing the lighting period. Then, a High erasure signal is input before a timing at which an erasure scanning line of a predetermined pixel to be erased is selected. That is, during the erasing operation period, when the erasing scanning line of the (i + 1) th row is selected as the erasing signal line of the first column, the erasing scanning line of the i-th row is selected as the erasing signal line of the jth column. Then, when the erasing signal line in the (j + 1) th column is selected as the erasing signal when the erasing scan line in the i-th row and the (i + 1) -th row is selected, High is input. In synchronization with the selection of the erasing scanning line and the erasing signal from the erasing signal line, the light emitting element does not emit light.
[0081]
As described above, the light emitting element is not emitted in each pixel, and a low gradation display can be performed.
[0082]
(Embodiment 8)
In this embodiment, an entire structure including pixels to which the lighting period control circuit in FIG. 4 is applied will be described.
[0083]
FIG. 10 includes Sw804 and 805 connected to wirings to which an erase signal and a video signal are input, respectively, and a shift register 800 for controlling on / off of Sw804 and 805. Further, it has an erasing shift register 801 for controlling the selection of the erasing scanning line 21 and a selecting shift register 802 for controlling the selection of the scanning line 11. Then, the video signal is input to the signal line 10 via Sw805.
[0084]
In such a pixel configuration, a video signal and an erase signal may be input. Therefore, there is no need to provide switches and other logic circuits, and the configuration of the display device can be simplified.
[0085]
(Embodiment 9)
In this embodiment mode, another effect of providing a lighting period control circuit in each pixel will be described.
[0086]
When the multi-gradation display is performed by using the above-described digital gradation method and applying the time gradation method using subframes obtained by dividing one frame, a problem of a pseudo contour occurs. Therefore, using the lighting period control circuit of the present invention, the order of the sub-frames is changed for each pixel to prevent a false contour. For example, control is performed so that the order of subframes or the time at which a subframe period starts or ends is changed in each row and further in each pixel so that light emission and non-light emission occur randomly in each pixel. As a result, the area of the portion where light emission or non-light emission continues is reduced, and the pseudo contour recognized by the human eye is reduced.
[0087]
Specifically, as shown in FIG. 13, a case where the lighting period control circuit changes the end of the lighting period in the sub-frame between the k-th row and the (k + 1) -th row will be described.
[0088]
FIG. 13A shows a timing chart in which one frame: T is divided into four subframe periods: t1 to t4, and 4-bit, 16-gradation display is performed. Referring to FIG. 13A, the periods t1 to t4 have write operation periods Tw1 to Tw4 in which writing is performed from the signal line, respectively, and the erase operation Te is provided in the periods t1 and t4.
[0089]
FIG. 13B shows the states of the k-th row and the (k + 1) -th row in the case of white display that emits light in 16 gradations, that is, in all subframe periods. In the period t1, the writing Tw1 is performed on the k-th row, and the lighting period Ta1 is set. At this time, in the (k + 1) -th row, the writing Tw1 is similarly performed, and then the erasing is performed by the erasing operation Te, and the lighting period Ta4 is set. In the period t2, the writing Tw2 is performed on the k-th row, and the lighting period Ta2 is set. At this time, in the (k + 1) -th row, the writing Tw2 is similarly performed, and the lighting period Ta2 is set. In the period t3, the writing Tw3 is performed on the k-th row, and the lighting period Ta3 is set. At this time, in the (k + 1) -th row, the writing Tw3 is similarly performed, and the lighting period Ta3 is set. In the period t4, the writing Tw4 is performed on the k-th row, and then the erasing is performed by the erasing operation Te, and the lighting period Ta4 is set. At this time, in the (k + 1) -th row, the writing Tw4 is similarly performed, and the lighting period Ta1 is set.
[0090]
In addition, the order of the lighting periods may be changed in a manner other than the white display. Further, the order of the lighting periods may be similarly changed for other than 16 gradations.
[0091]
Specifically, in the erasing operation period, the erasing scanning lines are sequentially selected. At this time, when an erase signal is input from the erase signal line, no light is emitted. Therefore, the length of the lighting period can be controlled, and as a result, the order of the lighting periods can be changed. In FIG. 13, the lighting time of the lighting period Ta4 can be greatly changed depending on the row.
[0092]
In FIG. 13, two erasing operations are provided. For example, a lighting period control circuit as shown in FIG. 3 may be used. Of course, any lighting period control circuit other than FIG. 3 can be used.
[0093]
FIG. 14A shows a timing chart in which one frame: T is divided into five subframe periods: t1 to t5, and a 32-gradation display is performed. At this time, a second erase operation SE is provided. This is because, when the time gray scale method is used, a multi-gray scale is displayed, that is, the duty ratio becomes lower as the subframe becomes shorter. Therefore, an erasing period SE is provided, the light emitting element is made non-light emitting, a writing operation period can be provided, and a decrease in the duty ratio can be prevented.
[0094]
Referring to FIG. 14A, the periods t1 to t5 have write operation periods Tw1 to Tw5, respectively, in which writing is performed from the signal line, and the first erase operations Te and t4 during the periods t1, t3 and t5. Is provided with a second erase operation SE.
[0095]
FIG. 14B shows the state of the k-th row and the (k + 1) -th row in the case of white display in which light emission is performed in 32 gradations, that is, in all subframe periods. In the period t1, the writing Tw1 is performed on the k-th row, and the lighting period Ta1 is set. At this time, in the (k + 1) -th row, the writing Tw1 is similarly performed, and then the erasing is performed in the first erasing operation Te, and the lighting period Ta3 is set. In the period t2, the writing Tw2 is performed on the k-th row, and the lighting period Ta2 is set. At this time, in the (k + 1) -th row, the writing Tw2 is similarly performed, and the lighting period Ta2 is set. In the period t3, the writing Tw3 is performed on the k-th row, and the lighting period Ta3 is set. At this time, in the (k + 1) -th row, the writing Tw3 is similarly performed, and then the erasing is performed in the first erasing operation Te, and the lighting period Ta5 is set. In the period t4, the writing Tw4 is performed on the k-th row, and then the erasing is performed in the erasing period SE, which is the lighting period Ta4. At this time, in the (k + 1) -th row, the writing Tw4 is similarly performed, and then the erasing is performed in the erasing period SE, and the lighting period becomes the lighting period Ta4. In the period t5, the writing Tw5 is performed on the k-th row, and then the erasing is performed in the first erasing operation Te, which is the lighting period Ta5. At this time, in the (k + 1) -th row, the writing Tw5 is similarly performed, and the lighting period Ta1 is set.
[0096]
In addition to the white display, the order of the lighting periods may be similarly changed. Further, in a display other than 32 gradations, the order of the lighting periods may be similarly changed.
[0097]
Specifically, in the erasing operation period, the erasing scanning lines are sequentially selected. At this time, when an erase signal is input from the erase signal line, no light is emitted. Therefore, the length of the lighting period can be controlled, and as a result, the order of the lighting periods can be changed.
[0098]
In FIG. 14, three first erasing operations are provided. For example, if a lighting period control circuit as shown in FIG. 3 is applied and the number of erasing scanning lines, erasing signal lines, and transistors is increased and used. Good. Further, another lighting period control circuit may be applied.
[0099]
The order in which subframes are exchanged and the number of erase operations are not limited to those shown in FIGS. Further, any of the lighting period control circuits described in Embodiments 1 to 5 may be used.
[0100]
As described above, the pseudo contour can be prevented by changing the order of the lighting periods in each row, that is, by changing the end of the lighting period. Further, the order of the lighting periods may be changed in each row and each column, and further in each pixel. In particular, it is preferable to change the order of the lighting periods in each adjacent pixel to prevent a false contour.
[0101]
(Embodiment 10)
The active matrix substrate manufactured according to the present invention can be applied to various electronic devices. Examples of the electronic device include a portable information terminal (mobile phone, mobile computer, portable game machine, electronic book, or the like), a video camera, a digital camera, a goggle-type display, a display, a navigation system, and the like. FIG. 12 shows specific examples of these electronic devices.
[0102]
FIG. 12A illustrates a display, which includes a housing 4001, an audio output portion 4002, a display portion 4003, and the like. According to the present invention, a display portion 4003 having a light-emitting element can be completed. The display device includes all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.
[0103]
FIG. 12B illustrates a mobile computer, which includes a main body 4101, a stylus 4102, a display portion 4103, operation buttons 4104, an external interface 4105, and the like. According to the present invention, a display portion 4103 having a light-emitting element can be completed.
[0104]
FIG. 12C illustrates a game machine including a main body 4201, a display portion 4202, operation buttons 4203, and the like. According to the present invention, a display portion 4202 having a light-emitting element can be completed. FIG. 12D illustrates a mobile phone, which includes a main body 4301, an audio output portion 4302, an audio input portion 4303, a display portion 4304, operation switches 4305, an antenna 4306, and the like. According to the present invention, a display portion 4304 having a light-emitting element can be completed.
[0105]
FIG. 12E illustrates an electronic book reader including a display portion 4401 and the like. According to the present invention, a display portion 4202 having a light-emitting element can be completed.
[0106]
As described above, the applicable range of the present invention is extremely wide, and the present invention can be used for electronic devices in all fields. In particular, by using a flexible substrate as the insulating substrate of the active matrix substrate, thinness and light weight can be realized.
[0107]
【The invention's effect】
According to the present invention, at least the W / L of the driving transistor can be designed so as to secure a wide saturation region. As a result, a wide saturation region serving as an operation region of the transistor can be ensured, and accurate display can be performed even in low gradation display.
[Brief description of the drawings]
FIG. 1 is a diagram showing a pixel configuration of a display device of the present invention.
FIG. 2 is a diagram showing a pixel configuration of a display device of the present invention.
FIG. 3 is a diagram showing a pixel configuration of a display device of the present invention.
FIG. 4 is a diagram showing a pixel configuration of a display device of the present invention.
FIG. 5 illustrates a pixel configuration of a display device of the present invention.
FIG. 6 illustrates a pixel configuration of a display device of the present invention.
FIG. 7 is a diagram showing a pixel configuration of a display device of the present invention.
FIG. 8 is a diagram showing a display device of the present invention.
FIG. 9 is a diagram showing a timing chart of the display device of the present invention.
FIG. 10 illustrates a display device of the present invention.
FIG. 11 illustrates characteristics of a light-emitting element and a transistor.
FIG. 12 illustrates an electronic device of the invention.
FIG. 13 is a diagram showing a timing chart of a display device of the present invention.
FIG. 14 is a diagram showing a timing chart of a display device of the present invention.
FIG. 15 is a top view illustrating a pixel configuration of a display device of the present invention.

Claims (21)

In a display device including at least a signal line to which an analog signal is input, a scan line, a plurality of transistors, a capacitor, and a light-emitting element,
A first transistor connected to the signal line and the scanning line;
A second transistor having a gate electrode connected to the capacitor element and one electrode connected to the light emitting element;
A circuit for controlling a lighting period of the light emitting element;
A display device comprising: In a display device including at least a signal line to which an analog signal is input, a scan line, a plurality of transistors, a capacitor, and a light-emitting element,
A first transistor connected to the signal line and the scanning line;
A second transistor having a gate electrode connected to the capacitor element and one electrode connected to the light emitting element;
A lighting period control circuit connected to both ends of the capacitive element,
A display device comprising: In claim 2,
The lighting period control circuit has first and second erasing transistors,
A gate electrode of the first erasing transistor is connected to an erasing signal line;
A display device, wherein a gate electrode of the second erase transistor is connected to an erase scan line. In claim 2,
The lighting period control circuit has first to fourth erasing transistors,
A gate electrode of the first erasing transistor is connected to a first erasing signal line;
A gate electrode of the second erasing transistor is connected to a first erasing scanning line;
A gate electrode of the first erasing transistor is connected to a second erasing signal line;
A display device, wherein a gate electrode of the second erase transistor is connected to a second erase scan line. In claim 2,
The lighting period control circuit includes first to third erasing transistors and an erasing capacitor,
A gate electrode of the first erasing transistor is connected to the erasing capacitance element and one electrode of the third transistor;
A gate electrode of the second transistor is connected to an erasing scan line;
The display device, wherein the other electrode of the third transistor is connected to an erasing signal line. In a display device including at least a signal line to which an analog signal is input, a scan line, a plurality of transistors, a capacitor, and a light-emitting element,
A first transistor connected to the signal line and the scanning line;
A second transistor having a gate electrode connected to the capacitor element and one electrode connected to the light emitting element;
A display device, wherein a lighting period control circuit is provided between the second transistor and the light emitting element. In claim 6,
The lighting period control circuit includes third to fifth transistors and an erasing capacitance element,
The third and fourth transistors are connected in parallel, one electrode is connected to the second transistor, and the other electrode is connected to the light emitting element;
A display device, wherein a gate electrode of the fourth transistor is connected to one electrode of the fifth transistor, and the erasing capacitor is provided so as to be input from the fifth transistor. A signal line to which an analog signal is input, a scan line, a transistor, a capacitor,
And a light-emitting element.
A first switch connected to the signal line;
A transistor connected to the switch;
A lighting period control circuit connected to both ends of the capacitive element,
When connected to the gate electrode of a transistor,
The capacitor is connected to a gate electrode of the transistor, and the light emitting element is
A display device, wherein the display device is connected to the transistor through a second switch. In a display device including at least a signal line to which an analog signal is input, a scan line, a plurality of transistors, a capacitor, and a light-emitting element,
A first switch connected to the signal line;
A first transistor connected to the switch;
A second transistor having a gate electrode connected to the gate electrode of the first transistor;
A lighting period control circuit connected to both ends of the capacitive element,
The display device, wherein the capacitor is connected to gate electrodes of the first and second transistors, and the light emitting element is connected to one electrode of the second transistor. The display device according to claim 8, wherein the switch is configured by a transistor. A signal line to which an analog signal is input, a scan line, a plurality of transistors, a capacitor, a light-emitting element, a first transistor connected to the signal line, the scan line, and a capacitor. A display device including a gate electrode connected thereto, a second transistor having one electrode connected to the light-emitting element, and a lighting period control circuit connected to both ends of the capacitor,
The lighting period control circuit has at least a third and a fourth transistor,
A gate electrode of the third transistor is connected to an erasing signal line;
A gate electrode of the fourth transistor is connected to an erasing scanning line;
A first shift register that controls selection of the signal line and the erasing signal line;
A second shift register for controlling selection of the erase scanning line;
A third shift register for controlling selection of the scanning line. 12. The display device according to claim 11, wherein an AND circuit is provided between the erasing scanning line and the second shift register. A signal line to which an analog signal is input, a scan line, a plurality of transistors, a capacitor, a light-emitting element, a first transistor connected to the signal line, the scan line, and a capacitor. A display device including a gate electrode connected thereto, a second transistor having one electrode connected to the light-emitting element, and a lighting period control circuit connected to both ends of the capacitor,
The lighting period control circuit includes third to fifth transistors and an erasing capacitor,
A gate electrode of the third transistor is connected between one electrode of the fifth transistor and one end of the erasing capacitor;
The other electrode of the fifth transistor is connected to an erasing signal line,
A gate electrode of the fourth transistor is connected to an erasing scanning line;
A gate electrode of the fifth transistor is connected to a gate electrode of the first transistor;
A first shift register that controls selection of the signal line and the erasing signal line;
A second shift register for controlling selection of the erase scanning line;
A third shift register for controlling selection of the scanning line. The display device according to any one of claims 1 to 13, wherein at least the second transistor is a thin film transistor including a crystalline semiconductor film. In a method for driving a display device having a light-emitting element that emits light based on an analog signal,
When the analog signal is larger than a predetermined value, control is performed to shorten a lighting period of the light emitting element. A light emitting element that emits light based on an analog signal,
A circuit for controlling a lighting period of the light emitting element, a driving method of a display device,
A driving method of a display device, wherein a circuit for controlling a lighting period of the light emitting element controls the lighting period of the light emitting element to be shorter when the analog signal is larger than a predetermined value. A light-emitting element that emits light based on an analog signal, a capacitor,
A lighting period control circuit connected to both ends of the capacitive element,
The lighting period control circuit has at least a third and a fourth transistor,
A gate electrode of the fourth transistor is connected to an erasing scanning line;
A method for driving a display device, comprising: an initialization signal line to which a signal for initializing the signal line is input.
A method for driving a display device, wherein the initialization signal line is selected while the erase scanning line is selected. A light-emitting element that emits light based on an analog signal, a capacitor,
A lighting period control circuit connected to both ends of the capacitive element,
The lighting period control circuit has at least a third and a fourth transistor,
A gate electrode of the third transistor is connected to an erasing signal line;
A gate electrode of the fourth transistor is connected to an erasing scanning line;
A method for driving a display device, comprising: an initialization signal line to which a signal for initializing the signal line is input.
By selecting the erasing signal line in synchronization with the selection of the erasing scanning line,
The light emitting element becomes non-light emitting,
A method for driving a display device, wherein the initialization signal line is selected while the erase scanning line is selected. A driving method of a display device including a light-emitting element that emits light based on an analog signal, a capacitor, and a lighting period control circuit connected to both ends of the capacitor,
Dividing the frame period into two or more sub-frame periods,
A driving method of a display device, wherein the order of the sub-frame periods is changed between a pixel arranged on a k-th row and a pixel arranged on a (k + 1) -th row by the lighting period control circuit. A method for driving a display device including a light-emitting element that emits light based on an analog signal, a transistor connected to the light-emitting element, and a lighting period control circuit provided between the light-emitting element and the transistor,
Dividing the frame period into two or more sub-frame periods,
A driving method of a display device, wherein the order of the sub-frame periods is changed between a pixel arranged on a k-th row and a pixel arranged on a (k + 1) -th row by the lighting period control circuit. 21. The method for driving a display device according to claim 15, wherein the transistor is a thin film transistor having a crystalline semiconductor film.

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