JP2004336147A - Signal demodulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal demodulator capable of demodulating a BPSK signal with high accuracy. <P>SOLUTION: The signal demodulator is provided with: a generating means (10) for generating a subcarrier transmission rate clock synchronously with a received BPSK modulation signal, a clock being a multiple of n of the subcarrier transmission rate, a clock being a multiple of 1/n of the subcarrier transmission rate, and a clock being inverse of the subcarrier transmission rate clock; a first correlation demodulation means (20) for applying correlation demodulation to the received signal on the basis of the subcarrier transmission rate clock and the clock being a multiple of n of the subcarrier transmission rate; and a second correlation demodulation means (30) for applying correlation demodulation to the received signal subjected to the correlation demodulation by the first correlation demodulation on the basis of the clock being a multiple of 1/n and the inverse of the clock. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a signal demodulation device for demodulating a BPSK (Binary Phase Shift Keying) modulated signal.
[0002]
[Prior art]
BPSK is a phase modulation method used in wireless communication, for example. BPSK assigns a carrier phase to 0 and a phase opposite to the carrier to 1. The receiving side detects whether the transmitted signal is "0" or "1" by detecting the phase shift. The result of simply sampling the BPSK modulation signal based on a clock synchronized with the BPSK modulation signal is used as a demodulation signal of the BPSK modulation signal.
[0003]
[Problems to be solved by the invention]
Generally, when a BPSK modulation signal is received and demodulated by an analog circuit, a phase delay, a signal waveform distortion, etc. occur at a phase change point due to an influence of a distance between antennas and the like, and the signal is accurately reproduced. Difficult to demodulate.
[0004]
By amplifying and binarizing a received signal including a phase delay, a signal waveform distortion, and the like, received data that cannot be compensated before and after a phase change point is received as a received signal Rx.
[0005]
When a received signal Rx that cannot be compensated after a phase change point is received, the signal is simply sampled and demodulated with a synchronous clock, and thus it is possible to correctly demodulate a change in the received signal Rx due to a phase delay, signal waveform distortion, or the like. And the error rate of the demodulated signal increases.
[0006]
SUMMARY OF THE INVENTION An object of the present invention is to provide a signal demodulation device capable of accurately demodulating a BPSK modulation signal in view of the circumstances described above.
[0007]
[Means for Solving the Problems]
In order to solve the above problems and achieve the object, a signal demodulation device of the present invention is configured as follows.
[0008]
The signal demodulation device of the present invention receives a BPSK modulation signal, and transmits a subcarrier transmission rate clock synchronized with the received signal, an n-times clock of the subcarrier transmission rate, a 1 / n times clock of the subcarrier transmission rate, and Generating means for generating an antiphase clock of the subcarrier transmission rate; first correlation demodulation means for correlating and demodulating the received signal based on the subcarrier transmission rate clock and an n-times clock of the subcarrier transmission rate; Second correlation demodulation means for correlating and demodulating the received signal correlated by the first correlation demodulation means based on a 1 / n clock of the subcarrier transmission rate and a reverse phase clock of the subcarrier transmission rate; It has.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0010]
The BPSK modulation is a method in which one bit of data is encoded using a subcarrier faster than the data transmission rate, and the phase of the subcarrier is inverted at a change point of the data phase. It is assumed that the reception data RXD is encoded by a subcarrier having a transmission rate eight times the transmission rate of the NRZ data.
[0011]
When a BPSK modulation signal is received and demodulated by an analog circuit, a phase delay occurs at a phase change point, a signal waveform distortion occurs, and it is difficult to accurately demodulate the signal.
[0012]
By amplifying and binarizing a received signal including a phase delay, a signal waveform distortion, and the like, received data that cannot be guaranteed after the phase change point is received as the received signal Rx.
s Since the number of bits of the subcarrier after the phase change point cannot be compensated, digital demodulation is performed once on the subcarrier basis from the BPSK code data, and the demodulated data is again correlated with the NRZ data on a 1-bit basis. It is possible to correctly demodulate a change in the received signal Rx due to a waveform distortion or the like, and to reduce the error occurrence rate of the demodulated signal.
[0013]
In the present invention, the above BPSK modulation signal is demodulated in units of 1-bit subcarriers and further demodulated to NRZ using a correlation by a double correlation method.
[0014]
FIG. 1 is a block diagram showing a schematic configuration of a signal demodulation device according to an example of the present invention. As shown in FIG. 1, the signal demodulation device includes a synchronization circuit 10, a first correlation block 20, and a second correlation block 30. The first correlation block 20 includes an eight-stage shift register 21 and a correlation circuit 22. The second correlation block 30 includes an eight-stage shift register 31 and a correlation circuit 32.
[0015]
The reception data RXD is input to the synchronization circuit 10. The synchronizing circuit 10 includes a subcarrier transmission rate clock CLK synchronized with the received data RXD, an eight-fold clock 8CLK of the subcarrier transmission rate clock, a negative phase clock NCLK of the subcarrier transmission rate clock, and ８ of the subcarrier transmission rate clock. A double clock 1/8 CLK is generated.
[0016]
The eight-times clock 8CLK is supplied to an eight-stage shift register 21, the clock CLK is supplied to a correlation circuit 22, the negative-phase clock NCLK is supplied to an eight-stage shift register 31, and 1 / 8CLK is supplied to a correlation circuit 32.
[0017]
Next, the synchronous reception data RXDATA is input to the eight-stage shift register 21 of the first correlation block 20. The first correlation block 20 aims to perform demodulation in units of 1-bit subcarrier, and to demodulate into NRZ signals by the continuous action.
[0018]
The output results Q8-1 sampled at 8CLK are input to the correlation circuit 22. The correlation circuit 22 has, for example, an expected value “11110000” in advance, and further sets a predetermined correlation value (5 in this embodiment, and hereafter, it is assumed that a correlation value 5 is set), and the sampling result Q8 Compare １1 with the expected value. As a result of the comparison, if the number of coincidences is equal to or more than the set correlation value (5 or more in this embodiment), the first post-correlation demodulated data FDATAI is “1” output, and is less than the correlation value (4 or less in this embodiment). In this case, "0" is output.
[0019]
The demodulated data FDATA1 after the first correlation is output at the rising timing of CLK. The operation of the data bits 1, 2, 3, and 4 in FIG. 2 will be described as an example.
[0020]
The data bit1 also has an expected value of “11110000”, and the sampling result of the data bit1 is also “11110000”. As a result, the correlation value is 8. Since the correlation value is 5 or more, "1" is output to the demodulated data FDATA1.
[0021]
For data bit2, the sampling result of data bit2 is "11101000" with respect to the expected value "11110000", and as a result, the correlation value is 6. Since the correlation value is 5 or more, "1" is output to the demodulated data FDATA1.
[0022]
For data bit3, the sampling result of data bit3 is "0110011010" with respect to the expected value "11110000", and as a result, the correlation value is 4. Since the correlation value is 4 or less, "0" is output to the demodulated data FDATA1.
[0023]
For data bit4, the sampling result of data bit4 is "000011111" with respect to the expected value "11110000", and as a result, the correlation value is zero. Since the correlation value is 4 or less, "0" is output to the demodulated data FDATA1.
[0024]
Hereinafter, similarly, FDATA1 is output at the timing of the rising edge of CLK.
[0025]
FDATA1 is input to the eight-stage shift register 31 of the second correlation block 30. The eight-stage shift register 31 outputs the results Q8 to 1 sampled with the negative phase clock NCLK of CLK, and Q8 to 1 are input to the correlation circuit 32.
[0026]
The correlation circuit 32 samples Q8 to Q1 at a 1/8 CLK clock 1/8 CLK, and as a result, if "1" is equal to or greater than a predetermined correlation value (5 in this embodiment), the demodulated NRZ data "1" is output to FDATA2, and "0" is output if "1" is 4 or less.
[0027]
FIG. 3 shows the demodulation timing of FDATA2. As an example, the operation of the NRZ data bits 1 and 2 in FIG. 3 will be described.
[0028]
The NRZ data bit 1 becomes “11011101” as a result of sampling with NCLK, and the number of “1” becomes six as a result. Since the correlation value is 5 or more, "1" is output to the demodulated data FDATA2.
[0029]
The NRZ data bit2 becomes “O0101000” as a result of sampling with NCLK, and the number of “1” becomes two as a result. Since the correlation value is less than 5, "0" is output to the demodulated data FDATA2.
[0030]
Hereinafter, similarly, FDATA2 is output at the timing of the rising edge of 1/8 CLK to become NRZ data. In this way, demodulation with few errors can be performed even when the waveform of the reception data RXD is disturbed due to duty cost, noise, or the like.
[0031]
As described above, the signal demodulation apparatus of the present invention first determines whether the correlation value is "1" or "0" in units of 1-bit subcarriers, and uses the result for every 8 bits to again determine the correlation value. Is determined as "1" or "0", and demodulation based on double correlation, which is finally demodulated as NRZ data, enables correct demodulation with respect to a change in the received signal Rx. Can be reduced.
[0032]
In the present embodiment, the description will be made assuming that the reception data RXD is encoded by a subcarrier having a transmission rate eight times the transmission rate of the NRZ data, and the synchronous reception data RXDATA is eight times the subcarrier transmission rate clock. Although the case of sampling with the clock 8CLK has been described, the present invention is not limited to this. The sampling frequency may be further increased to further increase the demodulation accuracy.
[0033]
It should be noted that the present invention is not limited to the above-described embodiment, and can be variously modified in an implementation stage without departing from the gist thereof. In addition, the embodiments may be implemented in appropriate combinations as much as possible, in which case the combined effects can be obtained. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriate combinations of a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effects described in the column of the effect of the invention can be solved. Is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention.
[0034]
【The invention's effect】
According to the present invention, it is possible to provide a signal demodulation device capable of accurately demodulating a BPSK modulation signal.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a signal demodulation device according to an example of the present invention.
FIG. 2 is a diagram showing a timing chart of each signal in a first correlation block of the signal demodulation device shown in FIG.
FIG. 3 is a diagram showing a timing chart of each signal in a second correlation block of the signal demodulation device shown in FIG. 1;
[Explanation of symbols]
Reference Signs List 10 synchronization circuit, 20 first correlation block, 21 eight-stage shift register, 22 correlation circuit, 30 second correlation block, 31 eight-stage shift register, 32 correlation circuit, RXD reception data, RXDATA Synchronous reception data, CLK: subcarrier transmission rate clock, 8CLK: 8 times clock of subcarrier transmission rate clock, NCLK: reverse phase clock of subcarrier transmission rate clock, 1 / 8CLK: 1/8 times of subcarrier transmission rate clock clock

Claims (3)

A signal demodulation device for demodulating a BPSK modulation signal,
A subcarrier transmission rate clock synchronized with the received BPSK modulated signal, a clock n times the subcarrier transmission rate, a clock 1 / n times the subcarrier transmission rate, and an opposite phase of the subcarrier transmission rate Generating means for generating a clock;
First correlation demodulation means for correlating and demodulating the received signal based on the subcarrier transmission rate clock and an n-times clock of the subcarrier transmission rate;
Second correlation demodulation means for correlating and demodulating the received signal correlated by the first correlation demodulation means based on a 1 / n clock of the subcarrier transmission rate and a reverse phase clock of the subcarrier transmission rate; ,
A signal demodulation device comprising: A signal demodulation device for demodulating a BPSK modulation signal,
A subcarrier transmission rate clock synchronized with the received signal after receiving the BPSK modulation signal, an n-times clock of this subcarrier transmission rate, a 1 / n times clock of this subcarrier transmission rate, and a reverse phase clock of this subcarrier transmission rate Generating means for generating
First sampling means for sampling the received signal based on an n-times clock of the subcarrier transmission rate;
First correlation demodulation means for correlating and demodulating the received signal sampled by the first sampling means based on the subcarrier transmission rate clock;
A second sampling unit that samples the received signal that has been correlated and demodulated by the first correlation demodulation unit based on a reverse phase of the subcarrier transmission rate;
Second correlation demodulation means for correlating and demodulating the received signal sampled by the second sampling means based on a 1 / n clock of the subcarrier transmission rate;
A signal demodulation device comprising: A signal demodulation device for demodulating a BPSK modulation signal,
A subcarrier transmission rate clock synchronized with the received signal after receiving the BPSK modulation signal, an n-times clock of this subcarrier transmission rate, a 1 / n times clock of this subcarrier transmission rate, and a reverse phase clock of this subcarrier transmission rate Generating means for generating
First sampling means for sampling the received signal based on an n-times clock of the subcarrier transmission rate;
The received signal sampled by the first sampling means is compared with a predetermined expected value, and a comparison result is output as first correlation demodulated data based on a preset first correlation value. First correlation demodulation means;
A second sampling unit that samples the first correlation demodulated data output by the first correlation demodulation unit based on a reverse phase of the subcarrier transmission rate;
Second correlation demodulation means for processing the first correlation demodulation data sampled by the second sampling means based on a second correlation value set in advance and outputting as second correlation demodulation data;
A signal demodulation device comprising:

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