JP2004334707A - Memory inspection device and memory inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory inspection device and memory inspection method for efficiently finding out a memory failure by imperfect connection of a data bus and an address bus. <P>SOLUTION: A DSP 2 writes specified data in a specified address of an SDRAM 3 connected to the N-bit address bus and the data bus followed by reading. At this time, when the read address is not matched to the data, a memory failure by the data bus is determined. The DSP 2 writes writing data all-0 in an address No. 0 followed by reading, and performs the processing of reading all the data from the specified address written previously and OR-operating all the data since then. According to this, the address bit position of the memory failure resulted from the address bus can be specified from the data finally calculated. As the determination method, a value 1 is present in a normal bit position, and a value 0 is present in a failure position. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory inspection device and a memory inspection method, and more particularly, to a memory inspection device and a memory inspection method for efficiently checking a memory failure due to a data bus and an address bus.
[0002]
[Prior art]
Conventionally, for finding a memory failure due to incomplete connection of the data bus and the address bus at the time of mounting the board, all possible patterns, data such as all 1, all 0, all A, all 5 are read and written for all addresses of the memory. In the case of a mismatch, an address or data is notified.
[0003]
Further, as a conventional technique of memory check caused by an address bus and a data bus, there is a memory check method disclosed in Patent Document 1. According to Patent Document 1, in a memory address, only one bit is “1” and all other bits are all “0”. After writing the value data, the read and written expected value data are compared with the read data to check for a memory defect due to a defect in the address bus.
[0004]
Further, in the memory control device and the state inspection method disclosed in Patent Document 2, all the voltage levels of the address line and the data line are set to “L” level, or one of a plurality of lines is sequentially set to “L” level. At the "H" level, data reading is performed every time data writing is completed, and the state of the address lines and data lines is checked by comparing the written data with the read data.
[0005]
[Patent Document 1]
JP-A-10-161940
[Patent Document 2]
JP-A-9-237230
[0006]
[Problems to be solved by the invention]
However, in the related art in which data consisting of all possible patterns (such as all 1s) is read / written from / to all addresses of the memory, and the written data is compared with the read data to detect a memory defect, the following technique is used. There were serious problems.
In the prior art described above, the check time increases with an increase in the memory capacity, and even if there is a memory failure due to the address bus, it may not be detected in some cases.
As an example, if the address bits A0 and A1 are connected due to a connection failure, "1" is written to the A0 bit, that is, even if an attempt is made to write data to the address 1, the A1 bit is actually connected to the A0 bit. Therefore, the A1 bit has the same value as the A0 bit, and data is written at the address 11. Further, since the read destination also refers to the address (address 11), it is determined that the address is normal, and it may not be possible to determine that the connection of the address bus is defective.
As described above, since the cause of the memory failure may be due to the incomplete connection of the data bus and the address bus, it is necessary to strengthen these checks and identify the failure of the base board before shipment.
[0007]
Patent Document 1 describes only a memory check method caused by an address bus, and the conventional technique described in Patent Document 1 does not check a connection failure of both a data bus and an address bus.
[0008]
Further, in Patent Document 2, the address value of the data write destination and the value of the data to be written are not set so as to always match.
[0009]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has an object to provide a memory inspection apparatus and a memory inspection method for efficiently finding a memory failure due to an incomplete connection of a data bus and an address bus, thereby shortening a memory check time. The aim is to provide a method.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a memory inspection device connected to a memory via a data bus and an address bus, wherein only one bit has a first value for an N-bit address bus, All other bits have the same address value and write data value as the second value, write specific data to a specific address, read and compare, and perform a memory check caused by the data bus. And
[0011]
The present invention also relates to a memory test device connected to a memory via a data bus and an address bus, wherein only one bit in an N-bit address bus is a first value, and all other bits are a second value. First data writing means for writing data of the same value as each address value for each address of the first value, and first data reading means for reading data of each address written by the first data writing means Data comparing means for comparing the value of each address to which data is written with the data read from the address by the first data reading means; and data read from the address value and the address by the data comparing means. If it is determined that there is an address that does not match with the information, information indicating that the data bus connection is defective is provided. A data bus connection information transmitting unit for output, characterized by having a.
[0012]
Further, according to the present invention, the data bus connection information sending means can determine whether the data bus connection information is inferior to the data bus connection information using the lower-order bits of the lower-order digits where the first value exists in the address value that did not match the data. Is transmitted to the effect that there is a.
[0013]
According to the invention, the first value is 1 and the second value is 0.
[0014]
Further, according to the present invention, the second data writing means for writing data of which all bits have the second value to the address of which all bits on the address bus have the second value, and the first data writing means, Means and second data reading means for reading data written by the second data writing means, OR operation means for performing an OR operation on all data read by the second data reading means, and OR operation means And an address bus connection information transmitting means for transmitting information indicating that the connection of the address bus is defective when the value of the second value includes a digit of the second value.
[0015]
Further, according to the present invention, the first value is 0 and the second value is 1.
[0016]
Further, according to the present invention, the second data writing means for writing data of which all bits have the second value to the address of which all bits on the address bus have the second value, and the first data writing means, Means and second data reading means for reading data written by the second data writing means, AND operation means for performing an AND operation on all data read by the second data reading means, and AND operation means And an address bus connection information transmitting means for transmitting information indicating that the connection of the address bus is defective when the value of the second value includes a digit of the second value.
[0017]
Further, according to the present invention, the address bus connection information sending means determines that the connection failure of the address bus exists in the lower order bits of the calculated value in the lowermost digits of the digit in which the second value exists. Is transmitted.
[0018]
The present invention also relates to a memory inspection method using a memory inspection device connected to a memory via a data bus and an address bus, wherein the memory inspection device has only one bit for an N-bit address bus. Is the first value, all other bits are the second value, the address value and the write data value are the same value, the specific data is written to the specific address, read and compared, and the memory caused by the data bus is A check is performed.
[0019]
Further, the present invention is a memory inspection method using a memory inspection device connected to a memory via a data bus and an address bus, wherein the memory inspection device is configured such that only one bit in an N-bit address bus is used. A first data writing step of writing data having the same value as each address value to each address having a value of 1 and all other bits having a second value; A first data reading step of reading data of each address written by the first step, and data for comparing the value of each address where the data is written by the memory inspection device with data read from each address in the first data reading step. In the comparison step, the memory inspection apparatus determines that the address value and the data read from the address are in the data comparison step. If never been address match is determined to exist, and having a data bus connection information sending step of sending information indicating the connection of the data bus is faulty, the.
[0020]
Further, according to the present invention, the data bus connection information sending step is such that the memory inspection device uses the lower order bits of the lower order digits where the first value exists in the address value that did not match the data. It is characterized by transmitting information indicating that a data bus connection failure exists.
[0021]
According to the invention, the first value is 1 and the second value is 0.
[0022]
Further, according to the present invention, the memory inspection device performs a second data writing step of writing data of which all bits have the second value with respect to the address of which all bits on the address bus have the second value; A second data reading step in which the memory inspection device reads the data written in the first data writing step and the second data writing step, and a memory inspection device for reading all the data read in the second data reading step. When the memory inspection apparatus determines that the second value digit is present in the value calculated by the OR operation step, information indicating that the connection of the address bus is defective is sent out. Address bus connection information sending step.
[0023]
Further, according to the present invention, the first value is 0 and the second value is 1.
[0024]
Further, according to the present invention, the memory inspection device performs a second data writing step of writing data of which all bits have the second value with respect to the address of which all bits on the address bus have the second value; A second data reading step in which the memory inspection device reads the data written in the first data writing step and the second data writing step, and a memory inspection device for reading all the data read in the second data reading step. An AND operation step of performing an AND operation by the memory test apparatus, and when the memory inspection device determines that the value calculated by the AND operation step includes a second digit, information indicating that the connection of the address bus is defective is transmitted. Address bus connection information sending step.
[0025]
According to the present invention, in the address bus connection information sending step, the memory inspection device may include a step of connecting the address bus with the lower number of bits of the calculated value where the second value is present. It is characterized by transmitting information indicating that a defect exists.
[0026]
According to the present invention, specific data is written to and read from a specific address in a memory connected to an N-bit address bus and a data bus. At this time, if the read address does not match the data, it is determined that the memory is defective due to the data bus. Next, write data and all 0s are written and read at address 0, and thereafter, all data are read from the specific address written earlier, and all the data are subjected to an OR operation.
By performing these steps, the address bit position of the memory failure due to the address bus can be specified from the finally calculated data. As a determination method, a value of 1 is set at a normal bit position and a value of 0 is set at a defective bit position.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
<First embodiment>
(Configuration of the first embodiment)
FIG. 1 is a diagram showing a configuration of a memory inspection system according to the first embodiment of the present invention.
As shown in FIG. 1, the memory inspection system includes a display terminal 1, a DSP (Digital Signal Processor) 2, and an SDRAM (Random Access Memory) 3.
[0028]
The display terminal 1 is an information processing device such as a PC (Personal Computer) that displays a message for starting a test and a result.
[0029]
The DSP 2 is a processor that internally stores a program for performing a test in advance, and functions as a memory inspection device. The DSP 2 performs a test on the SDRAM 3 by receiving a test start command from the display terminal 1 connected via the network, and returns the result to the display terminal 1. Note that the DSP 2 may be another type of information processing device such as a general-purpose MPU (Microprocessing Unit).
[0030]
The SDRAM 3 is a storage medium to be checked for a memory failure by the DSP 2. The DSP 2 and the SDRAM 3 are connected by a control bus, an address bus, and a data bus. Note that the SDRAM 3 may be another memory as long as it is a memory that can be randomly accessed.
[0031]
(Operation of First Embodiment)
FIG. 2 and FIG. 3 are flowcharts showing the flow of processing by the DSP 2 according to the first embodiment of the present invention. Hereinafter, the processing executed by the DSP 2 according to the program stored therein will be described with reference to FIG. 1 and along FIG. 2 and FIG.
[0032]
First, when the test is started, the DSP 2 checks the data bus between the DSP 2 and the SDRAM 3.
As actual processing, the DSP 2 sets the write destination address to the address A = 1 (step S1), sets the same numerical write data WD = 1 as the address (step S2), and sets the logical value to “1”. After setting the first bit (least significant bit) from the lower end of the address bus as bit B of the address bus ("bit B = 1") (step S3), data is written to the memory (SDRAM 3) (step S4). .
[0033]
Next, the DSP 2 reads data (read data RD) from the address A written in step S4 (step S5), and checks whether or not the address matches the data (step S6).
[0034]
If it is determined that the address does not match the data (step S6 / No), the DSP 2 increments the error number by “1” and sends the value of the address A and the data of the read data RD to a recording device (not shown). After saving (step S7), the process moves to step S8.
[0035]
When it is determined that the address and the data match (step S6 / Yes), the DSP 2 changes the write address and the data (steps S8 to S10).
Specifically, the DSP 2 shifts and sets the bit B of the address bus whose logical value is “1” by one bit higher (step S8). Next, the DSP 2 sets the address of the SDRAM 3 to be written to address A = 2 ＾ (B-1) (step S9). Further, the DSP 2 sets the write data to be written to the address A (= 2 ＾ (B-1)) to the write data WD = 2 ＾ (B-1) as in the case of the address A (step S10).
Here, the DSP 2 shifts the bit B of the address bus by one bit to “2” (step S8), and updates the address A = 2 (step S9) and the write data WD = 2 (step S10), respectively. I do.
[0036]
Thereafter, the DSP 2 determines whether or not the value of the bit B shifted in step S8 has exceeded the maximum number N of bits of the address bus (step S11).
[0037]
If the value of the bit B does not exceed the maximum number of bits N (step S11 / No), the DSP 2 writes the updated data to the updated address and repeats the processing of steps S4 to S11.
[0038]
When the value of the bit B exceeds the maximum bit number N (step S11 / Yes), the DSP 2 checks whether or not the number of errors recorded in the recording device (not shown) is zero (step S12). .
[0039]
If there is only one error (step S12 / No), the display terminal 1 displays the data bus error, the value of the address A stored at the time of the error, and the data of the read data RD in response to the instruction of the DSP 2 (step S12 / No). Step S13), the test ends.
[0040]
If the number of errors is 0 (step S12 / Yes), the DSP 2 moves to the next address bus check processing (steps S14 to S26). Here, the display terminal 1 may display a message indicating that the connection of the data bus is normal according to the instruction of the DSP 2.
[0041]
The DSP 2 sets a write destination address A = 0 for writing data (step S14).
[0042]
Next, the DSP 2 sets the write data WD = 0 to be written to the write destination address A = 0 set in step S14 (step S15).
[0043]
Next, the DSP 2 sets the result data FD = 0 (step S16). The result data FD is data indicating a result of checking the address bus.
[0044]
Next, the DSP 2 sets the bit B of the address bus to 0 (step S17).
[0045]
Next, the DSP 2 writes the write data WD set in step S17 to the address A set in step S16 (step S18).
[0046]
Next, the DSP 2 reads the data (read data RD) at the address A set in step S16 (step S19).
[0047]
Next, the DSP 2 performs an OR operation on the read data RD read in step S19 (step S20). At the time of the first OR operation, the read data RD that has been read is directly reflected in the result data FD.
[0048]
Next, the DSP 2 shifts and sets the bit B of the address bus whose logical value is “1” by one bit higher (step S21).
[0049]
Next, the DSP 2 sets the address of the SDRAM 3 to be read to the address A = 2 ＾ (B-1) (step S22).
[0050]
Thereafter, the DSP 2 determines whether or not the value of the bit B shifted in step S21 has exceeded the maximum bit number N of the address bus (step S23).
[0051]
If the value of the bit B does not exceed the maximum bit number N (step S23 / No), the DSP 2 performs the processing of steps S19 to S23 in order from address A = 1 to address 2, address 4, address 8,. After reading up to the maximum number of bits of the address bus, an OR operation is performed to update the result data FD.
[0052]
When the value of the bit B exceeds the maximum bit number N, that is, when the operation is performed up to the maximum bit number N of the address bus (step S23 / Yes), the DSP 2 determines whether the result data FD is ALL “1”. It is confirmed whether or not it is (step S24).
[0053]
If the result data FD is ALL "1" (step S24 / Yes), the display terminal 1 displays "data bus, address bus OK" according to the instruction of the DSP 2 (step S25), and ends.
[0054]
If there is "0" in a certain bit in the result data FD (step S24 / No), the DSP 2 determines that the bit that has become "0" is an NG bit of the address bus and responds to the instruction of the DSP 2 The display terminal 1 displays the result data FD and "address bus NG" (step S26), and ends.
As described above, the memory failure check caused by the data bus and the address bus is performed.
[0055]
Next, as a specific embodiment, an example in which the address bus and the data bus between the DSP 2 and the SDRAM 3 are each configured by 16 bits will be described.
[0056]
FIG. 4 is a diagram showing write data WD, read data RD, and result data FD at each address A when there is no connection failure in the address bus and the data bus in the first embodiment of the present invention.
FIG. 4 shows write data WD written to each address A of the SDRAM 3, final write data (that is, read data RD), and result data FD calculated by an OR operation of the read data RD. ing.
Note that “0” to “15” in the address A indicate the number of bits from the lower order of the address A.
The address A, the read data RD, and the result data FD are represented in a binary system, and the write data WD is represented in a hexadecimal system ("H" at the end of the write data WD indicates a hexadecimal number). ).
[0057]
First, when the processes of steps S1 to S12 in FIG. 2 are performed, the DSP 2 writes the write data WD to each address A in order from the process 1 in FIG. 4 to the process 16, and then reads the read data RD.
If there is an abnormality in the data bus at this point, a difference occurs between the address A of the address and the value of the write data WD (read data RD).
[0058]
Next, when the processing in steps S14 to S18 in FIG. 2 is performed, the DSP 2 writes ALL “0” at the address 0 as in processing 17 in FIG.
[0059]
After that, when the processes of steps S19 to S23 in FIG. 2 are performed, the DSP 2 reads the data in the order of the address address 0, the address address 1, the address address 2, the address address 4,. Specifically, the result data FD (= ALL “1”) is calculated as in processing 18 of FIG. With such a result, it can be determined that there is no connection failure of the address bus.
[0060]
FIG. 5 is a diagram showing the write data WD, the read data RD, and the result data FD at each address A when the bit 0 of the address bus has a fixing failure of 0 in the first embodiment of the present invention. The meaning of each item in FIG. 5 is the same as in FIG. Note that “0x” in the following “0x...” Indicates that the four-digit number indicated by “...” Is represented in hexadecimal. “Fixation failure” indicates a failure in which a certain bit is always fixed to a specific value (0 or 1) irrespective of the write processing of the processor.
[0061]
First, in the process 1 of FIG. 5, the DSP 2 attempts to write to the address 1, but actually writes the write data “0x0001” to the address 0 because there is a fixing failure of 0 at the 0th bit of the address.
Next, in the processing 2 of FIG. 5, even if there is a fixing failure of 0 at the 0th bit of the address, the DSP 2 correctly writes the write data “0x0002” at the address 2.
Similarly, the DSP 2 correctly writes the write data up to the processing 16 in FIG.
Next, in processing 17 of FIG. 5, the DSP 2 writes the data of ALL “0” at the address 0, so that the data of “0x0001” written in the processing 1 of FIG. 5 is overwritten with “0x0000”. .
When data is read in order from the address 0 and an OR operation is performed, the result data FD becomes “0xFFFE” in the processing 18 of FIG. 5 and the 1-th bit is not set in the 0-th bit. It can be seen that a defect has occurred.
[0062]
FIG. 6 is a diagram showing the write data WD, the read data RD, and the result data FD at each address A when the bit 0 of the address bus has a fixing failure of 1 in the first embodiment of the present invention. The meaning of each item in FIG. 6 is the same as in FIG.
[0063]
First, in process 1 of FIG. 6, although there is a fixing defect of 1 at the 0th bit of the address, the DSP 2 correctly writes the write data “0x0001” at the address 1.
Next, in process 2 of FIG. 6, the DSP 2 actually writes the write data "0x0002" to the address "0x0003" because there is a fixing failure of 1 at the 0th bit of the address.
Similarly, in processing 3 to processing 16 in FIG. 6, the DSP 2 writes the write data WD to an address different from the desired address.
In the process 17 of FIG. 6, the DSP 2 tries to write the data of ALL “0” at the address 0. However, since there is a fixing failure of 1 at the 0th bit of the address, the DSP 2 actually has ALL “0” at the address 1 Therefore, the data (0x0001) written at the address 1 performed in the process 1 of FIG. 6 is rewritten to ALL “0”.
In the process 18 of FIG. 6, the DSP 2 reads the data in order from the address 0 and performs an OR operation. When the result data FD becomes “0xFFFE” and the 0th bit is not set to “1”, the DSP 2 It can be seen that a connection failure has occurred at the 0th bit.
[0064]
FIG. 7 is a diagram showing write data WD, read data RD, and result data FD at each address A in the case where a failure occurs due to the connection of bit 0 and bit 1 of the address bus in the first embodiment of the present invention. It is. The meaning of each item in FIG. 7 is the same as in FIG.
[0065]
First, in the processing 1 of FIG. 7, since the 0th bit and the 1st bit of the address are connected, the DSP 2 does not write the write data "0x0001" at the address "0x0001" but writes the data at the address "0x0003". Write data "0x0001".
Next, in the process 2 of FIG. 7, similarly to the process 1 of FIG. 7, the DSP 2 writes the write data “0x0002” at the address “0x0003”, and the write data “0x0001” written in the process 1 of FIG. Rewritten as "0x0002".
Thereafter, in processing 3 to processing 17 in FIG. 7, the DSP 2 normally writes data to a desired address.
Finally, in process 18 of FIG. 7, when the DSP 2 reads data in order from address 0 and performs an OR operation, the result data FD becomes “0xFFFE” and a connection failure occurs at the 0th bit of the address bus. You can see that there is.
[0066]
As described above, similarly to the examples other than the examples shown in FIGS. 5 to 7, the memory inspection system also detects a failure of the memory (SDRAM 3) due to a fixing failure or a connection failure occurring in other bits of the address bus. Can be detected.
[0067]
As described above, according to the present embodiment, the DSP 2 operates in the same manner as the address A for the address A in which one of the bits of the address bus is “1” and all the other bits are “0”. After writing the write data WD, the written data (read data RD) is read. At this time, assuming that the number of bits of the address bus is N, the DSP 2 performs N times of writing and reading processing on the SDRAM 3.
The DSP 2 compares the value of the write data WD (address A) with the value of the read data RD, and determines whether the values of the two data match. If the values of the two data do not match, the DSP 2 determines that a connection failure of the data bus to at least one of the DSP 2 and the SDRAM 3 has occurred, and requests the display terminal 1 to display a message indicating a connection failure of the data bus. I do.
Thus, the memory inspection system can efficiently detect a connection failure between the DSP 2 and the SDRAM 3 due to the data bus.
Further, the DSP 2 can specify the bit of the data bus in which the connection failure has occurred by detecting the address A that has not been matched.
[0068]
Further, according to the present embodiment, the DSP 2 writes the write data WD similar to the address A to the address A in which one of the bits of the address bus is “1” and all the other bits are “0”. After writing, further, write data WD of ALL “0” is written to address 0 of address A. Next, the DSP 2 reads the written data (read data RD). At this time, assuming that the number of bits of the address bus is N, the DSP 2 performs (N + 1) write and read processes on the SDRAM 3.
The DSP 2 performs an OR operation on all the read data RD that have been read, calculates the result data FD, and determines whether all the digits of the calculated result data FD are “1”.
If the result data FD is ALL “1”, the DSP 2 determines that the connection of the address bus between the DSP 2 and the SDRAM 3 is normal, and displays a message to the display terminal 1 indicating that the connection of the data bus is normal. Make a request.
On the other hand, if the result data FD is not ALL “1”, the DSP 2 determines that the connection failure of the address bus to at least one of the DSP 2 and the SDRAM 3 has occurred, and indicates the connection failure of the address bus to the display terminal 1. Make a message display request.
Thus, the memory inspection system can efficiently detect a connection failure between the DSP 2 and the SDRAM 3 due to the address bus.
Further, the DSP 2 can identify the bit of the address bus in which the connection failure has occurred by detecting the “0” bit in the result data FD.
[0069]
Further, in the present embodiment, when performing the connection test of the address bus subsequent to the connection test of the data bus, the DSP 2 executes (N + 1) write processes and (2N + 1) read processes.
[0070]
<Second embodiment>
(Configuration and Operation of Second Embodiment)
Hereinafter, unless otherwise specified, the configuration and operation in the second embodiment of the present invention will be described as being the same as those in the first embodiment of the present invention.
[0071]
FIG. 8 is a diagram showing write data WD, read data RD, and result data FD at each address A when there is no connection failure in the address bus and the data bus in the second embodiment of the present invention.
[0072]
In the first embodiment, the DSP 2 writes the write data “0x0001” at the address 1.
On the other hand, in the present embodiment, as shown in FIG. 8, the DSP 2 includes the address A to be written / read, the write data WD, and the read data RD in the first embodiment shown in FIG. All bits are set to inverted values.
[0073]
In the process 1 of FIG. 8, the DSP 2 writes the write data “0xFFFE” at the address FFFE and executes the process.
Similarly, the DSP 2 writes the write data “0xFFFD” at the address FFFD in the process 2 of FIG. 8, and writes the read data RD written to each address A after writing the processes 3 to 16 in FIG. Read and check the data bus.
Next, the DSP 2 writes the write data “0xFFFF” to the address FFFF in the process 17 of FIG.
Thereafter, the DSP 2 reads the data in order of the address “0xFFFF”, the address “0xFFFE”, the address “0xFFFD”, the address “0xFFFB”,..., And performs the AND operation. Finally, when the result data FD becomes ALL “0” as in the process 18 in FIG. 8, the DSP 2 can determine that there is no memory failure due to the address bus and the data bus. In the case of abnormality, 1 is added to the bit of the abnormal part in the result data FD.
[0074]
As described above, according to the present embodiment, the DSP 2 operates in the same manner as the address A for the address A in which one of the bits of the address bus is “0” and all the other bits are “1”. After writing the write data WD, the written data (read data RD) is read. At this time, assuming that the number of bits of the address bus is N, the DSP 2 performs N times of writing and reading processing on the SDRAM 3.
The DSP 2 compares the value of the write data WD (address A) with the value of the read data RD, and determines whether the values of the two data match. If the values of the two data do not match, the DSP 2 determines that a connection failure of the data bus to at least one of the DSP 2 and the SDRAM 3 has occurred, and requests the display terminal 1 to display a message indicating a connection failure of the data bus. I do.
Thus, the memory inspection system can efficiently detect a connection failure between the DSP 2 and the SDRAM 3 due to the data bus.
Further, the DSP 2 can specify the bit of the data bus in which the connection failure has occurred by detecting the address A that has not been matched.
[0075]
Further, according to the present embodiment, the DSP 2 writes the same write data WD as the address A for the address A in which one of the bits of the address bus is “0” and all the other bits are “1”. After writing, the write data WD of ALL “1” is further written to the address FFFF of the address A. Next, the DSP 2 reads the written data (read data RD). At this time, assuming that the number of bits of the address bus is N, the DSP 2 performs (N + 1) write and read processes on the SDRAM 3.
The DSP 2 performs an AND operation on all the read data RD thus read to calculate the result data FD, and determines whether all the digits of the calculated result data FD are “0”.
If the result data FD is ALL “0”, the DSP 2 determines that the connection of the address bus between the DSP 2 and the SDRAM 3 is normal, and displays a message to the display terminal 1 that the connection of the data bus is normal. Make a request.
On the other hand, if the result data FD is not ALL “0”, the DSP 2 determines that the connection failure of the address bus to at least one of the DSP 2 and the SDRAM 3 has occurred, and indicates the connection failure of the address bus to the display terminal 1. Make a message display request.
Thus, the memory inspection system can efficiently detect a connection failure between the DSP 2 and the SDRAM 3 due to the address bus.
Further, the DSP 2 can identify the bit of the address bus in which the connection failure has occurred by detecting the “1” bit in the result data FD.
[0076]
Further, in the present embodiment, when performing the connection test of the address bus subsequent to the connection test of the data bus, the DSP 2 executes (N + 1) write processes and (2N + 1) read processes.
[0077]
<Summary of Embodiment>
As described above, in the embodiment of the present invention, the address bus and the data bus connecting the DSP 2 and the SDRAM 3 are composed of 16 bits. However, if the number of bits of the address bus and the data bus is the same, , The number of bits may be different.
[0078]
The DSP 2 also writes data into the SDRAM 3, reads the data, compares the write data WD (address A) with the read data RD, requests the display terminal 1 to display a screen, AND, OR, And a process of determining the value of the result data FD.
In addition, the display terminal 1 performs a process of instructing the DSP 2 to start a connection test of the data bus and the address bus, and a process of displaying a screen.
The above processing is executed by a computer program included in the display terminal 1 or the DSP 2, and the above program is recorded on a recording medium such as an optical recording medium, a magnetic recording medium, a magneto-optical recording medium, or a semiconductor. It may be loaded from a recording medium or from an external device connected via a predetermined network.
[0079]
Note that the above embodiment is an example of a preferred embodiment of the present invention, and the embodiment of the present invention is not limited to this, and may be variously modified and implemented without departing from the gist of the present invention. Becomes possible.
[0080]
【The invention's effect】
As described above, according to the present invention, the memory inspection device writes specific data to a specific address, reads data at each address, and compares the written data with the read data. The memory inspection device performs an OR operation or an AND operation on the read data, and compares the calculated value with a normal value. Therefore, it is possible to perform a memory check efficiently.
[0081]
Further, according to the present invention, the memory inspection device detects a bit position where both the data bus and the address bus are defective as a final result. Therefore, it is possible to easily specify a defective portion of the memory.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a memory inspection system according to a first embodiment of the present invention.
FIG. 2 is a flowchart showing an operation flow of the memory inspection system according to the first embodiment of the present invention.
FIG. 3 is a flowchart illustrating an operation flow of the memory inspection system according to the first embodiment of the present invention.
FIG. 4 is a diagram showing a process of an inspection result in a normal state according to the first embodiment of the present invention.
FIG. 5 is a diagram illustrating a process of an inspection result when a bit 0 of an address bus has a fixed defect of 0 according to the first embodiment of the present invention.
FIG. 6 is a diagram illustrating a process of an inspection result in a case where there is a fixing failure of 1 in bit 0 of an address bus according to the first embodiment of the present invention.
FIG. 7 is a diagram showing a process of an inspection result when there is a defect in which bit 0 and bit 1 of the address bus are connected according to the first embodiment of the present invention.
FIG. 8 is a diagram illustrating a process of an inspection result in a normal state according to the second embodiment of the present invention.
[Explanation of symbols]
1 display terminal
2 DSP
3 SDRAM

Claims (16)

A memory inspection device connected to a memory via a data bus and an address bus,
With respect to the address bus consisting of N bits, only one bit has a first value, and all other bits have a second value, so that an address value and a write data value are the same value. A memory inspection device which reads, compares, and performs a memory check caused by the data bus. A memory inspection device connected to a memory via a data bus and an address bus,
First data write for writing data of the same value as each address value for each address in which only one bit in the address bus consisting of N bits has a first value and all other bits have a second value Means,
First data reading means for reading data at each address written by the first data writing means;
Data comparing means for comparing the value of each address at which the data is written with data read by the first data reading means from each of the addresses;
If the data comparing means determines that there is an address where the address value does not match the data read from the address, a data bus connection for transmitting information indicating that the data bus connection is defective. Information sending means;
A memory inspection device, comprising: The data bus connection information sending means includes:
And transmitting information indicating that there is a connection failure of the data bus by the lower-order bits of the number of digits from the lower end where the first value is present in the address value that did not match the data. 3. The memory inspection device according to claim 2, wherein: 4. The memory inspection device according to claim 2, wherein the first value is 1, and the second value is 0. A second data writing unit in which all bits of the address bus write the data of the second value with respect to the address of the second value;
Second data reading means for reading data written by the first data writing means and the second data writing means;
OR operation means for performing an OR operation on all data read by the second data reading means;
Address bus connection information sending means for sending information indicating that the connection of the address bus is defective, when the value calculated by the OR operation means has a digit of the second value;
The memory inspection device according to claim 4, comprising: 4. The memory inspection device according to claim 2, wherein the first value is 0 and the second value is 1. A second data writing unit in which all bits of the address bus write the data of the second value with respect to the address of the second value;
Second data reading means for reading data written by the first data writing means and the second data writing means;
AND operation means for performing an AND operation on all data read by the second data reading means;
Address bus connection information transmitting means for transmitting information indicating that the connection of the address bus is defective, when the value of the second value exists in the value calculated by the AND operation means;
7. The memory inspection device according to claim 6, comprising: The address bus connection information sending means includes:
6. The information indicating that there is a connection failure of the address bus using lower-order bits of the number of lower-order digits of the digit where the second value exists in the calculated value. 8. The memory inspection device according to 7. A memory inspection method using a memory inspection device connected to a memory via a data bus and an address bus,
The memory testing apparatus sets the address value and the write data value to the same value as the N-bit address bus, where only one bit is a first value and all other bits are second values, A memory inspection method, comprising writing and reading specific data, performing comparison, and performing a memory check caused by the data bus. A memory inspection method using a memory inspection device connected to a memory via a data bus and an address bus,
The memory inspecting apparatus, for each address in which only one bit in the N-bit address bus has a first value and all other bits have a second value, writes data having the same value as each address value. A first data writing step for writing;
A first data reading step in which the memory inspection device reads data at each address written in the first data writing step;
A data comparing step of comparing the value of each address where the data is written and the data read from the respective addresses in the first data reading step,
When the memory inspection device determines in the data comparison step that there is an address where the address value does not match the data read from the address, information indicating that the connection of the data bus is defective is provided. Sending data bus connection information sending step;
A memory inspection method, comprising: The data bus connection information sending step includes:
The memory inspection device may provide information indicating that there is a connection failure of the data bus using lower-order bits of the number of lower-order digits where the first value is present at an address value that did not match the data. 11. The memory inspection method according to claim 10, wherein the transmission is performed. 12. The memory inspection method according to claim 10, wherein the first value is 1, and the second value is 0. A second data writing step in which the memory inspection device writes all bits of the address bus with the second value of the address and all digits of the address with the second value;
A second data reading step in which the memory inspection device reads data written in the first data writing step and the second data writing step;
An OR operation step in which the memory inspection device performs an OR operation on all data read in the second data reading step;
An address bus connection information transmitting step of transmitting information indicating that the connection of the address bus is defective, when the memory inspection device determines that the second value digit is present in the value calculated by the OR operation step; When,
13. The memory inspection method according to claim 12, comprising: 12. The memory inspection method according to claim 10, wherein the first value is 0 and the second value is 1. A second data writing step in which the memory inspection device writes all bits of the address bus with the second value of the address and all digits of the address with the second value;
A second data reading step in which the memory inspection device reads data written in the first data writing step and the second data writing step;
An AND operation step in which the memory inspection device performs an AND operation on all data read in the second data reading step;
An address bus connection information transmitting step of transmitting information indicating that the connection of the address bus is defective, when the memory inspection device determines that the digit of the second value exists in the value calculated by the AND operation step; When,
The memory inspection method according to claim 14, comprising: The address bus connection information sending step includes:
The memory inspection device sends information indicating that there is a connection failure of the address bus using lower-order bits of the number of digits from the lowermost digit where the second value in the calculated value exists. 16. The memory inspection method according to claim 13, wherein:

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