JP2004327677A - Semiconductor film and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a crystalline semiconductor film having high reliability with sufficiently reduced content of catalytic elements. <P>SOLUTION: The method for manufacturing a semiconductor film comprises steps of preparing a first semiconductor film 104b containing the catalytic elements for accelerating crystallization of an amorphous semiconductor film 104, providing a second semiconductor film 107 to be in contact with an upper part of the first semiconductor film 104b, transferring the catalytic elements present in the first semiconductor film 104b to the second semiconductor film 107 by giving a first heat treatment to the first semiconductor film 104b, oxidizing the second semiconductor film 107, and removing an oxidized second semiconductor film 109. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor film used for a thin film transistor (hereinafter, sometimes abbreviated as “TFT”) and the like, and a method for manufacturing the same, and further relates to a semiconductor device using the semiconductor film. In particular, the present invention can be used for an active matrix type liquid crystal display device, organic EL display device, contact image sensor, three-dimensional IC, and the like.
[0002]
[Prior art]
In recent years, large-scale, high-resolution liquid crystal display devices and organic EL display devices, high-speed, high-resolution contact-type image sensors, and three-dimensional ICs have been developed on glass or other insulating substrates or insulating films. Attempts have been made to form high performance semiconductor devices. In particular, a liquid crystal display device in which a pixel portion and a driver circuit are provided over the same substrate has begun to enter not only a monitor for a personal computer (PC) but also into general households. For example, instead of a CRT (Cathode-Ray Tube), a liquid crystal display as a television, and a front projector for watching a movie or playing a game as entertainment are introduced into ordinary households. The market for equipment is growing at a considerable rate. Further, the development of a system-on-panel in which a logic circuit such as a memory circuit or a clock generation circuit is built on a glass substrate has been actively promoted.
[0003]
The amount of information to be written to pixels for displaying high-resolution images is increasing. If the information is not written in a short time, it is impossible to display a moving image of an image having a huge amount of information for high-definition display. Therefore, high-speed operation is required for the TFT used in the drive circuit. In order to enable high-speed operation, it is required to realize a TFT using a crystalline semiconductor film having good crystallinity and capable of obtaining high field-effect mobility.
[0004]
As a method for obtaining a good crystalline semiconductor film over a glass substrate, the present inventors have proposed a method in which a metal element having a function of accelerating crystallization is added to an amorphous semiconductor film and then heat treatment is performed. We are developing a technology to obtain a good semiconductor film with uniform crystal orientation by heat treatment at lower temperature and shorter time.
[0005]
However, a TFT manufactured using a crystalline silicon film obtained using a catalytic element as a semiconductor layer as it is has a problem that off-current is suddenly increased. Irregular segregation of the catalytic element in the semiconductor film, particularly this segregation is remarkably confirmed at the crystal grain boundaries. This segregation of the catalytic element becomes a current escape path (leakage path). It is thought that it is causing a significant increase. Therefore, after the step of forming the crystalline silicon film, it is necessary to move the catalyst element from within the semiconductor film to reduce the concentration of the catalyst element in the semiconductor film. Hereinafter, the step of removing the catalyst element is referred to as a gettering step.
[0006]
Various processes and methods have been proposed for the gettering process and gettering method. In general, a gettering region having a gettering function is formed, and a catalytic element is moved to the gettering region to reduce a catalytic element concentration in an active region (semiconductor layer) of a semiconductor device. The relationship between the semiconductor layer and the gettering region can be divided into the following three methods.
[0007]
{Circle around (1)} In the crystalline semiconductor film, a gettering region is formed in a region other than a region to be a semiconductor layer, and a catalytic element is moved there.
[0008]
{Circle around (2)} A gettering region is formed in the semiconductor layer, and the catalytic element is moved to the gettering region, so that only a portion (such as a channel region) where the remaining catalytic element is particularly problematic in the semiconductor layer is obtained.
[0009]
{Circle around (3)} In the state of the crystalline semiconductor film, a gettering layer is formed on the upper surface thereof, and the catalytic element is moved in a direction perpendicular to the film surface.
[0010]
Among these methods, in the above method (1), in order to allow a region other than the semiconductor layer to function as a gettering region in the crystalline semiconductor film, selective use of an element having a gettering effect (gettering element) is performed. It is necessary to perform a proper introduction. Therefore, a photolithography process for forming a mask at that time, a doping process for introducing a gettering element, and the like are increased, resulting in an increase in manufacturing cost and a reduction in manufacturing yield. Further, since the catalyst element is moved to a region other than the semiconductor layer, the distance required for the movement of the catalyst element (gettering distance) is increased, and a long time is required for the heat treatment for the gettering movement. In this case, not only the tact time of the apparatus is increased and the manufacturing cost is increased, but also a large glass substrate or the like is at a level where thermal deformation of the substrate cannot be dealt with, and it is even difficult to manufacture.
[0011]
Further, the method (2) is advantageous in that the use of the source / drain region as a gettering region eliminates the need for an additional step for gettering, thereby simplifying the manufacturing process. Is big. However, in the doping process at this time, it is necessary to satisfy both the conditions as the source / drain regions and the gettering, and the process margin becomes very small. Further, since heat treatment for gettering is performed after the formation of the semiconductor layer, the problem of shrinkage in the glass substrate is large, and it is difficult to perform heat treatment sufficient for gettering. Therefore, in this method, the degree of freedom of the process after the formation of the semiconductor layer is greatly limited due to gettering, and the condition margin of each step is small.
[0012]
In contrast to these methods, in the method (3), gettering is performed in the vertical direction in a state where the crystalline semiconductor film is formed on the entire surface of the substrate (a stage before the first photolithography step). Although some additional steps for gettering are required, the heat treatment conditions for gettering can be set regardless of the shrinkage of the glass substrate, and sufficient heat treatment is possible. Further, the required gettering distance is sufficient only in the thickness direction of the crystalline semiconductor film. Further, since gettering can be completed in the state of the crystalline semiconductor film, a process with a high degree of freedom can be constructed without considering a gettering step in a later step. From such a viewpoint, the advantage of the method (3) is great.
[0013]
Gettering methods using the method (3) are described in Patent Documents 1, 2 and 3.
[0014]
Patent Document 1 discloses a method of transferring a catalytic element into an oxide film by thermally oxidizing the surface of a single crystal silicon film crystallized with a catalytic element using an SOI substrate. . Thereafter, gettering of the single crystal silicon film is completed by removing the oxide film formed by thermal oxidation. According to Patent Document 1, the oxidizing atmosphere at this time is an atmosphere containing a halogen element, and the catalytic element is vaporized and removed by the action, and is moved into the thermal oxide film and gettered.
[0015]
In Patent Documents 2 and 3, a barrier layer is formed on a semiconductor film crystallized by a catalyst element, and a second semiconductor film and a third semiconductor film containing a gettering element (a gettering element) are further formed thereon. A method is disclosed in which a catalyst element is transferred from a lower semiconductor film through a barrier layer to a second semiconductor film and then to a third semiconductor film by performing heat treatment after forming a stacked layer. Then, gettering of the catalytic element is performed by removing the third semiconductor film / second semiconductor film / barrier layer. At this time, in Patent Document 2, a rare gas element is used as a gettering element, and the third semiconductor film contains a rare gas element. In Patent Document 3, one conductivity type impurity (such as phosphorus) is used as a gettering element, and the third semiconductor film contains one conductivity type impurity. In these patent documents, the second semiconductor film is provided, which prevents the gettering element contained in the third semiconductor layer from diffusing into the first semiconductor film crystallized by the catalyst element. It is provided for the purpose of prevention, and may not be provided in some cases.
[0016]
[Patent Document 1]
JP-A-10-64817
[Patent Document 2]
JP-A-2002-246394
[Patent Document 3]
JP-A-2002-246395
[0017]
[Problems to be solved by the invention]
However, the gettering techniques disclosed in Patent Literatures 1 to 3 are not yet satisfactory, and have some problems.
[0018]
First, Patent Document 1 has a fundamental problem that the gettering effect is not sufficient and the residual amount of the catalyst element cannot be sufficiently reduced. The present inventors have actually confirmed that the catalyst element in the crystalline semiconductor film after gettering can be reduced to only about 1/3 of the initial amount by the method described in Patent Document 1. .
The reason is that the diffusion coefficient of the catalytic element (typically nickel) in the oxide film is at least three orders of magnitude smaller than the diffusion coefficient in the semiconductor film. However, the main gettering action is NiCl ₂ And NiF ₂ It is considered that it is vaporized in the form as shown below. Such a reaction system has a certain effect on the film surface, but it is difficult to reduce the catalyst element concentration in the entire semiconductor film. Further, in order to sufficiently promote such a reaction, a high temperature of 1000 ° C. or more is required, and this is not a process that can use a glass substrate.
[0019]
Further, as another problem, in the method of Patent Document 1, the semiconductor film crystallized by the catalytic element is directly thermally oxidized. , The catalyst element is a silicide compound (eg, NiSi ₂ ) Exists locally. Since the silicide compound has a higher oxidation rate with respect to the semiconductor film, oxidation is locally advanced in that region, and there is a problem that pits (small holes) are generated in the semiconductor film at the stage of removing the thermal oxide film. The size of the pit is as large as several μm or more, and the semiconductor layer of the TFT may be disconnected due to this. Therefore, the method of Patent Document 1 has many problems as described above, and in particular, it cannot be implemented at all by a TFT process using a cheap and large glass substrate.
[0020]
On the other hand, when Patent Document 2 or Patent Document 3 is used, it can be confirmed that the concentration of the catalyst element in the semiconductor film can be reduced to 1/1000 or less in the temperature range where the glass substrate can be used. It has a very good gettering ability. However, it was found that there were many problems from the viewpoint of the manufacturing method and the yield.
[0021]
First, problems concerning the film quality, film thickness, and formation method of the barrier layer will be described. The barrier layer is provided for the purpose of an etching stopper of the upper gettering film, and the catalyst element moves to the upper gettering film through the barrier layer. As the barrier layer, an extremely thin oxide film is used. However, since the diffusion of the catalytic element in the oxide film is extremely slow, if the oxide film is dense and thick, the catalytic element cannot move to the upper layer. Conversely, when a porous and thin film is used, it does not function as an etching stopper, and the lower semiconductor film is etched when the upper gettering layer is etched. Since this condition is extremely difficult and requires an unstable state, it cannot be controlled with a sufficient process margin, which causes a large problem in yield. Even if the optimal conditions can be set, the heat treatment conditions for the gettering movement are determined by the barrier layer (oxide film) having the slowest diffusion movement speed, and the gettering distance can be set to the thickness of the semiconductor film. Regardless, a long heat treatment is required.
[0022]
Further, as a second problem, peeling (film peeling) of the gettering layer is very likely to occur. Since the underlying barrier layer is in a half-finished state as a film, it is difficult to enhance the adhesion to the upper gettering layer. If there is a minute hole due to peeling in the gettering layer, the etchant etches the underlying semiconductor film therefrom, and a small hole is also formed in the semiconductor film, which causes a reduction in manufacturing yield. Since dust in the gettering layer also exerts a similar effect, there is a problem in using a sputtered film having high adhesion but a large amount of dust.
[0023]
A third problem is a problem of an etching residue in the etching of the gettering layer. Since a very high selectivity is required between the gettering layer and the barrier layer, a strong alkali solution that is not usually used is used as an etchant.
It is known that the etching of the silicon film by the strong alkali is unstable, and the etching action stops when the oxidizing component increases even a little during the etching, and that the etching rate is largely changed by the fluctuation of the liquid. As a result, in the gettering layer containing a silicon film as a main component, an etching residue is very easily generated. As a countermeasure, if the etching time is extended, the barrier layer is damaged, and the underlying semiconductor layer is also etched, which cannot be solved simply by extending the time. If there is an etching residue of the gettering layer, the channel surface of the TFT semiconductor layer will be formed by the gettering layer in that region, and normal electrical characteristics cannot be expected at all.
[0024]
Therefore, when the technology of Patent Document 2 or Patent Document 3 is used, a high-performance TFT element can be partially produced stochastically, but the manufacturing process margin is extremely small, and as a result, the defect rate increases. Therefore, it is difficult to apply these techniques to mass production of TFT elements.
[0025]
In view of the above problems, an object of the present invention is to provide a highly reliable crystalline semiconductor film in which the content of a catalytic element is sufficiently reduced, and a semiconductor device using the same. Another object of the present invention is to provide a method for easily manufacturing such a semiconductor film without increasing a manufacturing process or manufacturing cost.
[0026]
[Means for Solving the Problems]
The semiconductor film of the present invention is a semiconductor film having a plurality of crystal domains, wherein the plurality of crystal domains are mainly constituted by a region in which a <111> crystal zone plane of a crystal is oriented, and a surface of the semiconductor film is formed. The height is different for each of the plurality of crystal domains, thereby achieving the above object.
[0027]
In a preferred embodiment, 50% or more of the regions where the <111> crystal zone plane is oriented are (110) plane-oriented or (211) plane-oriented regions.
[0028]
It is preferable that the domain diameter of the plurality of crystal domains is 2 μm or more and 10 μm or less.
[0029]
In a preferred embodiment, at least a part of the semiconductor film contains a catalyst element for promoting crystallization of the amorphous semiconductor film.
[0030]
It is preferable that the catalyst element does not precipitate as a compound but exists as a solid solution in the semiconductor film.
[0031]
Preferably, the catalyst element is nickel (Ni), iron (Fe), cobalt (Co), tin (Sn), lead (Pb), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium ( Os), iridium (Ir), platinum (Pt), copper (Cu), and gold (Au).
[0032]
The catalyst element is 1 × 10 ¹⁴ atoms / cm ³ More than 1 × 10 ¹⁷ atoms / cm ³ Preferably, it is contained in at least a part of the semiconductor film at the following concentration.
[0033]
The semiconductor film may be formed with silicon (Si) as a main component.
[0034]
In one preferred embodiment, the catalyst element promotes crystallization of the amorphous semiconductor film by forming a silicide compound.
[0035]
The thickness of the semiconductor film is preferably 25 nm or more and 80 nm or less.
[0036]
The method of manufacturing a semiconductor film according to the present invention includes: (1) a step of preparing a first semiconductor film including a catalytic element for promoting crystallization of an amorphous semiconductor film and having a crystalline region; Providing a second semiconductor film in contact with the first semiconductor film; and (3) performing a first heat treatment on the first semiconductor film to remove the catalyst element present in the first semiconductor film from the first semiconductor film. (2) a step of transferring to the second semiconductor film; (4) a step of oxidizing the second semiconductor film; and (5) a step of removing the oxidized second semiconductor film. The above object is achieved.
[0037]
In a preferred embodiment, the step (1) includes (1a) a step of preparing an amorphous semiconductor film containing the catalyst element, and (1b) performing a second heat treatment on the amorphous semiconductor film. Thereby forming the first semiconductor film.
[0038]
Preferably, between the step (1) and the step (2), a step of removing a natural oxide film formed on a surface of the first semiconductor film is further included.
[0039]
The second semiconductor film is preferably in an amorphous state.
[0040]
It is preferable that the second semiconductor film contains a gettering element that attracts the catalyst element.
[0041]
The gettering element may include at least one rare gas element selected from the group consisting of Ar, Kr, and Xe.
[0042]
The gettering element may include at least one element selected from the group consisting of P, As, and Sb.
[0043]
The gettering element may include at least one element selected from the group consisting of P, As, and Sb, and at least one element selected from the group consisting of B and Al.
[0044]
The step (3) preferably includes a step of performing the first heat treatment while maintaining the amorphous state of the second semiconductor film.
[0045]
The step (4) may include a step of performing a third heat treatment on the second semiconductor film in an oxidizing gas atmosphere.
[0046]
The third heat treatment step may be performed in a high-pressure atmosphere exceeding 1 atm.
[0047]
The third heat treatment step may include a rapid thermal annealing (RTA) for blowing a heated oxidizing gas onto the surface of the second semiconductor film.
[0048]
Water vapor may be used as the oxidizing gas in the third heat treatment step.
[0049]
In a preferred embodiment, the thickness of the second semiconductor film is in a range from 1/10 to 2 times the thickness of the first semiconductor film.
[0050]
In a preferred embodiment, the step (2) includes exposing a surface of the first semiconductor film to a plasma atmosphere containing hydrogen, and exposing the first semiconductor film exposed to the plasma atmosphere to the atmosphere. Forming the second semiconductor film on the first semiconductor film.
[0051]
In a preferred embodiment, in the step (4), in addition to the second semiconductor film, a part of a lower first semiconductor film is also oxidized, and in the step (5), the oxidized second semiconductor film is formed. In addition to the semiconductor film, the oxidized part of the first semiconductor film is also removed.
[0052]
In the step (4), the amount of dangling bonds of semiconductor atoms in the first semiconductor film is preferably reduced.
[0053]
The first heat treatment step of the step (3) and the third heat treatment step of the step (4) may be continuously performed.
[0054]
The first heat treatment and the third heat treatment may be performed simultaneously.
[0055]
The step (5) may include a step of removing the second semiconductor film by wet etching using an acid containing hydrogen fluoride.
[0056]
In a preferred embodiment, the step (1a) includes the step of forming an amorphous semiconductor film, and the step of applying the solution containing the catalyst element to the surface of the amorphous semiconductor film to thereby contain the catalyst element. Forming a first semiconductor film to be formed.
[0057]
Preferably, the step (1a) includes a step of obtaining the amorphous semiconductor film containing the catalyst element by selectively adding the catalyst element to a part of the amorphous semiconductor film. 1b) includes a step of obtaining the first semiconductor film by growing the amorphous semiconductor film in a lateral direction from a region where the catalytic element is selectively added to a peripheral portion thereof.
[0058]
Nickel (Ni), iron (Fe), cobalt (Co), tin (Sn), lead (Pb), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), It is preferable to use at least one element selected from the group consisting of iridium (Ir), platinum (Pt), copper (Cu), and gold (Au).
[0059]
A step of irradiating the first semiconductor film with a laser beam may be performed between the step (1b) and the step (2).
[0060]
Another semiconductor film of the present invention is manufactured by the above-described manufacturing method.
[0061]
The semiconductor device of the present invention is configured using the above-described semiconductor film as an active region.
[0062]
Another semiconductor device of the present invention includes a thin film transistor (TFT) using the above-described semiconductor film as an active region (semiconductor layer).
[0063]
An electronic device according to the present invention includes the above-described semiconductor device.
[0064]
Another electronic device of the present invention includes a display portion including a plurality of pixels, and a display signal is supplied to the plurality of pixels via the above-described semiconductor device.
[0065]
BEST MODE FOR CARRYING OUT THE INVENTION
In the present embodiment, a first step of preparing a first amorphous semiconductor film containing a catalytic element that promotes crystallization of the amorphous semiconductor film, A second heat treatment to form a crystalline semiconductor film; a third step of providing a second semiconductor film so as to be in contact with the crystalline semiconductor film; and a first heat treatment. Performing a fourth step of moving a catalyst element present in the crystalline semiconductor film to the second semiconductor film, a fifth step of oxidizing the second semiconductor film, and a step of oxidizing the second semiconductor film. And a sixth step of removing the second semiconductor film. Here, the crystalline semiconductor film has a reduced catalytic element concentration and can be used later as a semiconductor layer (active region) of a semiconductor device. The second semiconductor film functions as the gettering layer described above.
[0066]
It is preferable to include a step of removing a natural oxide film on the surface of the crystalline semiconductor film between the second step and the third step.
[0067]
That is, in this embodiment, the natural oxide film on the crystalline semiconductor film is removed and the second semiconductor layer is provided so as to be in contact with the crystalline semiconductor film without providing the barrier layer which has been a problem in the conventional method. Thus, the problem in the barrier layer can be solved, the catalyst element can be smoothly moved to the gettering layer (the second semiconductor film), the gettering ability can be increased, and the heat treatment time for gettering can be shortened. . In addition, even when the second semiconductor film as the upper layer is formed, the adhesion to the lower layer is increased, and the condition margin in which peeling does not occur is significantly increased. Then, by oxidizing and removing the gettering layer (second semiconductor film), selective etching without unevenness can be performed, and a problem of an etching residue which becomes a problem when the above-described etching with a strong alkali is used. Does not occur.
[0068]
In addition, since the catalyst element is transferred to the gettering layer and the gettering layer is oxidized and removed, the oxidation step after the catalyst element concentration in the lower crystalline semiconductor film is sufficiently reduced is performed. Thus, there is no problem associated with oxidation (low gettering ability or small holes due to local oxidation of silicide) as described in Patent Document 1. In addition, since the oxidation step is intended only for the oxidation, not for the reaction by the halogen element, the treatment can be performed in a temperature range where the glass substrate can be used.
[0069]
In this embodiment, the second semiconductor film serving as the gettering layer is preferably in an amorphous state. Then, in the fourth step, the first heat treatment is preferably performed while maintaining the amorphous state of the second semiconductor film.
[0070]
Further, the second semiconductor film preferably contains a gettering element having an effect of attracting a catalytic element. The gettering element is, for example, one or more rare gas elements selected from Ar, Kr, and Xe. Alternatively, the gettering element may be one or more elements belonging to Group 5 B of the periodic table selected from P, As, and Sb. Alternatively, as the gettering element, one or more kinds of elements belonging to Group 5B of the periodic table selected from P, As, and Sb, and one or more kinds of elements belonging to Group 3B of the periodic table selected from B and Al Can be used together.
[0071]
The mechanism of the movement of the catalyst element by gettering is to increase the segregation coefficient of the catalyst element in the gettering layer and to use the force to move the catalyst element from the lower crystalline semiconductor film. In the lower crystalline semiconductor film crystallized by the catalytic element, not all exist in a solid solution state in the semiconductor film, but most of the crystalline semiconductor film is precipitated as a semiconductor compound. The diffusion and transfer of nickel to the gettering layer below the solid solubility of the catalytic element in the semiconductor film, causing the semiconductor compound of the catalytic element deposited in the crystalline semiconductor film to form a solid solution and disappear. Gettering is performed.
[0072]
As a mechanism for increasing the segregation coefficient of the catalyst element in the gettering layer at this time, an action of increasing the solid solubility for the catalyst element from that of the lower semiconductor film and moving the catalyst element there (first gettering action); There is a function (second gettering function) of forming a defect or a local segregation site that traps the catalyst element and moving and trapping the catalyst element there. As described above, the effect of the second gettering action can be obtained by setting the second semiconductor film serving as the gettering layer in an amorphous state. By performing the first heat treatment for gettering movement while maintaining the amorphous state of the second semiconductor film, the gettering layer can maintain high gettering ability over the entire period of the heat treatment. As a result, the concentration of the catalytic element in the lower crystalline semiconductor layer can be further reduced. If the gettering layer is crystallized during this heat treatment, the gettering action thereafter becomes small, and the catalyst element once moved may flow back.
[0073]
In addition, the first or second gettering action can be further enhanced by including a gettering element having a gettering effect in the second semiconductor film which is a gettering layer. At this time, it is known that the action differs depending on the type and combination of the gettering elements.
[0074]
When one or more rare gas elements selected from Ar, Kr, and Xe are used as the gettering elements, a large interstitial distortion occurs in a place where these rare gas elements are present in the gettering layer, resulting in a defect. -The second gettering action by the segregation site works very strongly. At this time, the concentration of the rare gas element contained in the gettering layer is 1 × 10 ¹⁹ atoms / cm ³ 3 × 10 or more ²¹ atoms / cm ³ Within the following range, sufficient gettering efficiency can be obtained.
[0075]
When one or more elements belonging to Group V of the periodic table B selected from P, As, and Sb are used as the gettering elements, the solid solubility of the gettering layer with respect to the catalytic element increases, That is, the gettering is moved using the above-described first gettering action. Among these elements, phosphorus is particularly effective. At this time, the concentration of these impurity elements contained in the gettering layer is 1 × 10 ¹⁹ atoms / cm ³ More than 1 × 10 ²¹ atoms / cm ³ When the concentration is within the following range, a sufficient gettering efficiency can be obtained.
[0076]
Further, in addition to one or more kinds of elements belonging to Group 5 of the Periodic Table B selected from P, As, and Sb as the gettering elements, one or more kinds of Periodic Table 3 selected from B and Al are added. It is known that when the element belonging to Group B is used together, only the element belonging to Group V has a gettering ability. However, when the element belonging to Group B is also introduced, a larger gettering effect can be obtained. . If the gettering layer contains, for example, not only phosphorus but also boron, the gettering mechanism changes, and in the case of only phosphorus, diffusion transfer utilizing the difference in solid solubility of the catalytic element with the underlying crystalline semiconductor film. Although the gettering is the type gettering (the first gettering action described above), the inclusion of boron additionally makes it easier for the catalyst element to be precipitated in the gettering layer, and the gettering to defects or segregation sites (described above). Of the second gettering effect) becomes dominant, and the effect is synergistically enhanced. At this time, the concentration of the impurity element contained in the gettering layer is 1 × 10 5 ¹⁹ atoms / cm ³ More than 1 × 10 ²¹ atoms / cm ³ The following concentration, the element belonging to Group 3 B of the periodic table is 1.5 × 10 ¹⁹ atoms / cm ³ 3 × 10 or more ²¹ atoms / cm ³ It is desirable that the concentration be within the following range, and within this range, high gettering efficiency can be obtained.
[0077]
In the present embodiment, in the third step of providing the second semiconductor film to be a gettering layer, the surface of the lower crystalline semiconductor film is exposed to a plasma atmosphere containing hydrogen and then exposed to the atmosphere. Preferably, the second semiconductor film is formed over the crystalline semiconductor film. Even after the treatment with hydrofluoric acid, a slight natural oxide film is formed on the surface of the lower crystalline semiconductor film due to the residence time and the like. If the gettering layer is formed in such a state, it causes peeling of the gettering layer and lowers the gettering efficiency. Therefore, in order to completely remove the natural oxide film, it is effective to expose the gettering layer to a plasma atmosphere containing hydrogen before forming the gettering layer, whereby the natural oxide film is removed by etching. In addition, since the process is a plasma process, the gettering layer can be continuously formed without being exposed to the air.
[0078]
Next, the fifth step in this embodiment can be performed by performing a third heat treatment on the second semiconductor film in an oxidizing gas atmosphere. At this time, the third heat treatment in an oxidizing gas atmosphere is preferably performed in a high-pressure atmosphere exceeding 1 atm. Alternatively, the third heat treatment in an oxidizing gas atmosphere may be performed by rapid thermal annealing (RTA) in which a heated oxidizing gas is blown onto the surface of the second semiconductor film. Further, it is preferable to use steam as the oxidizing gas in the third heat treatment.
[0079]
In the present embodiment, since the purpose is to oxidize and remove the second semiconductor film that is the gettering layer, it is necessary to oxidize at least the entire second semiconductor film. The thickness of the second semiconductor film in this embodiment is preferably in the range of 1/10 to 2 times the thickness of the first amorphous semiconductor film (crystalline semiconductor film). The thickness of the first amorphous semiconductor film in the present embodiment is desirably in the range of 25 nm or more and 80 nm or less from the viewpoint of crystal growth. In the layer, the gettering ability required in the present embodiment can be secured. If it is twice or less, it is possible to suppress the etching damage and the non-uniform film reduction of the lower crystalline semiconductor film at the time of removal by oxidation to the extent that there is no problem. However, more preferably, the thickness of the second semiconductor film is 1/5 or more and equal to or less than 1 times the thickness of the first amorphous semiconductor film, and is substantially 10 nm or more and 50 nm or less.
[0080]
That is, in the present embodiment, it is necessary to oxidize the second semiconductor film having a certain thickness in such a range. desirable. However, at this time, in consideration of the heat resistance of the glass substrate, it is not possible to use a thermal oxidation method of performing treatment at a high temperature as in the conventional method.
[0081]
In this embodiment, by performing the thermal oxidation treatment in a high-pressure oxidizing gas atmosphere exceeding 1 atm, the reactivity of the oxidizing gas can be increased, and the thermal oxidation can be performed at a lower temperature in a shorter time. The rate of the oxidation reaction at this time increases in proportion to the pressure, and therefore it is desirable to set the rate higher. However, there is a safety problem in the production apparatus, and the oxidation reaction rate is in the range of 5 to 15 atm. It is desirable. Further, as the heat treatment conditions in this case, it is desirable that the temperature is 550 ° C. or more and 600 ° C. or less and the treatment time is about 10 minutes or more and 2 hours or less.
[0082]
Further, as another thermal oxidation method in this embodiment, it is also effective to use rapid thermal annealing (RTA) in which a heated oxidizing gas is blown onto the surface of the second semiconductor film. In this method, the temperature of the entire substrate is instantaneously raised to a high temperature region having high oxidation reactivity, and an oxidizing gas heated to a high temperature is directly blown onto the surface of the gettering layer, thereby performing a necessary oxidation process in a short time. I can do it. After that, the temperature can be rapidly lowered, so that the processing can be performed without causing significant thermal deformation of the glass substrate. The heat treatment conditions at this time are preferably a temperature of 650 ° C. or more and 800 ° C. or less, and a treatment time of about 5 minutes or more and 20 minutes or less. In this case, it is preferable that the rate of temperature rise and the rate of temperature fall are both 100 ° C./min or more.
[0083]
In the two thermal oxidation methods of the present embodiment described above, the oxidizing gas used is required to have high oxidation reactivity, and for this reason, steam is most desirable. Besides, ozone gas or the like can be used.
[0084]
In the present embodiment, in the fifth step of oxidizing the second semiconductor film, in addition to the second semiconductor film, a part of the underlying semiconductor film having crystallinity may be oxidized. In this case, in the sixth step of removing the oxidized second semiconductor film, in addition to the oxidized second semiconductor film, a part of the oxidized crystalline semiconductor film may be removed. it can. That is, oxidation may partially progress not only in the second semiconductor film serving as the gettering layer but also in the lower crystalline semiconductor film. In this case, by removing the oxidized portion, not only the gettering layer but also the layer near the surface of the lower crystalline semiconductor film is removed, and the film thickness becomes smaller than the initial thickness.
[0085]
The gettering layer and the lower crystalline semiconductor layer both have the same semiconductor component, and there is almost no difference in oxidation rate. As described above, by keeping the second semiconductor film, which is the gettering layer, in an amorphous state, the difference in structure between crystalline and amorphous (the oxidation rate is higher in the amorphous state). Such a state is useful because a certain degree of difference in the oxidation rate can be obtained by utilizing this. However, it is more important that the gettering layer remains on the crystalline semiconductor film without being completely removed due to insufficient oxidation. Therefore, the oxidation treatment is performed on the entire second semiconductor film and on the lower layer. It is desirable to proceed to the upper part of the crystalline semiconductor film from the viewpoint of a manufacturing process margin.
[0086]
In the present embodiment, in the fifth step of oxidizing the second semiconductor film, it is possible to reduce the amount of dangling bonds of the semiconductor atoms in the underlying semiconductor film having crystalline properties. That is, in the step of oxidizing the second semiconductor film, excess semiconductor atoms in the second semiconductor film are diffused into the underlying crystalline semiconductor film and combined with dangling bonds. That's why it is terminated. As described above, in the present embodiment, the function of improving the crystallinity of the crystalline semiconductor film can be performed together with gettering.
[0087]
In this embodiment, the first heat treatment and the third heat treatment for oxidizing the second semiconductor film are preferably performed continuously. By doing so, the second and third heat treatments become substantially one heat treatment, which is advantageous not only in shortening the manufacturing process and improving the tact time of the manufacturing apparatus, but also when performing the steps separately. In comparison, dust adhering between steps can be eliminated, and the production yield can be improved. Furthermore, by performing the first heat treatment and the third heat treatment for oxidizing the second semiconductor film as one heat treatment at the same time, the total heat treatment time can be further reduced. The process can be simplified and the takt time of the manufacturing apparatus can be improved.
[0088]
In this embodiment, the sixth step of removing the oxidized second semiconductor film can be performed by wet etching using an acid containing hydrogen fluoride. By using such a method, a high etching selectivity can be obtained between the oxidized semiconductor film and the underlying crystalline semiconductor film, and a reduction in the thickness of the crystalline semiconductor film due to over-etching and a variation in the thickness due to the over-etching can be prevented. Can be reduced. In addition, the surface of the lower crystalline semiconductor film is an important surface for forming a channel surface in the semiconductor device. However, in a wet method, a favorable state can be maintained without etching damage caused by plasma or the like.
[0089]
In the present embodiment, the first step of preparing a first amorphous semiconductor film containing a catalyst element is to form an amorphous semiconductor film and apply a solution containing the catalyst element thereon. It is preferable to perform this. In this embodiment, the concentration of the catalytic element added to the first amorphous semiconductor surface is 1 × 10 ¹¹ atoms / cm ² More than 1 × 10 ¹⁴ atoms / cm ² Or less, which is 1/100 or less the concentration of the catalyst atom monoatomic layer. On the other hand, when the first amorphous semiconductor film is prepared by applying a solution containing a catalyst element to the amorphous semiconductor film, the surface of the amorphous semiconductor film is adjusted by adjusting the concentration of the catalyst element in the solution. It is possible to control the concentration of the added catalyst element with a very small amount in a controlled manner.
[0090]
In the present embodiment, typically, the first step of preparing a first amorphous semiconductor film containing a catalyst element includes selectively adding a catalyst element to a part of the amorphous semiconductor film. In the second step of subjecting the amorphous semiconductor film to the second heat treatment, the crystal is grown laterally from the region where the catalytic element is selectively added to the periphery thereof, whereby the crystal is formed. A semiconductor film having quality is obtained. By doing so, in the region where the crystal has grown in the lateral direction, it is possible to obtain a good crystalline semiconductor film in which the crystal growth directions are substantially aligned in one direction, and it is possible to further enhance the current driving capability of the TFT. is there. Further, in the region where the crystal is grown in the lateral direction, the concentration of the catalyst element in the film after the crystal growth can be reduced by one to two orders of magnitude compared to the region where the catalyst element is directly added, so that the load of the gettering step is reduced. can do.
[0091]
Furthermore, in this embodiment, after the second step, a step of irradiating the semiconductor film having a crystalline property with laser light may be performed. When the crystalline semiconductor film obtained in this embodiment is irradiated with a laser beam, a difference in melting point between the crystalline portion and the amorphous portion causes a grain boundary portion or a minute residual amorphous region (uncrystallized region). Is intensively processed. The crystalline semiconductor film crystallized by introducing a catalytic element is formed of columnar crystals, and the inside thereof is in a single crystal state. Therefore, when the crystal grain boundary portion is processed by laser light irradiation, the single crystal is formed over the entire surface of the substrate. A high-quality crystalline semiconductor film close to a crystalline state is obtained, and the crystallinity is greatly improved. As a result, the ON characteristics of the TFT are greatly improved, and a semiconductor device having better current driving capability can be realized.
[0092]
Here, in the present embodiment, nickel (Ni), iron (Fe), cobalt (Co), tin (Sn), lead (Pb), ruthenium (Ru), rhodium (Rh), palladium are preferable catalyst elements. One or more elements selected from (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), and gold (Au) are used. One or a plurality of elements selected from these elements have an effect of promoting crystallization in a trace amount. Among them, the most remarkable effect can be obtained particularly when Ni is used. The catalyst element does not act alone, but acts on crystal growth by bonding to the silicon film to form silicide. The crystal structure at that time acts as a kind of template when the amorphous silicon film is crystallized, and promotes the crystallization of the amorphous silicon film. Ni is two Si and NiSi ₂ To form NiSi ₂ Shows a fluorite type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, NiSi ₂ Has a lattice constant of 0.5406 nm (5.406 angstroms), which is very close to the lattice constant of 0.5430 nm (5.430 angstroms) in the diamond structure of crystalline silicon. Therefore, NiSi ₂ Is optimal as a template for crystallizing an amorphous silicon film, and it is most desirable to use Ni as the catalyst element in the present embodiment.
[0093]
Next, features of the semiconductor film according to the present embodiment will be described. As a result of manufacturing the semiconductor film of the present embodiment using such a manufacturing method, the semiconductor film of the present embodiment has a semiconductor film having a region composed of a plurality of crystal domains (substantially the same crystal plane orientation region). The plane orientation of the crystal domains is mainly constituted by the <111> crystal zone plane, and a height difference (irregularity) occurs between the crystal domains on the film surface. That is, the height of the surface of the semiconductor film differs depending on each of the crystal domains.
[0094]
Further, among the <111> crystal zone planes, the (110) plane orientation and the (211) plane orientation occupy 50% or more of the entire crystal domain plane orientation. In addition, the domain diameter of the crystal domain is typically 2 μm or more and 10 μm or less.
[0095]
Further, in the semiconductor film of this embodiment, a catalyst element that promotes crystallization of the amorphous semiconductor film is included in the semiconductor film. Here, the catalyst element contained in the semiconductor film typically does not precipitate as a compound but exists in a solid solution state.
[0096]
At this time, the catalyst element contained in the semiconductor film of this embodiment is preferably nickel (Ni), iron (Fe), cobalt (Co), tin (Sn), lead (Pb), ruthenium ( One or more elements selected from the group consisting of Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), and gold (Au) It is. Here, in the semiconductor film of this embodiment, the catalyst element contains 1 × 10 ¹⁴ atoms / cm ³ More than 1 × 10 ¹⁷ atoms / cm ³ It is preferably present at the following concentrations:
[0097]
Further, the semiconductor film of the present embodiment can be formed from a material containing silicon (Si) as a main component. Further, the compound of the catalyst element may be silicide.
[0098]
Further, the thickness of the semiconductor film of the present embodiment is preferably in the range of 25 nm to 80 nm.
[0099]
Generally, in crystallization without using a catalytic element, the plane orientation of a crystalline semiconductor film is (100) due to the influence of an insulator under a semiconductor film (especially in the case of amorphous silicon dioxide) or the influence of the semiconductor film surface. Or it is easy to turn to (111). On the other hand, FIG. 7A shows a schematic diagram of crystallization in the case where a catalyst element is added to an amorphous semiconductor film and crystallized. In FIG. 7A, 61 is a base insulator, 62 is an amorphous semiconductor film in an uncrystallized region, 63 is a crystalline semiconductor film, and 64 is a semiconductor compound of a catalytic element serving as a driving force for crystal growth. is there. As shown in FIG. 7A, the catalytic element compound 64 exists at the forefront of crystal growth, and the adjacent amorphous regions 62 are successively crystallized rightward on the paper. The catalyst element compound 64 has a property of growing strongly in the <111> direction. As a result, as the plane orientation of the obtained crystalline semiconductor film, a <111> crystal plane appears as shown in FIG.
[0100]
Further, the crystal structure at this time is composed of a plurality of columnar crystals positioned at the tip of the catalyst element compound, and the cross-sectional shape of each columnar crystal is 80 nm square in a stress-free state. That is, when the thickness of the semiconductor film is 80 nm or less, the semiconductor film is formed of a single-layer columnar crystal in the thickness direction. However, when the thickness is more than 80 nm, the crystal has a two-layer structure, and the crystallinity deteriorates. Therefore, the thickness of the semiconductor film is desirably 80 nm or less. Conversely, it has been found that when the thickness of the semiconductor film is extremely thin (25 nm or less), crystal growth hardly occurs.
[0101]
FIG. 7B shows a <111> crystal zone plane. In FIG. 7B, the horizontal axis represents the inclination angle from the (-100) plane, and the vertical axis represents the surface energy. Group 65 is a crystal plane to be a <111> crystal zone plane. The (100) plane and the (111) plane are not <111> zone planes, but are shown for comparison. FIG. 7C shows a standard triangle of the crystal orientation. Here, the distribution of the <111> crystal zone plane is as shown by a broken line. The numbers are representative pole indices. Among these <111> crystal zone planes, in the crystalline semiconductor film obtained in the present embodiment, especially the (110) plane or the (211) plane has a dominant orientation, and when these planes occupy 50% or more of the whole. The advantage is obtained. These two crystal planes have extremely high hole mobility as compared with the other planes, so that the performance of a P-channel TFT, which is inferior to that of an N-channel TFT, can be particularly improved, and a balance can be easily achieved in a semiconductor circuit. There are benefits.
[0102]
FIG. 8 shows the plane orientation distribution of the crystalline semiconductor film obtained according to the present embodiment. FIG. 8 shows the results of EBSP (Electron Backscattered Diffraction Pattern) measurement, in which crystal orientations are specified for individual micro regions, and the crystal orientations are connected and mapped. FIG. 8A shows the plane orientation distribution in the crystalline semiconductor film of the present embodiment. FIG. 8B shows the distribution between the adjacent mapping points based on the data shown in FIG. Those in which the inclination of the plane orientation is equal to or smaller than a predetermined value (here, equal to or smaller than 5 °) are painted in the same color to highlight the distribution of individual crystal domains. FIG. 8C shows the standard triangle of the crystal orientation described earlier with reference to FIG. 8C. As can be seen from FIG. 8C, the crystalline semiconductor film according to the present embodiment generally has a plane orientation on the <111> zone plane, and is particularly strongly oriented to (110) and (211). You can see that In this embodiment, the nucleation density is increased by the action of the rare gas element contained in the semiconductor film, and the size of each crystal domain (substantially the same plane orientation region) shown in FIG. 8B is 2 μm or more. It is distributed in a range of 10 μm or less.
[0103]
Here, in the semiconductor film of the present embodiment, a gettering layer exists as an upper layer, and gettering is performed by oxidizing and removing the gettering layer. At this time, as described above, it is difficult to selectively oxidize and remove only the upper gettering layer, and the surface layer of the lower crystalline semiconductor film is also partially oxidized and removed together. It is preferable from the viewpoint of margin. Therefore, it is desirable that the film surface is also oxidized and removed to some extent in the semiconductor film of the present embodiment. At this time, in the crystalline semiconductor film, since the oxidation rate differs depending on the plane orientation, a difference occurs in the oxidation rate between the crystal domains which are the same plane region. As a result, in the semiconductor film of the present embodiment, the oxidation amount differs between the crystal domains on the film surface. Then, after being removed, a height difference (irregularity) occurs between the respective crystal domains, which is one feature of the semiconductor film of the present embodiment. The height difference between the domains at this time depends on how much the surface layer of the crystalline semiconductor film is oxidized (how much a manufacturing margin is taken), but is preferably in the range of 1 nm to 20 nm.
[0104]
In addition, since the semiconductor film of the present embodiment is obtained by introducing a catalyst element into an amorphous semiconductor film and crystallizing the same, even if gettering is performed, the concentration of the catalyst element in the semiconductor film is completely maintained. However, there is a small amount of the remaining catalytic element. However, it is the catalytic element semiconductor compound that acts as a nucleus during crystal growth and drives the crystal growth that adversely affects the electrical characteristics of the semiconductor device. These semiconductor compounds exist locally segregated. However, in the semiconductor film obtained in the present embodiment, the semiconductor compounds are obtained by solid solution in the crystalline semiconductor film and moved by gettering. The catalyst element is not precipitated as a compound but exists in a solid solution state. At this time, the concentration of the catalyst element in the semiconductor film is 1 × 10 ¹⁴ atoms / cm ³ More than 1 × 10 ¹⁷ atoms / cm ³ Less than, 1 × 10 ¹⁷ atoms / cm ³ If it is below, the semiconductor compound of the catalytic element which does not adversely affect the electrical characteristics of the semiconductor device is not deposited. Also, 1 × 10 ¹⁴ atoms / cm ³ Is the lower limit at which the catalyst element concentration can be reduced by the gettering treatment.
[0105]
Hereinafter, an embodiment of a semiconductor film and a method for manufacturing the same according to the present invention will be described with reference to FIG.
[0106]
(1st Embodiment)
Here, a method for manufacturing a semiconductor film according to the present invention on a glass substrate will be described. The semiconductor thin film of the present embodiment can be used for an active region of a TFT, a PN junction diode, and the like. FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor thin film described here, and the manufacturing process sequentially proceeds in the order of (A) → (G).
[0107]
In FIG. 1A, a low alkali glass substrate or a quartz substrate can be used as a substrate 101. In this embodiment, a low alkali glass substrate is used. In this case, heat treatment may be performed in advance at a temperature about 10 ° C. to 20 ° C. lower than the glass strain point. A base film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on a surface of the substrate 101 on which a semiconductor film is formed in order to prevent impurity diffusion from the substrate 101. In the present embodiment, for example, a silicon oxynitride film formed from a material gas of SiH4, NH3, and N2O by a plasma CVD method is formed as the lower first base film 102, and a plasma CVD method is similarly formed thereon. A second underlayer 103 was formed using SiH4 and N2O as material gases. At this time, the thickness of the silicon oxynitride film of the first base film 102 is from 25 nm to 200 nm (for example, 100 nm), and the thickness of the silicon oxynitride film of the second base film 103 is from 25 nm to 300 nm (for example, 100 nm). ). In the present embodiment, a two-layer base film is used. However, a single-layer structure composed of only a silicon oxide film can be used.
[0108]
Next, an intrinsic (I-type) amorphous silicon film (a-Si film) 104 having a thickness of 25 nm to 80 nm (eg, 50 nm) is formed by a plasma CVD method. In the present embodiment, a multi-chamber parallel plate type plasma CVD apparatus is used to continuously form three layers of a first base film 102, a second base film 103, and an a-Si film 104 without exposing them to the atmosphere. Filmed. By doing so, contamination and adhesion of dust at the film interface can be suppressed as much as possible. Of course, the formation of the base films 102 and 103 and the a-Si film 104 is not limited to the above-described plasma CVD method, and other known methods such as a thermal CVD method and a sputtering method can also be used. As the semiconductor film, it is preferable to use a film containing silicon as a main component in terms of ease of handling and characteristics as a semiconductor device. Alternatively, a germanium film or the like can be used. Further, the thickness of the a-Si film 104 is preferably in the range of 25 nm to 80 nm from the viewpoint of crystal growth.
[0109]
Subsequently, a catalytic element is added to the a-Si film 104 and heat treatment is performed. An aqueous solution (aqueous nickel acetate solution) containing, for example, 10 ppm by weight of a catalytic element (nickel in this embodiment) is applied to the a-Si film by spin coating to form a catalytic element-containing layer 105. The catalyst element usable here is selected from the group consisting of nickel (Ni), cobalt (Co), tin (Sn), lead (Pb), palladium (Pd), iron (Fe), and copper (Cu). One or more elements are preferred. Besides, ruthenium (Ru), rhodium (Rh), osmium (Os), iridium (Ir), platinum (Pt), gold (Au) and the like can be used. Prior to this step, the surface of the a-Si film 104 may be slightly oxidized with ozone water or the like to improve the wettability of the surface of the a-Si film 104 during spin coating.
[0110]
In the present embodiment, a method of adding nickel by a spin coating method is used. However, a thin film made of a catalytic element (a nickel film in the case of the present embodiment) is formed on the a-Si film 104 by an evaporation method, a sputtering method, or the like. Means for forming may be used. This state corresponds to the state shown in FIG. The nickel concentration on the surface of the a-Si 104 thus added in the state of FIG. 1A was measured by a total reflection X-ray fluorescence (TRXRF) method. ¹² atoms / cm ² It was about. At this time, the concentration of nickel added to the a-Si film surface was 1 × 10 ¹¹ atoms / cm ² More than 1 × 10 ¹⁴ atoms / cm ² It is desirable that: Since this concentration is 1/100 or less of the nickel atomic layer, the added nickel is discretely present on the a-Si film, and is not actually in a film state.
[0111]
Then, this is subjected to a second heat treatment in an inert atmosphere, for example, in a nitrogen atmosphere. This heat treatment is preferably performed at a temperature of 530 ° C. to 620 ° C. and a heating time of 30 minutes to 8 hours. In the present embodiment, as an example, the heat treatment is performed at 580 ° C. for one hour. In this heat treatment, the nickel 105 added to the surface of the a-Si film first diffuses into the a-Si film 104, and subsequently, they are aggregated and silicidation occurs. Crystallization proceeds. As a result, the a-Si film 104 is crystallized to become a crystalline silicon film 104a. Here, the heat treatment was performed using a general furnace. However, an RTA (Rapid Thermal Annealing) apparatus using a lamp or the like as a heat source, an RTA apparatus by inserting a substrate into the furnace in a single wafer, or a high temperature. The heat treatment may be performed using an RTA apparatus or the like in which a heated inert gas is blown onto the substrate surface. When such an RTA method is used, it is preferable to perform heat treatment at a temperature of 650 ° C. or more and 750 ° C. or less for 30 seconds or more and 10 minutes or less. When the crystal plane orientation of the crystalline silicon film 104a thus obtained is examined by EBSP measurement, it is mainly composed of the <111> zone plane, and among them, the (110) plane orientation and the (211) plane orientation are particularly preferable. Occupies more than 50% of the total area. The domain diameter of the crystal domain (substantially the same plane orientation region) is 2 μm or more and 10 μm or less. This state corresponds to FIG.
[0112]
Subsequently, as shown in FIG. 1C, the crystalline silicon film 104a obtained by the heat treatment is irradiated with a laser beam 106, whereby the crystalline silicon film 104a is further recrystallized to improve crystallinity. The formed crystalline silicon film 104b is formed. As the laser beam at this time, a XeCl excimer laser (wavelength 308 nm) or a KrF excimer laser (wavelength 248 nm) can be used. The beam size of the laser beam at this time is molded so as to have a long shape on the surface of the substrate 101, and the entire surface of the substrate is recrystallized by sequentially performing scanning in a direction perpendicular to the long direction. .
At this time, by scanning so that a part of the beam overlaps, laser irradiation is performed a plurality of times at any one point of the crystalline silicon film 104a, and the uniformity can be improved. If the energy of the laser beam at this time is too low, the effect of improving the crystallinity is small, and if it is too high, the crystalline state of the crystalline silicon film 104a obtained in the previous step disappears. There is. In addition, as a laser that can be used at this time, a pulse oscillation type or continuous emission type KrF excimer laser, XeCl excimer laser, YAG laser, or YVO4 laser can be used. The crystallization conditions may be appropriately selected by the practitioner.
[0113]
In this embodiment, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) is used. The irradiation conditions of the laser beam are as follows: nitrogen atmosphere, energy density 300 mJ / cm ² More than 500mJ / cm ² The following (for example, 420 mJ / cm ² ). The beam size was formed to be a long shape of 150 mm × 1 mm on the surface of the substrate 101, and scanning was sequentially performed in a direction perpendicular to the long direction with a step width of 0.05 mm. That is, laser irradiation is performed a total of 20 times at any one point of the crystalline silicon film 104a.
[0114]
In this manner, the crystalline silicon film 104a obtained by solid-phase crystallization is reduced in crystal defects by a melt-solidification process by laser irradiation, and becomes a higher-quality crystalline silicon film 104b. Note that, even after the laser irradiation step, the crystal plane orientation and the crystal domain state before the laser irradiation are maintained as they are, and no significant change is observed in the EBSP measurement.
[0115]
Next, the crystalline silicon film 104b is washed with an acid containing hydrogen fluoride to remove a natural oxide film on the surface. Then, as shown in FIG. 1D, the crystalline silicon film 104b is directly in contact with the crystalline silicon film 104b. The gettering layer 107 is formed. At this time, since a natural oxide film may be re-formed on the surface of the crystalline silicon film 104b after the cleaning with hydrofluoric acid, the gettering layer 107 can be formed immediately after the cleaning with hydrofluoric acid. desirable. If a natural oxide film of a certain degree or more is present on the crystalline silicon film 104b, it may cause peeling of the gettering layer 107 and lower the gettering efficiency.
[0116]
Here, the gettering layer 107 is desirably in an amorphous state, and desirably contains an element having a gettering effect. In this embodiment, some typical methods for forming the gettering layer 107 will be described. First, when an a-Si film containing a rare gas element (Ar in this embodiment) is used as the gettering layer 107, a sputtering method or a plasma CVD method can be used. In the case of the sputtering method, an amount of Ar necessary for gettering can be contained by using a silicon target and using a sputtering gas of Ar. In plasma CVD, SiH ₄ The gas and the Ar gas are used as materials, and the Ar concentration in the a-Si film to be formed increases in a direction in which both the film forming temperature and the film forming pressure are reduced. To further increase the Ar concentration, an a-Si film can easily contain an Ar element by using a dual-bias or dual-frequency plasma CVD apparatus that applies another bias to the substrate side. In the present embodiment, as an example, an a-Si film containing Ar having a thickness of 20 nm is formed using a general plasma CVD apparatus at a deposition temperature of 250 ° C. and a deposition pressure of about 20 Pa. At this time, the Ar concentration in the a-Si film was 5 × 10 ¹⁹ atoms / cm ³ It was about. Further, other than Ar, Kr and Xe can be similarly used. The concentration of the rare gas element contained in the gettering layer is 1 × 10 ¹⁹ atoms / cm ³ 3 × 10 or more ²¹ atoms / cm ³ It is preferable to be within the following range.
[0117]
Secondly, when an a-Si film containing an element belonging to Group 5B of the periodic table (P in the present embodiment) is used as the gettering layer 107, silane (SiH ₄ ) And phosphine (PH ₃ ) Is formed as a material gas, whereby an a-Si film containing P can be easily obtained. At this time, the content of P in the a-Si film is PH ₃ Gas and SiH ₄ It can be controlled by the flow ratio with gas. In addition to P, As and Sb can be used, and the concentration of these elements contained in the gettering layer is 1 × 10 ¹⁹ / Cm ³ More than 1 × 10 ²¹ / Cm ³ It may be within the following range.
[0118]
Third, as the gettering layer 107, in addition to the element belonging to Group 5B of the periodic table (P in the present embodiment), an element belonging to Group B in the periodic table (B in the present embodiment) is contained. By using the a-Si film, the gettering ability can be further enhanced. In this case, the two types of diborane (B ₂ H ₆ ) Can be added. And PH ₃ Gas and SiH ₄ Gas and B ₂ H ₆ The content of P and B in the a-Si film can be similarly controlled by the flow ratio with the gas. At this time, in addition to B, Al can be used, and the concentration of these elements contained in the gettering layer is 1.5 × 10 ¹⁹ / Cm ³ 3 × 10 or more ²¹ / Cm ³ It may be within the following range.
[0119]
Before the formation of the gettering layer 107, it is desirable to perform a plasma treatment on the surface of the crystalline silicon film 104b in an atmosphere containing hydrogen, and then to form the film continuously. When a gettering layer is formed by a plasma CVD apparatus as in the present embodiment, hydrogen plasma processing can be easily performed only by switching the material gas, and thereafter, the gettering layer is continuously formed without being exposed to the air. Film formation can be performed.
[0120]
The thickness of the gettering layer 107 is desirably in the range of 1/10 to 2 times the thickness of the crystalline silicon film 104b, and optimally 1/5 to 1 times. In the present embodiment, since the thickness of the crystalline silicon film is set to 50 nm, the thickness of the gettering layer is desirably 5 nm or more and 100 nm or less, and most preferably 10 nm or more and 50 nm or less. In the present embodiment, the thickness of the gettering layer 107 is set to 20 nm.
[0121]
Then, this is subjected to a first heat treatment under an inert atmosphere. As a heat treatment method at this time, general furnace annealing and rapid thermal annealing (RTA) can be used. At this time, in the case of furnace annealing, at a temperature of 500 ° C. or more and 600 ° C. or less, 15 minutes or more and 4 hours or less, and in the case of RTA, at a temperature of 600 ° C. or more and 750 ° C. or less, about 30 seconds or more and 15 minutes or less. May be performed. In the present embodiment, for example, the RTA process is performed in a nitrogen atmosphere. The condition of the RTA at this time is as follows: from a state where the substrate is preheated to about 400 ° C., the temperature is raised at a rate of 50 ° C./min to 300 ° C./min. Was done. In the present embodiment, the RTA processing of the above temperature profile is realized by providing a temperature gradient in the furnace using a resistive heating furnace and controlling the speed at which the substrate is inserted into the furnace. At this time, the substrates are processed one by one, and during the processing, a high-temperature heated nitrogen gas is uniformly sprayed on the surface of the substrate 101, so that a high-speed heating rate that cannot be obtained only by heat radiation and a high- The uniformity in the substrate surface is obtained.
[0122]
FIG. 9 shows the configuration of the RTA apparatus used in this embodiment. A heater 803 is provided for each zone above the quartz tube 802. 804 is a quartz shower plate, and 805 is a substrate stage. The substrate stage 805 supports the substrate 801 by pin support, so that heat exchange from the substrate is eliminated and instantaneous heating can be performed only by the heat capacity of the substrate 801. The substrate stage 805 is supported by a support flange 806, and is heated by moving up and down as indicated by an arrow 809. Reference numeral 807 denotes an O-ring for sealing the chamber. Nitrogen gas 808 is introduced from the upper part of the quartz tube, diffuses and heats in the reservoir on the shower plate 804, and is uniformly sprayed on the surface of the substrate 801 through the shower plate. The lifting speed of the substrate 801 is controlled by the vertical speed (indicated by an arrow 809) of the substrate stage.
[0123]
By this heat treatment, the gettering layer 107 moves nickel in the lower crystalline silicon film 104b upward as indicated by an arrow 108 in FIG. In this gettering step, first, the nickel dissolved in the crystalline silicon film 104b moves to the gettering layer 107, so that the nickel concentration in the silicon film decreases, and the Ni silicide deposited in the film is removed. Is dissolved in the silicon film. These also move to the gettering layer 107 in a solid solution state, the Ni silicide in the crystalline silicon 104b disappears, the concentration of nickel in the solid solution is reduced, and the crystalline silicon film 104c is obtained. As a result, the nickel concentration of the crystalline silicon film 204c was measured by secondary ion mass spectrometry (SIMS) to be 5 × 10 ^Fifteen atoms / cm ³ To about the lower limit of measurement. The nickel remaining in the crystalline silicon film 104c is not in a silicide state but in a solid solution state as interstitial nickel.
[0124]
Subsequently, as shown in FIG. 1F, the gettering layer 107 is oxidized by heat treatment in an oxidizing gas atmosphere to form a silicon oxide film 109. As the oxidation treatment at this time, a heat treatment in a relatively high-pressure oxidizing gas atmosphere exceeding 1 atm, or an RTA treatment in which a heated oxidizing gas is blown onto the surface of the gettering layer 107 can be used. As the oxidizing gas at this time, steam is optimal from the viewpoint of high oxidation reactivity and safety. In the former method, the inside of the furnace may be pressurized with steam in a range of 5 to 15 atm, and heat treatment may be performed at 550 to 600 ° C for about 10 minutes to 2 hours. In the latter method, a steam gas heated to a high temperature may be directly blown onto the surface of the gettering layer to perform RTA treatment at 650 ° C. or more and 800 ° C. or less for about 5 minutes to 20 minutes. At this time, it is desirable that the rate of temperature increase and the rate of temperature decrease are both 100 ° C./min or more.
[0125]
In the present embodiment, the gettering layer 107 is oxidized using the RTA apparatus shown in FIG. The temperature of the substrate is increased from 100 ° C./min to 300 ° C./min from the state where the substrate is preheated to about 400 ° C. using steam as the introduced gas 808, and a heat treatment is performed at a temperature of 720 ° C. for 10 minutes, for example. Was. As a result, the gettering layer 107 having a thickness of 20 nm is oxidized to form a silicon oxide film 109. At this time, the surface of the lower crystalline silicon film 104c was also oxidized by about 10 nm to form a crystalline silicon film 104d having a thickness of 40 nm. In addition, during this process, oxidation of the surface layer of the gettering layer 107 and the crystalline silicon film 104c causes excessive silicon atoms, which diffuse into the crystalline silicon film 104c and cause dangling bonds (dangling bonds). Ring bond) to terminate it. As a result, the resulting crystalline silicon film 104d has a reduced defect density and higher crystallinity. Further, on the surface of the crystalline silicon film 104d, irregularities were generated between the crystal domains due to the difference in the oxidation rate depending on the crystal orientation, and the height difference was about 2 nm or more and 5 nm or less.
[0126]
In the present embodiment, the heat treatment for gettering and the oxidation treatment with water vapor in the nitrogen atmosphere can be performed continuously using the apparatus shown in FIG. 9, which is effective. In this case, continuous processing can be easily performed by continuously switching from nitrogen gas to steam gas during RTA processing. Also, in the case of oxidation in a high-pressure atmosphere, continuous treatment with gettering heat treatment can be performed by similarly switching the atmosphere gas. Furthermore, by optimizing the heating conditions, gettering and oxidation can be performed simultaneously / continuously by heat treatment in a steam atmosphere.
[0127]
Then, the silicon oxide film 109 is entirely removed by etching. As an etchant at this time, wet etching was performed using a sufficiently lower crystalline silicon film 104d and 1: 100 buffered hydrofluoric acid (BHF) having etching selectivity.
[0128]
Through the above steps, a semiconductor film (crystalline silicon film) 104d according to the present invention is obtained as shown in FIG.
[0129]
FIG. 2A is a schematic plan view of a semiconductor film obtained by the above-described method. As shown in FIG. 2A, the semiconductor film has a plurality of domains 10. Each domain 10 is in contact with an adjacent domain at a domain boundary 11.
[0130]
FIG. 2B is a cross-sectional view of the semiconductor film taken along line AA ′ of FIG. In FIG. 2B, a base film 15 and a semiconductor film 16 are sequentially stacked on a substrate 12. The base film 15 is composed of a first base film 13 and a second base film 14 (both are silicon oxynitride films). As can be seen from FIG. 2B, since each domain 10 has a different surface height, the surface of the semiconductor film 16 has irregularities corresponding to the shape of the domain 10. The reason why the surface height differs for each domain is that the oxidation rate varies depending on the crystal orientation as described above.
[0131]
(2nd Embodiment)
Next, a second embodiment of the present invention will be described. This embodiment is an n-channel TFT using the semiconductor thin film (crystalline silicon film) manufactured in the first embodiment and a method of manufacturing the same on a glass substrate. The TFT of the present embodiment can be used not only as a driver circuit and a pixel portion of an active matrix type liquid crystal display device or an organic EL display device, but also as an element constituting a thin film integrated circuit. FIG. 3 is a cross-sectional view illustrating a manufacturing process of the n-channel TFT described here. The manufacturing process sequentially proceeds in the order of (A) → (E).
[0132]
FIG. 3A shows a state in which a crystalline silicon film 204d is formed by a method similar to the method described in the first embodiment, and corresponds to FIG. 1G in the first embodiment. That is, a silicon oxynitride film is formed as a first base film 202 on a glass substrate 201, and a silicon oxide film is formed as a second base film 203 thereon.
Then, a crystalline silicon film 204d manufactured according to the first embodiment is formed.
[0133]
Then, unnecessary portions of the crystalline silicon film 204d are removed to perform element isolation. By this step, as shown in FIG. 3B, an island-shaped semiconductor layer 210 to be an active region (source / drain region, channel region) of the TFT later is formed.
[0134]
Next, a silicon oxide film having a thickness of 20 to 150 nm (here, 100 nm) is formed as the gate insulating film 211 so as to cover the semiconductor layer 210. Here, the silicon oxide film is formed by using an RF plasma CVD method at a substrate temperature of 150 ° C. to 600 ° C., preferably 300 ° C. to 450 ° C., together with oxygen, using TEOS (Tetra Ethoxy Ortho Silicate) as a raw material. .
Alternatively, the substrate may be formed at a substrate temperature of 350 ° C. or more and 600 ° C. or less, preferably 400 ° C. or more and 550 ° C. or less using TEOS as a raw material by a low pressure CVD method or a normal pressure CVD method together with ozone gas. After the film formation, annealing is performed at 500 to 600 ° C. for 1 to 4 hours in an inert gas atmosphere in order to improve the bulk characteristics of the gate insulating film itself and the interface characteristics between the crystalline silicon film and the gate insulating film. You may.
[0135]
Subsequently, a conductive film is deposited on the gate insulating film 211 by a sputtering method, a CVD method, or the like, and this is patterned to form a gate electrode 212. Various materials such as a metal film, a high-melting-point metal film, and a low-resistance semiconductor film can be used as the conductive film, and may be selected depending on the use as a semiconductor device, a required process temperature in a later step, and the like. In this embodiment, a gate electrode 212 is formed by forming a film of aluminum (containing 1% of scandium) to a thickness of 400 to 800 nm, for example, 500 nm by sputtering, and patterning the film. The high temperature resistance is improved by mixing trace elements such as scandium, titanium, and silicon in the aluminum film. Here, when the TFT according to the present embodiment is applied as a pixel TFT of a liquid crystal display device or the like, the gate electrode 212 simultaneously constitutes a gate bus line in plan view.
[0136]
Then, as shown in FIG. 3C, a low-concentration impurity (phosphorus) 213 is implanted into the semiconductor layer 210 using the gate electrode 212 as a mask by an ion doping method. Phosphine (PH) as doping gas ₃ ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose is 1 × 10 ¹² ~ 1 × 10 ¹⁴ cm ^-2 , For example, 8 × 10 ¹² cm ^-2 And By this step, in the semiconductor layer 210, a low-concentration phosphorus 213 is implanted into a region 214 which is not covered with the gate electrode 212, and a region which is masked by the gate electrode 212 and is not implanted with phosphorus 213 is later formed with a channel region 215 of the TFT. Become.
[0137]
Subsequently, as shown in FIG. 3D, a doping mask 216 made of a photoresist is provided so as to cover the gate electrode 212 slightly larger. After that, an impurity (phosphorus) 217 is implanted into the semiconductor layer 210 at a high concentration using the resist mask 216 as a mask by an ion doping method. Phosphine (PH) as doping gas ₃ ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose is 1 × 10 ^Fifteen ~ 8 × 10 ^Fifteen cm ^-2 , For example, 2 × 10 ^Fifteen cm ^-2 And By this step, a region into which the impurity (phosphorus) 217 is implanted at a high concentration becomes a source / drain region 218 of the TFT later. In the semiconductor layer 210, a region covered with the resist mask 216 and not doped with high-concentration phosphorus 217 remains as a low-concentration phosphorus-implanted region to form an LDD (Lightly Doped Drain) region 219. . By forming the LDD region 219 in this manner, the electric field concentration at the junction between the channel region and the source / drain region can be reduced, the leak current at the time of TFT off operation can be reduced, and deterioration due to hot carriers can be suppressed. And the reliability of the TFT can be improved.
[0138]
Note that, even if the LDD region 219 is left in a non-doped (intrinsic) state without doping with low-concentration phosphorus in FIG. 3C, a so-called offset gate structure is formed. And improvement of hot carrier resistance can be achieved. However, in this case, since the resistance of the offset portion 219 becomes larger, the on-current value of the TFT is lower than that of the LDD structure. As a method for forming such an LDD structure or an offset gate structure, in addition to the method using a resist mask as described above, the surface of an aluminum electrode is anodized to form an oxide layer on the surface, and the oxidation is performed. The above structure can be formed using the thickness (width) of the material layer. Alternatively, an insulating film or the like is formed over the gate electrode and etched back to form a sidewall on a side wall of the gate electrode, which can be used. In the present embodiment, the LDD region 219 is formed outside the gate electrode 212, but may be formed to have a structure that partially overlaps the gate electrode (GOLD structure; Gate Overlapped LDD). This is particularly effective in suppressing hot carrier deterioration.
[0139]
Then, after removing the photoresist 216 used as a mask for doping, annealing is performed by irradiating a laser beam from above the substrate to activate the ion-implanted impurities and, at the same time, to improve the crystallinity in the impurity introduction step. Improve the crystallinity of the deteriorated part. At this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) was used as a laser, and the energy density was 200 to 450 mJ / cm. ² , Preferably 250 to 350 mJ / cm ² Irradiation was performed. At this time, the channel region 215 is not irradiated with laser light because the upper gate electrode 212 serves as a mask to block laser light. The sheet resistance of the N-type impurity (phosphorus) region 218 thus formed was 200 to 500 Ω / □, and the sheet resistance of the LDD region 219 in which phosphorus was implanted at a low concentration was 30 to 50 kΩ / □.
[0140]
Here, the impurity was activated by laser irradiation. However, an RTA apparatus using a lamp or the like as a heat source, an RTA apparatus by inserting a substrate into a furnace with a single wafer, an inert gas heated to a high temperature, An RTA apparatus or the like that sprays on the substrate surface may be used. When such an RTA method is used, it is preferable to perform the heating at a temperature of 600 ° C. or more and 650 ° C. or less for about 30 seconds or more and 2 minutes or less from the heat resistance of aluminum.
[0141]
Subsequently, as shown in FIG. 3E, a silicon oxide film or a silicon nitride film having a thickness of about 400 nm to 1000 nm is formed as the interlayer insulating film 220. When a silicon oxide film is used, if TEOS is used as a raw material and formed by a plasma CVD method with oxygen, a reduced pressure CVD method with ozone, or a normal pressure CVD method, a good interlayer insulation with excellent step coverage can be obtained. A film is obtained. In addition, SiH ₄ And NH ₃ If a silicon nitride film formed by a plasma CVD method is used as a source gas, hydrogen atoms are supplied to the interface between the active region and the gate insulating film, and there is an effect of reducing dangling bonds that deteriorate TFT characteristics.
[0142]
Next, a contact hole is formed in the interlayer insulating film 220, and an electrode / wiring 221 of the TFT is formed using a metal material, for example, a two-layer film of titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer. When the present TFT 222 is used as a pixel TFT, since it is an element for switching the pixel electrode, the other drain electrode is provided with a pixel electrode made of a transparent conductive film such as ITO. In this case, the other electrode forms a source bus line, a video signal is supplied via the source bus line, and necessary charges are written to the pixel electrodes based on the gate signal of the gate bus line 212. Further, the present TFT can be easily applied to a thin film integrated circuit or the like. In that case, a contact hole may be formed also on the gate electrode 212 and a necessary wiring may be provided.
[0143]
Finally, annealing is performed at 350 ° C. for one hour in a nitrogen atmosphere, a hydrogen atmosphere, or the like to complete the TFT 222 shown in FIG. If necessary, a protective film made of a silicon nitride film or the like may be provided on the TFT for the purpose of protecting the TFT 222.
[0144]
The TFT manufactured according to the above embodiment has a field effect mobility of 300 cm. ² Despite the extremely high performance of about / Vs and the threshold voltage of about 1.5 V, the abnormal increase of the leak current at the time of the TFT off operation, which is a problem in the conventional example, is suppressed. A very low value of several pA or less was stably shown. This value is not much different from that of a conventional TFT formed without using a catalytic element, and the production yield was greatly improved. In addition, even after repeated measurements and durability tests with bias and temperature stress, little deterioration in characteristics was observed, and the reliability was much higher than that of the conventional one.
[0145]
Further, when the TFT manufactured according to the present embodiment is applied to a pixel TFT of an active matrix substrate for liquid crystal display as a dual gate structure, display unevenness is clearly less than that manufactured by a conventional method, and TFT leakage is caused. A pixel defect was extremely small, and a high display quality liquid crystal panel having a high contrast ratio was obtained.
[0146]
(Third embodiment)
A third embodiment according to the present invention will be described. The present embodiment is a circuit having a CMOS structure using the semiconductor thin film (crystalline silicon film) manufactured in the above-described first embodiment and a step of manufacturing the circuit on a glass substrate. The circuit having the CMOS structure according to the present embodiment is configured such that an n-channel TFT and a p-channel TFT forming a peripheral driving circuit of an active matrix type liquid crystal display device or a general thin film integrated circuit are formed in a complementary manner. .
[0147]
FIG. 4 is a cross-sectional view illustrating a manufacturing process of the TFT described in the present embodiment, and the process proceeds sequentially according to the order of FIGS.
[0148]
FIG. 4A shows a state in which the crystalline silicon film 304d is formed according to the method described in the first embodiment, and corresponds to FIG. 1G in the first embodiment. That is, a silicon oxynitride film is formed as a first base film 302 on a glass substrate 301, and a silicon oxide film is formed as a second base film 303 thereon. Then, a crystalline silicon film 304d manufactured according to the first embodiment is formed.
[0149]
Next, unnecessary portions of the crystalline silicon film 304d are removed to perform element isolation. By this step, as shown in FIG. 4B, an island-shaped crystalline silicon film (semiconductor layer) 310n which will later become active regions (source / drain regions, channel regions) of the n-channel TFT and the p-channel TFT And 310p are formed.
[0150]
Here, as an impurity element for imparting p-type at a concentration of about 1 × 1016 to 5 × 1017 / cm3 for the purpose of controlling the threshold voltage, boron is deposited on the entire surface of the semiconductor layers of the n-channel TFT and the p-channel TFT. (B) may be added. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film.
[0151]
Next, a silicon oxide film having a thickness of 20 to 150 nm, here 100 nm, is formed as the gate insulating film 311 so as to cover the semiconductor layers 310 n and 310 p. In this case, the silicon oxide film was formed using TEOS as a raw material and decomposed and deposited by RF plasma CVD at a substrate temperature of 300 to 450 ° C. together with oxygen. As the gate insulating film 311, another insulating film containing silicon may be used as a single layer or a stacked structure.
[0152]
Subsequently, a conductive film is deposited and patterned to form gate electrodes 312n and 312p. In this embodiment, a high melting point metal is formed as a conductive film by a sputtering method. As the high melting point metal at this time, an element selected from tantalum (Ta), tungsten (W), molybdenum (Mo), titanium (Ti), an alloy containing the above elements as a main component, or an alloy combining the above elements A film (typically, a Mo-W alloy film or a Mo-Ta alloy film) may be used. Further, as another alternative material, tungsten silicide, titanium silicide, or molybdenum silicide may be used. In the present embodiment, tungsten (W) is used and the thickness is 300 to 600 nm, for example, 450 nm. At this time, it is preferable to reduce the concentration of impurities contained in order to reduce the resistance. By setting the oxygen concentration to 30 ppm or less, a specific resistance value of 20 μΩcm or less could be realized.
[0153]
Next, as shown in FIG. 4C, low-concentration impurities (phosphorus) 313 are implanted into the semiconductor layer by ion doping using the gate electrodes 312n and 312p as a mask. Phosphine (PH) as doping gas ₃ ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose is 1 × 10 ¹² ~ 1 × 10 ¹⁴ cm ^-2 , For example, 2 × 10 ^Thirteen cm ^-2 And In this step, regions of the semiconductor layers 310n and 310p that are not covered with the gate electrodes 312n and 312p become regions 314n and 314p into which low-concentration phosphorus 313 has been implanted. The regions later become channel regions 315n and 315p of the n-channel TFT and the p-channel TFT.
[0154]
Next, as shown in FIG. 4D, in the later n-channel TFT, a doping mask 316n made of a photoresist is provided so as to cover the gate electrode 312n a little larger, and in the later p-channel TFT, a semiconductor is used. A photoresist doping mask 316p is provided so as to cover the entire layer 310p. After that, an impurity (phosphorus) 317 is implanted into the semiconductor layer at a high concentration by the ion doping method using the resist masks 316n and 316p as a mask. At this time, phosphine (PH) is used as a doping gas. ₃ ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose is 1 × 10 ^Fifteen ~ 1 × 10 ¹⁶ cm ^-2 , For example, 5 × 10 ^Fifteen cm ^-2 And By this step, in the semiconductor layer 310n of the n-channel TFT, the region into which the impurity (phosphorus) 317 is implanted at a high concentration later becomes the source / drain region 318 of the n-channel TFT and is covered with the resist mask 316n. The region where the high concentration phosphorus 317 is not doped remains as a region where low concentration phosphorus is implanted to form an LDD (Lightly Doped Drain) region 319. Further, in the p-channel TFT later, since the entire region of the semiconductor layer is covered with the mask 316p, the high concentration impurity (phosphorus) 317 is not implanted in this step. At this time, the concentration of n-type impurity element (phosphorus) 317 in region 318 in the film is 1 × 10 ¹⁹ ~ 1 × 10 ²¹ / Cm ³ It has become. The concentration of the n-type impurity element (phosphorus) 313 in the LDD region 319 of the n-channel TFT in the film is 1 × 10 ¹⁷ ~ 1 × 10 ²⁰ / Cm ³ And functions as an LDD region in such a range.
[0155]
Next, after removing the resist masks 316n and 316p, as shown in FIG. 4E, a doping mask 320 of a photoresist is newly provided so as to entirely cover the semiconductor layer 310n of the n-channel TFT. At this time, no mask is provided above the p-channel TFT, and the entire TFT is exposed. In this state, an impurity (boron) 321 for imparting p-type is implanted into the semiconductor layer by ion doping using the resist mask 320 and the gate electrode 312p of the p-channel TFT to be used as a mask. As a doping gas, diborane (B ₂ H ₆ ), The acceleration voltage is 40 kV to 80 kV, for example, 65 kV, and the dose is 1 × 10 ^Fifteen ~ 1 × 10 ¹⁶ cm ^-2 , For example, 7 × 10 ^Fifteen cm ^-2 And By this step, in the semiconductor layer of the p-channel type TFT, high-concentration boron 321 is implanted into a region 314p exposed from the gate electrode 312p, and the low-concentration phosphorus implanted in the previous step is canceled out (so-called. The polarity is reversed from N-type to P-type (by counter doping). As a result, the source / drain region 322 of the p-channel TFT is formed, and the region which is masked by the gate electrode 312p and into which impurities are not implanted becomes the channel region 315p of the p-channel TFT. In this step, the semiconductor layer 310n of the subsequent n-channel TFT is entirely covered with the mask 320, so that the boron 321 is not doped at all.
[0156]
At the time of doping with the n-type impurity and the p-type impurity, each element is selectively doped by covering the region not requiring doping with a photoresist in this manner, so that the n-type high-concentration impurity region 318 and the p-type impurity are doped. The impurity region 322 and the impurity region 322 can be separately formed. In this embodiment, the n-type impurity element is added to the semiconductor layer. However, the order of the steps is not limited to this embodiment, and may be appropriately determined by an operator.
[0157]
Next, after the resist mask 320 is removed, this is subjected to a heat treatment in an inert atmosphere. This heat treatment activates the ion-implanted impurity in the source / drain region and the LDD region, and at the same time, improves the crystallinity of the portion where the crystallinity has deteriorated in the impurity introducing step. At this time, in this embodiment, since a high melting point metal (W) is used as the gate electrode material, heat treatment at a relatively high temperature is possible, and the condition margin is widened. Actually, in the present embodiment, a general diffusion furnace is used to perform a heat treatment in a nitrogen atmosphere at a temperature range of 500 ° C. to 600 ° C. for about 30 minutes to 8 hours. In addition, an RTA apparatus using a lamp or the like as a heat source, an RTA apparatus in which a substrate is inserted into a furnace by a single wafer, and an RTA apparatus in which an inert gas heated to a high temperature is blown onto the substrate surface are used. You may. When such an RTA method is used, it is preferable to perform the heating at a temperature of 600 ° C. to 700 ° C. for about 30 seconds to 10 minutes. As a result, the sheet resistance of the source / drain region 318 of the n-channel type TFT was about 500 to 800 Ω / □, and the sheet resistance of the LDD region 319 was 30 to 60 kΩ / □. The sheet resistance of the source / drain region 322 of the p-channel TFT was about 1 to 1.5 kΩ / □.
[0158]
Next, an interlayer insulating film is formed as shown in FIG. A silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed with a thickness of 400 to 1500 nm (typically, 600 to 1000 nm). In this embodiment, a 200-nm-thick silicon nitride film 323 and a 700-nm-thick silicon oxide film 324 are stacked to form a two-layer structure. As a film forming method at this time, a plasma CVD method is used, and the silicon nitride film is formed of SiH ₄ And NH ₃ Is used as a source gas, the silicon oxide film is made of TEOS and O ₂ Was used as a raw material to form a continuous film. Of course, the inorganic interlayer insulating film is not limited to this, and another insulating film containing silicon may have a single-layer or stacked structure.
[0159]
Further, a heat treatment is performed at 300 to 500 ° C. for one to several hours to hydrogenate the semiconductor layer. In this step, hydrogen atoms are supplied to the interface between the semiconductor layer and the gate insulating film to terminate and inactivate dangling bonds that degrade TFT characteristics. In this embodiment, heat treatment was performed at 410 ° C. for one hour in a nitrogen atmosphere containing about 3% of hydrogen. When the amount of hydrogen contained in the interlayer insulating film (particularly, the silicon nitride film 323) is sufficient, the effect can be obtained even by performing the heat treatment in a nitrogen atmosphere. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0160]
Next, a contact hole is formed in the interlayer insulating film, and an electrode / wiring 325 of the TFT is formed using a metal material, for example, a two-layer film of titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer. Finally, annealing is performed at 350 ° C. for one hour to complete the n-channel TFT 326 and the p-channel TFT 327 shown in FIG. Further, if necessary, contact holes are provided also on the gate electrodes 312n and 312p, and necessary electrodes are connected by the wiring 325. For the purpose of protecting the TFTs, a protective film made of a silicon nitride film or the like may be provided on each TFT.
[0161]
The field-effect mobility of each TFT manufactured according to the above embodiment is 250 to 300 cm for an n-channel TFT. ² / Vs, 120-150cm with p-channel TFT ² / Vs, and the threshold voltage is about 1 V for an n-channel TFT, and about -1.5 V for a p-channel TFT, showing very good characteristics. In addition, the abnormal increase of the leak current at the time of the TFT off operation, which was a problem in the conventional example, was suppressed, and almost no characteristic deterioration was observed even after repeated measurement or durability test by bias or temperature stress. Further, when a circuit such as an inverter chain or a ring oscillator is formed by a CMOS structure circuit in which an n-channel TFT and a p-channel TFT manufactured in the present embodiment are configured in a complementary manner, it is very much compared with the conventional one. High reliability and stable circuit characteristics.
[0162]
(Fourth embodiment)
A semiconductor film and a method for manufacturing the semiconductor film according to a fourth embodiment of the present invention will be described with reference to FIG. In the present embodiment, the amorphous semiconductor film is crystallized by a method different from the method described in the first embodiment. FIG. 5 is a cross-sectional view illustrating a manufacturing process in the present embodiment, and the manufacturing process sequentially proceeds according to (A) to (I).
[0163]
First, as in the first embodiment, a base film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on a substrate (a glass substrate in this embodiment) 401 in order to prevent impurity diffusion from the substrate. I do. In the present embodiment, the silicon nitride film is formed as the lower first base film 402, and the silicon oxide film is stacked thereon with the second base film 403. At this time, the thickness of the silicon oxynitride film of the first base film 402 was, for example, 100 nm, and the thickness of the silicon oxynitride film of the second base film 403 was, for example, 100 nm. Next, the a-Si film 404 is formed with a thickness of 25 nm or more and 80 nm or less. In this embodiment, an amorphous silicon film having a thickness of 50 nm is formed by using the plasma CVD method. In this step, the base insulating film and the amorphous semiconductor film may be formed continuously without opening to the atmosphere.
[0164]
Next, a mask insulating film 405 made of a silicon oxide film is formed to a thickness of 200 nm. As shown in FIG. 5A, the mask insulating film has an opening 400 for adding a catalytic element to the semiconductor film.
[0165]
Next, as shown in FIG. 5B, an aqueous solution (aqueous nickel acetate solution) containing 100 ppm by weight of a catalytic element (nickel in this embodiment) is applied by spin coating to form a catalytic element layer 406. I do. At this time, the catalytic element 406 selectively contacts the a-Si film 404 in the opening 400 of the mask insulating film 405 to form a catalytic element added region.
[0166]
In this embodiment, a method of adding nickel by spin coating is used, but a thin film (a nickel film in the case of this embodiment) made of a catalytic element is formed on the a-Si film by a vapor deposition method, a sputtering method, or the like. Means may be taken.
[0167]
Next, heat treatment is performed at a temperature of 500 to 650 ° C. (preferably 550 to 600 ° C.) for 6 to 20 hours (preferably 8 to 15 hours). In this embodiment, the heat treatment is performed at 570 ° C. for 14 hours. As a result, as shown in FIG. 5C, a crystal nucleus is generated in the catalytic element addition region 400, and the a-Si film in the region 400 is first crystallized to form a crystalline silicon film 404a. Further, crystallization proceeds from the crystallization region 404a in a direction substantially parallel to the substrate (the direction indicated by the arrow 407), and a crystalline silicon film 404b having a uniform macroscopic crystal growth direction is formed. At this time, nickel 406 existing on mask 405 is blocked by mask film 405 and does not reach the underlying a-Si film, and crystallization of a-Si film 404 is caused only by nickel introduced in region 400. Done. Further, a region where the crystal growth in the lateral direction does not reach remains as an amorphous region 404c. However, depending on the layout, there may be a case where a boundary occurs by colliding with a region where the crystal has grown laterally from an adjacent opening, and in this case, the region does not become an amorphous region.
[0168]
After removing the silicon oxide film 405 used as a mask, the obtained crystalline silicon film is irradiated with a laser beam as shown in FIG. Improvements may be made. As a result, the crystalline silicon film in the region 404b where the crystal has grown in the lateral direction has a higher quality, and becomes a crystalline silicon film 404d.
[0169]
Next, after removing the natural oxide film on the surface of the crystalline silicon film 404d, a gettering layer 409 is formed as shown in FIG. Regarding the formation of the gettering layer, the same method as in the first embodiment may be used.
[0170]
Then, this is subjected to a first heat treatment under an inert atmosphere. As a heat treatment method at this time, general furnace annealing or rapid thermal annealing (RTA) can be used. In this embodiment, RTA is used. When RTA is used, heat treatment is performed at a temperature of 600 ° C. or more and 750 ° C. or less for about 30 seconds to 15 minutes. In the case of using furnace annealing, a heat treatment at a temperature of 500 ° C. or more and 600 ° C. or less for about 15 minutes to 4 hours may be performed.
[0171]
By this heat treatment, the gettering layer 409 moves nickel in the lower crystalline silicon film 404d upward as indicated by an arrow 410 in FIG. As a result, Ni silicide in the crystalline silicon film 404d disappears, the concentration of nickel in a solid solution state is reduced, and gettering is performed. Then, a crystalline silicon film 404e with a reduced nickel concentration is obtained.
[0172]
Subsequently, as shown in FIG. 5G, the gettering layer 409 is oxidized by heat treatment in an oxidizing gas atmosphere to form a silicon oxide film 411. At this time, as in the first embodiment, as in the first embodiment, steam is used as an oxidizing gas, heat treatment is performed in a high-pressure oxidizing gas atmosphere exceeding 1 atm, or the surface of the gettering layer 409 is heated. RTA treatment for blowing an oxidizing gas may be used. Through this step, the crystalline silicon film 404e has a reduced defect density and becomes a crystalline silicon film 404f having higher crystallinity. The surface of the crystalline silicon film 404f has irregularities between crystal domains due to a difference in oxidation rate depending on the crystal orientation.
[0173]
Then, as shown in FIG. 5H, the silicon oxide film 411 is entirely removed by etching to obtain a desired high-quality crystalline silicon film 404f. Then, as shown in FIG. 5I, the crystalline silicon film in the laterally grown region 404f is etched into a predetermined shape to form a semiconductor layer 412 of a later TFT.
[0174]
By adapting the crystallization method described in this embodiment to the crystallization steps in the first to third embodiments, a high-performance TFT having higher current driving capability can be realized.
[0175]
(Fifth embodiment)
The semiconductor device of the present embodiment is an active matrix substrate. FIGS. 6A and 6B are block diagrams of the active matrix substrate of the present embodiment.
[0176]
FIG. 6A shows a circuit configuration for performing analog driving. This embodiment shows a semiconductor device having a source side driving circuit 50, a pixel portion 51, and a gate side driving circuit 52. Note that in this specification, a drive circuit is a general term including a source-side processing circuit and a gate-side drive circuit.
[0177]
The source-side drive circuit 50 includes a shift register 50a, a buffer 50b, and a sampling circuit (transfer gate) 50c. The gate-side drive circuit 52 includes a shift register 52a, a level shifter 52b, and a buffer 52c. If necessary, a level shifter circuit may be provided between the sampling circuit and the shift register.
[0178]
In the present embodiment, the pixel unit 51 includes a plurality of pixels, and each of the plurality of pixels includes a TFT element.
[0179]
Although not shown, a gate-side drive circuit may be further provided on the side opposite to the gate-side drive circuit 52 with the pixel portion 51 interposed therebetween.
[0180]
FIG. 6B shows a circuit configuration for performing digital driving.
This embodiment shows a semiconductor device having a source side driving circuit 53, a pixel portion 54, and a gate side driving circuit 55. In the case of digital driving, a latch (A) 53b and a latch (B) 53c may be provided instead of the sampling circuit as shown in FIG. The source-side drive circuit 53 includes a shift register 53a, a latch (A) 53b, a latch (B) 53c, a D / A converter 53d, and a buffer 53e. The gate-side drive circuit 55 includes a shift register 55a, a level shifter 55b, and a buffer 55c. If necessary, a level shifter circuit may be provided between the latch (B) 53c and the D / A converter 53d.
[0181]
The above configuration can be realized according to the manufacturing steps described in the first to fourth embodiments. In this embodiment, only the configuration of the pixel portion and the driving circuit is shown. However, according to the manufacturing process of the present invention, a memory or a microprocessor can be formed.
[0182]
(Sixth embodiment)
The semiconductor device of the present embodiment is an active matrix type liquid crystal display device using the CMOS circuit or the pixel portion formed in the above embodiment, and all electric appliances having such a liquid crystal display device as a display portion.
[0183]
Examples of such appliances include video cameras, digital cameras, projectors (rear or front type), head mounted displays (goggle type displays), personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Is mentioned.
[0184]
In this embodiment, a crystalline semiconductor film having good crystallinity using a catalyst element can be formed, and the catalyst element can be gettered more sufficiently. Therefore, the characteristics of the n-channel TFT and the p-channel TFT can be improved. And a good CMOS drive circuit with high reliability and stable circuit characteristics can be realized. Further, even in a switching TFT in a pixel in which a leak current at the time of an off operation becomes a problem, a TFT of a sampling circuit in an analog switch portion, and the like, generation of a leak current considered to be caused by segregation of a catalytic element can be sufficiently suppressed. As a result, good display without display unevenness becomes possible. In addition, since the display is good and has no display unevenness, it is not necessary to use a light source more than necessary, so that unnecessary power consumption can be reduced and electric appliances (cell phones, portable books, displays, etc.) that can reduce power consumption can be obtained. ) Can be realized.
[0185]
As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electric appliances in all fields. Further, the electric appliance of the present embodiment can be realized by using a display device manufactured by combining the above embodiments.
[0186]
Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible.
[0187]
For example, in addition to the pure silicon film described in the above-described embodiment, a mixed film of germanium and silicon (silicon-germanium film) or a pure germanium film can be used as the semiconductor film to be used in the present invention.
[0188]
Further, as a method of introducing nickel, a method of applying the surface of the amorphous silicon film with a solution in which a nickel salt was dissolved was adopted. A method in which nickel is diffused from the lower layer of the amorphous silicon film to perform crystal growth may be used. Various other methods can be used as a method for introducing nickel. For example, an SOG (spin-on-glass) material is used as a solvent for dissolving a nickel salt, ₂ There is also a method of diffusing from a film. Further, a method of forming a thin film by a sputtering method, a vapor deposition method, a plating method, a method of directly introducing a thin film by an ion doping method, or the like can be used.
[0189]
In the above-described embodiment, the crystalline semiconductor film is manufactured by crystallizing the entire amorphous silicon film formed over the entire surface of the substrate. However, the present invention is not limited to this. Alternatively, a crystalline semiconductor film may be formed in each of a plurality of regions by the method described above.
[0190]
As described above, in the present invention, a stable gettering method that has a large manufacturing process margin, a high manufacturing yield, and an excellent gettering effect is used. Therefore, in a crystalline semiconductor film having good crystallinity manufactured using a catalytic element, the concentration of the catalytic element contained in the crystalline semiconductor film can be stably reduced without damaging the crystalline semiconductor film itself by etching or the like. It can be greatly reduced. When such a semiconductor film is used, generation of a leak current can be suppressed, reliability can be improved, and a high-performance semiconductor device (TFT, active matrix substrate, liquid crystal display, Devices, appliances, etc.). Further, in the manufacturing process of such a semiconductor device, the yield can be greatly improved, and the manufacturing cost can be reduced.
[0191]
【The invention's effect】
According to the present invention, a highly reliable crystalline semiconductor film in which the content of a catalytic element is sufficiently reduced can be provided. In addition, it is possible to provide a method for easily manufacturing such a semiconductor film without increasing a manufacturing process or manufacturing cost. Further, by using the semiconductor film as an active layer, a high-performance semiconductor device (including a TFT) can be realized, and a high-performance semiconductor device with a high degree of integration can be easily manufactured.
[0192]
In particular, when the present invention is applied to a liquid crystal display device (a driver monolithic type active matrix substrate forming an active matrix portion and a peripheral drive circuit portion on the same substrate), the switching characteristics of the pixel switching TFT required for the active matrix substrate are improved. This is advantageous because it simultaneously satisfies the high performance and high integration required for the TFTs constituting the peripheral drive circuit section, and can realize a compact, high performance and low cost module.
[Brief description of the drawings]
FIGS. 1A to 1G are schematic process cross-sectional views illustrating a method for manufacturing a semiconductor film according to a first embodiment of the present invention.
FIGS. 2A and 2B are a schematic plan view and a cross-sectional view of a semiconductor film according to a first embodiment of the present invention.
FIGS. 3A to 3E are schematic process cross-sectional views illustrating a method for manufacturing a thin film transistor according to a second embodiment of the present invention.
FIGS. 4A to 4F are process cross-sectional views illustrating a method of manufacturing a circuit having a CMOS structure according to a third embodiment of the present invention.
FIGS. 5A to 5I are schematic cross-sectional views illustrating a method for forming a semiconductor film according to a fourth embodiment of the present invention.
FIGS. 6A and 6B are block diagrams of an active matrix substrate according to a fifth embodiment of the present invention.
7A is a diagram showing crystal growth and FIG. 7B is a diagram showing a <111> crystal zone plane in a case where an amorphous semiconductor film is crystallized by adding a catalytic element. (C) is a diagram showing a standard triangle of the crystal orientation.
FIGS. 8A and 8B are diagrams showing a plane orientation distribution of a crystalline semiconductor film obtained by using a catalytic element, and FIG. 8C is a diagram showing a standard triangle of crystal orientation. .
FIG. 9 is a diagram schematically showing a configuration of an RTA apparatus used in an embodiment of the present invention.
[Explanation of symbols]
10 domains
11 Domain boundaries
12 Substrate
13,14 silicon oxynitride film
15 Underlayer
16 Semiconductor film
101 substrate
102, 103 Underlayer
104 amorphous silicon film
104a, 104b crystalline silicon film
107 Gettering layer (amorphous silicon film)
108 Movement direction of catalytic element
109 Oxidized gettering layer (silicon oxide film)

Claims (39)

A semiconductor film having a plurality of crystal domains, wherein the plurality of crystal domains are mainly formed of a region in which a <111> crystal zone plane of a crystal is oriented, and a height of a surface of the semiconductor film is the plurality of crystal domains. A semiconductor film that differs depending on each of the crystal domains. 2. The semiconductor film according to claim 1, wherein 50% or more of the region in which the <111> crystal plane is oriented is a region with a (110) plane orientation or a (211) plane orientation. The semiconductor film according to claim 1, wherein a domain diameter of the plurality of crystal domains is 2 μm or more and 10 μm or less. 4. The semiconductor film according to claim 1, wherein at least a part of the semiconductor film contains a catalyst element that promotes crystallization of the amorphous semiconductor film. 5. The semiconductor film according to claim 4, wherein the catalyst element does not precipitate as a compound but exists as a solid solution in the semiconductor film. 6. The catalyst element includes nickel (Ni), iron (Fe), cobalt (Co), tin (Sn), lead (Pb), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), The semiconductor film according to claim 4, wherein the semiconductor film is at least one element selected from the group consisting of iridium (Ir), platinum (Pt), copper (Cu), and gold (Au). The semiconductor film according to claim 4, wherein the catalyst element is contained in at least a part of the semiconductor film at a concentration of 1 × 10 ¹⁴ atoms / cm ³ or more and 1 × 10 ¹⁷ atoms / cm ³ or less. . The semiconductor film according to claim 1, wherein the semiconductor film is formed with silicon (Si) as a main component. 9. The semiconductor film according to claim 5, wherein the catalyst element promotes crystallization of the amorphous semiconductor film by forming a silicide compound. 10. The semiconductor film according to claim 1, wherein the thickness of the semiconductor film is 25 nm or more and 80 nm or less. (1) preparing a first semiconductor film containing a catalytic element that promotes crystallization of an amorphous semiconductor film and having a crystalline region;
(2) providing a second semiconductor film in contact with the first semiconductor film;
(3) performing a first heat treatment on the first semiconductor film to move the catalyst element present in the first semiconductor film to the second semiconductor film;
(4) oxidizing the second semiconductor film;
(5) a method of manufacturing a semiconductor film, comprising: removing the oxidized second semiconductor film. In the step (1),
(1a) a step of preparing an amorphous semiconductor film containing the catalyst element;
(1b) performing a second heat treatment on the amorphous semiconductor film to form the first semiconductor film. 13. The method of manufacturing a semiconductor film according to claim 11, further comprising a step of removing a native oxide film formed on a surface of the first semiconductor film between the step (1) and the step (2). Method. 14. The method according to claim 11, wherein the second semiconductor film is in an amorphous state. The method of manufacturing a semiconductor film according to claim 11, wherein the second semiconductor film contains a gettering element that attracts the catalyst element. The method according to claim 15, wherein the gettering element includes at least one rare gas element selected from the group consisting of Ar, Kr, and Xe. The method according to claim 15, wherein the gettering element includes at least one element selected from the group consisting of P, As, and Sb. 18. The gettering element according to claim 15, wherein the gettering element includes at least one element selected from the group consisting of P, As, and Sb, and at least one element selected from the group consisting of B and Al. 3. The method for manufacturing a semiconductor film according to item 1. 19. The method of manufacturing a semiconductor film according to claim 11, wherein the step (3) includes a step of performing the first heat treatment while maintaining the amorphous state of the second semiconductor film. 20. The method of manufacturing a semiconductor film according to claim 11, wherein the step (4) includes a step of performing a third heat treatment on the second semiconductor film in an oxidizing gas atmosphere. . The method for manufacturing a semiconductor film according to claim 20, wherein the third heat treatment step is performed under a high-pressure atmosphere exceeding 1 atm. 21. The method of manufacturing a semiconductor film according to claim 20, wherein the third heat treatment step includes a high-speed thermal anneal for blowing a heated oxidizing gas onto a surface of the second semiconductor film. 23. The method for manufacturing a semiconductor film according to claim 20, wherein steam is used as the oxidizing gas in the third heat treatment step. 24. The method of manufacturing a semiconductor film according to claim 11, wherein the thickness of the second semiconductor film is in the range of 1/10 to 2 times the thickness of the first semiconductor film. The step (2) includes:
Exposing the surface of the first semiconductor film to a plasma atmosphere containing hydrogen;
25. The method according to claim 11, further comprising: forming the second semiconductor film on the first semiconductor film without exposing the first semiconductor film exposed to the plasma atmosphere to the air. A method for manufacturing a semiconductor film. In the step (4), in addition to the second semiconductor film, a part of the underlying first semiconductor film is also oxidized,
26. The semiconductor film according to claim 11, wherein, in the step (5), the part of the oxidized first semiconductor film is removed in addition to the oxidized second semiconductor film. Manufacturing method. 27. The method of manufacturing a semiconductor film according to claim 11, wherein in the step (4), the amount of dangling bonds of semiconductor atoms in the first semiconductor film is reduced. 28. The method of manufacturing a semiconductor film according to claim 20, wherein the first heat treatment step of the step (3) and the third heat treatment step of the step (4) are continuously performed. . 28. The method of manufacturing a semiconductor film according to claim 20, wherein the first heat treatment and the third heat treatment are performed simultaneously. 30. The method of manufacturing a semiconductor film according to claim 11, wherein the step (5) includes a step of removing the second semiconductor film by wet etching using an acid having hydrogen fluoride. . The step (1a) comprises:
Forming an amorphous semiconductor film;
30. A step of forming a first semiconductor film containing the catalyst element by applying a solution containing the catalyst element on the surface of the amorphous semiconductor film. A method for manufacturing a semiconductor film as described above. The step (1a) includes a step of selectively adding the catalyst element to a part of the amorphous semiconductor film to obtain an amorphous semiconductor film containing the catalyst element, and the step (1b) includes: 32. The step of obtaining the first semiconductor film by laterally crystal-growing the amorphous semiconductor film from a region where the catalytic element is selectively added to a peripheral portion thereof. The method for manufacturing a semiconductor film according to any one of the above. Nickel (Ni), iron (Fe), cobalt (Co), tin (Sn), lead (Pb), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), 33. The method of manufacturing a semiconductor film according to claim 11, wherein at least one element selected from the group consisting of iridium (Ir), platinum (Pt), copper (Cu), and gold (Au) is used. 34. The method of manufacturing a semiconductor film according to claim 12, wherein a step of irradiating the first semiconductor film with laser light is performed between the step (1b) and the step (2). A semiconductor film manufactured by the manufacturing method according to claim 11. A semiconductor device comprising the semiconductor film according to claim 1 as an active region. 36. A semiconductor device comprising a thin film transistor having the semiconductor film according to claim 1 as an active region. An electronic apparatus comprising the semiconductor device according to claim 36. An electronic device, comprising: a display unit including a plurality of pixels, wherein a display signal is supplied to the plurality of pixels via the semiconductor device according to claim 36.

Images