JP2004311764A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing a junction capacity with respect to a source and drain region. <P>SOLUTION: An element isolation region 109 is formed for a gate electrode 103 through self alignment. The shortest distance between the gate electrode 103 and the element isolation region 109 is not more than an alignment accuracy or (F/3). Here, F is the minimum working size. In other word, the active layer width of the source and drain region 103 is not more than F/3. Further, the width of a superimposed diffusion layer 1121 for the source and drain region 112 is made larger than a distance between the gate electrode 103 and the element isolation region 109. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor device capable of reducing a junction area of a source / drain region (a source region or a drain region is generally referred to as a source / drain region) to reduce a junction capacitance, and a manufacturing method thereof.
[0002]
[Prior art]
2. Description of the Related Art In recent years, high integration of LSIs (Large Scale Integrated Circuits) has been steadily progressing, and MOS transistors constituting LSIs have been increasingly miniaturized. With the miniaturization of MOS transistors, characteristic degradation such as an increase in punch-through and off-leak current due to the short channel effect has become a problem. As one of the methods for solving such a problem, there is a method of reducing the junction depth of the source and drain regions adjacent to the channel region of the transistor. To realize this shallow junction, Japanese Patent Application Laid-Open No. 2000-82815 (Patent Document 1) discloses that a source and a drain are stacked above a channel region on both sides of a gate electrode via a gate electrode side wall insulating film. A transistor having a structure in which a region (stacked diffusion layer) is formed has been proposed.
[0003]
FIG. 27 shows a schematic structure of this semiconductor device. FIG. 27A shows a planar layout thereof, and FIG. 27B shows a cross section taken along line BB ′ in FIG. 27A. An element isolation region 302 is formed in a semiconductor substrate 301, and a gate insulating film 303 and a gate electrode 304 are sequentially formed on the semiconductor substrate 301. On both sides of the gate electrode 304, a semiconductor layer 3081 is stacked above the surface of the semiconductor substrate 301 via a gate electrode side wall insulating film 305. After the impurities are implanted into the stacked semiconductor layers 3081, the impurities are diffused into the semiconductor substrate 301 by heat treatment, and an in-substrate diffusion layer 3082 is formed in the semiconductor substrate 301. By forming the in-substrate diffusion layer 3082 in this manner, a shallow junction can be formed with good controllability, that is, a structure capable of preventing the short channel effect can be formed. On the gate electrode 304 and the stacked semiconductor layers 3081, a high melting point silicide film 309 is formed. The width of the stacked semiconductor layers 3082 in a direction perpendicular to the longitudinal direction of the gate electrode 304 is determined by the distance between the gate electrode side wall insulating film 305 and the element isolation region 302, that is, the semiconductor substrate 301 and the gate insulating film 303. Are formed to be larger than the width of the active layer region of the source / drain region 308 on the surface in contact with. Therefore, the contact hole 311 is formed without reducing the contact area between the contact hole 311 and the high melting point silicide film 309, that is, without increasing the contact resistance, and the junction area is reduced to reduce the junction capacitance. You can do it.
[0004]
[Patent Document 1]
JP 2000-82815 A
[0005]
[Problems to be solved by the invention]
However, the above-described conventional semiconductor device has the following problems.
[0006]
The above problem will be described with reference to FIG. FIG. 2B is an enlarged view showing a source / drain region 308 formed in the semiconductor substrate 301 of the conventional semiconductor device. Assuming that the minimum processing size is F and the width of the gate electrode side wall insulating film 305 is b, the distance a between the gate electrode 304 and the element isolation region 302 is a> b + F in consideration of the alignment accuracy (F / 3). / 3 was satisfied. Therefore, there is a problem that the junction capacitance of the source and drain regions 308 increases. This is because the element isolation region 302 is not formed in a self-aligned manner with respect to the gate electrode 304, and therefore, the alignment accuracy (F / 3) is required to secure a region where current flows in the source and drain electrodes 308. This is because it is necessary to design the distance between the gate electrode 304 and the element isolation region 302 to be large by that size.
[0007]
The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device in which the junction capacitance of the source and drain regions is reduced, and a method for manufacturing the same.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor device according to the present invention includes:
In a semiconductor substrate, an active region, an element isolation region, a source region, and a drain region are provided directly or indirectly, a gate insulating film is provided on the active region, and a gate electrode is provided on the gate insulating film. In semiconductor devices,
Assuming that the minimum processing dimension is F, the shortest distance between the gate electrode and the element isolation region is F / 3 or less.
[0009]
Here, the semiconductor substrate is a semiconductor substrate including not only a semiconductor substrate in a narrow sense but also a broadly defined semiconductor substrate in which a thin film semiconductor is formed on an insulating substrate such as an SOI (Silicon On Insulator) substrate.
[0010]
Here, “providing an active region, an element isolation region, a source region, and a drain region directly or indirectly in a semiconductor substrate” means that they are directly provided in the semiconductor substrate. That is, providing them in a well region provided in the semiconductor substrate means indirectly providing them in the semiconductor substrate.
[0011]
The minimum processing dimension F is determined by the performance (accuracy, etc.) of a process apparatus for forming a fine resist pattern and the accuracy of an etching apparatus for etching a substrate using the fine resist pattern as a mask. For the moon, it is between 130 nm and 180 nm, and for those skilled in the art, it is generally determined uniquely by age. Of course, it should be noted that the minimum processing dimension F is determined by the state of the art at the time, is not fixed, and becomes smaller as the times progress.
[0012]
According to the semiconductor device having the above configuration, the shortest distance between the gate electrode and the element isolation region is F / 3 or less, so that the junction area between the source and drain regions is reduced as compared with a conventional semiconductor device. be able to. Therefore, the junction capacitance of the source and drain regions can be reduced.
[0013]
In one embodiment, the source region and the drain region are located above the interface between the active region and the gate insulating film, respectively, such that the source region and the drain region are located above the interface between the active region and the gate insulating film. Including a conductor formed over a portion of the region.
[0014]
According to the above embodiment, the conductor reduces the parasitic resistance of the transistor and improves the element speed.
[0015]
In one embodiment, a thickness of the region of the conductor near the gate electrode is smaller than a thickness of another region of the conductor.
[0016]
According to the above embodiment, the area where the gate electrode and the conductor face each other is reduced. Therefore, the capacitance associated with the gate electrode and the source and drain regions can be reduced.
[0017]
In one embodiment, the conductor is a stacked diffusion layer made of a polycrystalline silicon film.
[0018]
According to the above embodiment, since the conductor is made of a polycrystalline silicon film, the diffusion coefficient of impurities is large. Therefore, even if the thickness of the polycrystalline silicon film fluctuates due to process fluctuations, the impurity can be diffused from the stacked diffusion layer to the semiconductor substrate and the well region to the same depth with good controllability. An in-substrate diffusion layer can be formed.
[0019]
In one embodiment, a deep well region of a first conductivity type formed in the semiconductor substrate and a second well region formed in the deep well region of the first conductivity type and separated by the element isolation region are provided. A shallow well region of conductivity type,
The active region is provided in the shallow well region,
The gate electrode and the shallow well region of the second conductivity type are electrically connected.
[0020]
In this specification, the first conductivity type refers to P-type or N-type. When the first conductivity type is P-type, the second conductivity type is N-type and the first conductivity type is N-type. When it is a type, it means that the second conductivity type is a P type.
[0021]
The above embodiment has a so-called DTMOSFET (Dynamic Threshold) MOSFET in which the gate electrode and the shallow well region are electrically connected. Therefore, a semiconductor device with high speed and low power consumption can be realized.
[0022]
In one embodiment, the gate electrode and the shallow well region are electrically connected at two locations at both ends in the longitudinal direction of the gate electrode.
[0023]
According to the above embodiment, since the gate electrode and the shallow well region are connected at two places, a higher-speed semiconductor device can be realized.
[0024]
The method for manufacturing a semiconductor device according to the present invention includes:
A step of sequentially forming a gate insulating film, a gate electrode, and an insulating film on the gate electrode on the semiconductor substrate;
Forming a first gate electrode side wall insulating film and a second gate electrode side wall insulating film sequentially positioned from the gate electrode side on the side of the gate electrode;
Using the insulating film on the gate electrode, the first gate electrode side wall insulating film and the second gate electrode side wall insulating film as a mask, etching the semiconductor substrate to form a groove;
Burying an insulating film in the trench to form an element isolation region;
Removing the second gate electrode side wall insulating film;
Forming a polycrystalline silicon film on a part of the active region and the element isolation region so as to be located above the interface between the gate insulating film and the active region;
Removing a portion of the polycrystalline silicon film at both ends in the longitudinal direction of the gate electrode,
Forming an insulating film on the active region in the region where the polycrystalline silicon film has been removed;
It is characterized by having.
[0025]
According to the method of manufacturing a semiconductor device of the present invention, the first sidewall insulating film and the second sidewall insulating film are used without using a special manufacturing device, so that the device can be separated from the gate electrode. The region can be formed in a self-aligned manner. For this reason, the area of the active region of the source region and the drain region can be reduced. Therefore, a semiconductor device having a small junction capacitance can be easily formed. Further, an insulating film is formed on the active region from which a part of the polycrystalline silicon film has been removed. Therefore, a short circuit between the source region and the drain region and a short circuit between the source / drain region and the well region (semiconductor substrate) can be prevented.
[0026]
In one embodiment, the step of forming the polycrystalline silicon film includes:
The method comprises the steps of: depositing a polycrystalline silicon film having a thickness larger than the distance between the gate electrode and the element isolation region on the entire surface; and etching until the polycrystalline silicon film on the gate electrode is eliminated.
[0027]
According to the above embodiment, a semiconductor device having a stacked diffusion layer can be formed without using a special manufacturing apparatus.
[0028]
In one embodiment, the step of forming the polycrystalline silicon film includes the steps of: depositing a polycrystalline silicon film over the entire surface; applying a resist flat on the polycrystalline silicon film; A step of reducing the thickness of the resist so that the insulating film on the gate electrode region is exposed; a step of patterning the resist; and a region of the polycrystalline silicon film near the gate electrode using the resist as a mask. Is performed until the polycrystalline silicon film becomes thinner than the film thickness when the polycrystalline silicon film is deposited.
[0029]
According to the above embodiment, a semiconductor device having a thin stacked diffusion layer in the vicinity of the gate electrode can be formed with good controllability without using a special process device.
[0030]
In one embodiment, after the polycrystalline silicon film is formed, part of the gate electrode region at both ends in the longitudinal direction of the gate electrode region for forming the gate electrode is removed. Forming a contact region for connecting the gate electrode to the shallow well region of the second conductivity type while removing a part of the polycrystalline silicon film; and forming an interlayer insulating film over the entire surface. Depositing the interlayer insulating film on a part of the gate electrode, and removing a part of the interlayer insulating film on the contact region, and forming a contact over the gate electrode and the contact region. Forming a hole and burying a conductive material in the contact hole.
[0031]
According to the above embodiment, a DTMOSFET in which the gate electrode and the shallow well region are short-circuited can be formed with good controllability without using a special process device.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. The semiconductor substrate that can be used in the present invention is not particularly limited, but a silicon substrate is preferable. Further, the semiconductor substrate may have a P-type or N-type conductivity.
[0033]
(Embodiment 1)
The first embodiment provides a semiconductor device with a reduced junction capacitance by reducing the area of the active region of the source and drain regions, and a method for manufacturing the same.
[0034]
First, the configuration of the semiconductor device of the first embodiment will be described with reference to FIGS. 1 (a), 1 (b) and 1 (c). 1A shows a plan layout thereof, FIG. 1B shows a cross section taken along the line BB ′ in FIG. 1A, and FIG. The cross sections taken along the line -C 'are shown.
[0035]
An element isolation region 109 is formed in the semiconductor substrate 101 of the first conductivity type. A gate electrode 103 is formed on the semiconductor substrate 101 with a gate insulating film 102 interposed therebetween. The gate electrode 103 is located on the channel region 130 of the present semiconductor device, and is not located on the first gate electrode portion 1031 made of a semiconductor film doped with the second conductivity type. A second gate electrode portion 1032 made of a semiconductor layer not doped with an impurity is located on a region 120 where a contact hole 116 for an upper wiring (not shown) is provided. On both sides of the gate electrode 103 in a direction perpendicular to the longitudinal direction, a gate electrode side wall insulating film 160 made of a silicon oxide film 106 and a silicon nitride film 107 is formed. The gate electrode side wall insulating film 160 is not limited to this example, and may be any insulating film.
[0036]
On both sides of the gate electrode 103, a semiconductor layer 1121 is stacked above the surface of the semiconductor substrate 101 via a gate electrode side wall insulating film 160. After the impurities are implanted into the stacked semiconductor layers 1121, heat treatment is performed to form the stacked diffusion layers 1121, and the impurities are diffused into the semiconductor substrate 101 by the heat treatment. An in-substrate diffusion layer 1122 is formed. The stacked diffusion layer 1121 and the in-substrate diffusion layer 1122 constitute source / drain regions 112. The stacked diffusion layer 1121 is an example of a conductor.
[0037]
By forming the in-substrate diffusion layer 1122 in this manner, a shallow junction can be formed with good controllability, and the short channel effect can be prevented. In addition, the presence of the stacked diffusion layer 1121 reduces the parasitic resistance of the device and improves the speed of the device.
[0038]
As shown in FIGS. 1C and 2A, the stacked diffusion layer 1121 has a width larger than a distance between the first gate electrode portion 1031 and the element isolation region 109, It is formed over the element isolation region 109. Therefore, the contact area between the contact hole 116 to the source and drain electrodes and the stacked diffusion layer 1121 can be kept large, so that the contact resistance can be reduced. If the stacked diffusion layer 1121 does not exist, the distance between the gate electrode 103 and the element isolation region 109 is very small, so that a contact is provided on the source / drain active region having a small width. This reduces the contact area with the source and drain active regions, and increases the contact resistance.
[0039]
In the first embodiment, since the stacked diffusion layer 1121 having a width larger than the distance between the first gate electrode portion 1031 and the element isolation region 109 is formed, the junction is formed without increasing the contact resistance. Thus, a semiconductor device having a small capacity can be realized.
[0040]
As shown in FIGS. 1A, 1B, and 1C, the alignment accuracy (F / 3) is provided on the gate electrode 103 and the stacked diffusion layer 1121 from both ends in the longitudinal direction of the gate electrode 103. The metal film 114 is formed only over the entire area inside. Note that F is the minimum processing dimension. The metal film 114 is, for example, a high melting point metal film such as tungsten, titanium, titanium nitride, tantalum, a high melting point metal silicide film such as titanium silicide, cobalt silicide, nickel silicide, platinum silicide, or aluminum, copper, Any of these alloys or those obtained by adding impurities such as silicon and palladium to these metals and alloys may be used. Contact holes 116 are formed in the gate electrode 103, the source and drain regions 112 at desired positions for connection with upper wiring (not shown).
[0041]
The distance between the gate electrode 103 and the element isolation region 109 is set to be F / 3 or less, where F is the minimum processing dimension. FIGS. 2A and 2B illustrate the positional relationship between the gate electrodes 103 and 304 and the element isolation regions 109 and 302. The vicinity of the in-substrate diffusion layers 1122 and 3082 in the semiconductor substrates 101 and 301 is enlarged. It was done. FIG. 2A shows a semiconductor device according to the first embodiment, and FIG. 2B shows a semiconductor device disclosed in JP-A-2000-82815, which is a conventional example. In the conventional semiconductor device shown in FIG. 2B, since the gate electrode 304 is formed after forming the element isolation region 302, the element isolation region 302 is formed in a self-aligned manner with respect to the gate electrode 304. Not. Therefore, in consideration of the alignment accuracy (F / 3) of the gate electrode 304 with the element isolation region 302, the distance a between the gate electrode 304 and the element isolation region 302 is a = (b + F / 3 + α). Here, b is the width of the gate electrode side wall insulating film 305. α indicates that even when the maximum misalignment F / 3 occurs and the gate electrode side wall insulating film 305 approaches the element isolation region 302, the gate in the source / drain region 308 is used to make the source / drain region 308 function as an electrode. The minimum distance between the electrode side wall insulating film 305 and the element isolation region 302 is 10 nm or more. If the minimum processing dimension F is set to 180 nm, the width b of the gate electrode side wall insulating film 305 is designed to be 50 nm, and α is set to 30 nm, the distance a between the gate electrode 304 and the element isolation region 302 of the conventional semiconductor device is a = ( b + F / 3 + α) = (50 + 180/3 + 30) = 140 nm. The dimension (hereinafter, referred to as a source / drain active layer width) between the gate electrode sidewall insulating film 305 and the element isolation region 302 in the source / drain region 308 is F / 3 + α = 180/3 + 30 = 90 nm. Is calculated.
[0042]
On the other hand, in the semiconductor device of the first embodiment, which will be described later when a manufacturing method is described, since the element isolation region 109 is formed in a self-aligned manner with respect to the gate electrode 103, There is no need to consider the alignment accuracy of the electrode 103. Therefore, as shown in FIG. 2A, the width of the active layer of the source / drain region 112 can be formed with a minimum width α = 30 nm for the source / drain region 112 to function as an electrode. Specifically, when the thickness of each of the silicon oxide film 106 and the silicon nitride film 107 is set to 10 nm, the width b of the gate electrode side wall insulating film 160 becomes b = 20 nm. Therefore, the distance a between the gate electrode 103 and the element isolation region 109 is a = b + α = 50 nm, and can be formed to have an alignment accuracy of F / 3 (60 nm) or less. As described above, in the semiconductor device of the first embodiment, the active layer width of the source / drain region 112 can be reduced. Therefore, the junction capacitance can be reduced to about 1/3 of the conventional semiconductor device (Japanese Patent Laid-Open No. 2000-82815).
[0043]
Next, a procedure for forming the semiconductor device of the first embodiment will be described with reference to FIGS. 3 to 8, each diagram (a) is a plan layout diagram, and each diagram (b) is a cross-sectional view taken along the line BB ′ of the corresponding diagram (a) and each diagram. (C) is a sectional view taken along the line CC ′ of the corresponding part (a).
[0044]
First, although not shown, impurities are implanted into the semiconductor substrate 101 shown in FIGS. 3A, 3B, and 3C for adjusting a threshold value. Next, as shown in FIGS. 3B and 3C, a gate insulating film 102, a polycrystalline silicon film 103 serving as a gate electrode, a silicon oxide film 104, and a silicon nitride film 105 are sequentially formed on the semiconductor substrate 101. Form. Next, a silicon oxide film 106 and a silicon nitride film 107 are deposited to a thickness of about 10 nm and then etched back to form a first gate electrode side wall insulating film comprising the silicon oxide film 106 and the silicon nitride film 107. 160 is formed. Next, after depositing a silicon oxide film 108 to a thickness of about 30 nm, this is also etched back to form a second gate sidewall insulating film 108.
[0045]
Next, regions other than the region of the semiconductor substrate 101 covered with the silicon nitride film 105, the first gate electrode side wall insulating film 160, and the second gate electrode side wall insulating film 108 shown in FIG. 4A, 4B, and 4C, a groove having a depth of 200 to 700 nm is formed in order to form the element isolation region 109. At this time, since the etching rate of the semiconductor substrate 101 is very high with respect to the silicon oxide films 106 and 108 and the silicon nitride film 107, that is, the etching condition with a large selectivity is used, the silicon nitride film 105 and the silicon oxide film are used. 108 and the like are hardly etched.
[0046]
Next, an oxide film is embedded in the trench by a CVD (chemical vapor deposition) method. Next, the oxide film is polished by CMP (Chemical Mechanical Polishing) using the silicon nitride film 105 on the gate electrode region 103 'as a stopper. Thereafter, the oxide film is etched with hydrofluoric acid until the surface approaches the vicinity of the surface of the semiconductor substrate 101. At this time, the silicon oxide film 108 serving as the second gate electrode side wall insulating film is completely removed, and an active layer (a region defined as α in FIG. 2) serving as a source / drain region is exposed in a later step. Although the upper portion of the silicon oxide film 106 of the first gate electrode side wall insulating film 160 is slightly etched, its width is very small, 10 nm, so that the rate for hydrofluoric acid is reduced by the oxide film 109 embedded in the element isolation region 109. Since it is sufficiently smaller than the silicon oxide film 108 or the silicon oxide film 108, the upper part is slightly removed, and most of it is left as a sidewall. Thus, the element isolation region 109 is formed in a self-aligned manner with respect to the gate electrode region 103 '.
[0047]
Next, as shown in FIGS. 5A, 5B, and 5C, a polycrystalline silicon film is formed by LPCVD (low-pressure chemical vapor deposition) as a material of the source / drain stacked diffusion layer 112 shown in FIG. After the entire surface is formed by the method, anisotropic etch back is performed to form a polycrystalline silicon film sidewall 110. The deposition thickness of the polycrystalline silicon film and the etch-back conditions are adjusted so that the width of the sidewall 110 is larger than the width of the active layer of the source and drain regions 112. When forming the sidewall 110 made of the polycrystalline silicon film, it is important to form the natural oxide film so as not to grow on the interface with the surface of the silicon substrate 101. When a natural oxide film grows at the interface between the active layer surfaces of the source and drain regions of the semiconductor substrate and the deposited polycrystalline silicon film, it becomes a donor or an acceptor in the polycrystalline silicon film by ion implantation in a later step. After the impurities are introduced, when the impurities are thermally diffused into the semiconductor substrate by heat treatment to form a junction, the natural oxide film acts as a diffusion barrier for the impurities, thereby inhibiting uniform impurity diffusion. Therefore, the junction depth of the source and drain regions becomes non-uniform, which causes the transistor characteristics to vary.
[0048]
In the first embodiment, a polycrystalline silicon film is formed by an LPCVD (low-pressure vapor deposition) apparatus including a preliminary evacuation chamber (not shown), a nitrogen purge chamber whose dew point is always kept at −100 ° C. or lower, and a deposition furnace. Since 110 is formed, it is possible to grow polycrystalline silicon film 110 so that a natural oxide film does not grow.
[0049]
Specifically, immediately before forming the polycrystalline silicon film 110, the wafer is washed with a hydrofluoric acid-based solution to remove the natural oxide film once, and then transported to the preliminary evacuation chamber. Before this transfer, the preliminary vacuum exhaust chamber is evacuated once from the atmosphere and then replaced with a nitrogen atmosphere. Next, the wafer is transferred to a nitrogen purge chamber where the dew point is kept at -100 ° C or lower. Here, the role of the preliminary evacuation chamber is to prevent the atmosphere during transport from being mixed into the nitrogen purge chamber. If the atmosphere is mixed into the nitrogen purge chamber even with a slight amount of atmosphere, it takes several days to recover the atmosphere to -100 ° C. or lower, which greatly deteriorates the throughput. The role of the nitrogen purge chamber is to completely remove water molecules adsorbed on the wafer surface by nitrogen purge. Experiments have confirmed that water molecules adsorbed on the wafer surface can be completely removed by nitrogen purge.
[0050]
In a normal LPCVD apparatus, such water molecules that cannot be completely removed are transported to a deposition furnace while being adsorbed on the wafer surface. Since a normal polycrystalline silicon film is formed at a temperature of about 550 ° C. to 650 ° C., when transporting a wafer to a deposition furnace maintained at this temperature, water molecules adsorbed and oxygen in the atmosphere Reacts with the silicon wafer to grow a natural oxide film before forming a polycrystalline silicon film. As a result, a natural oxide film grows at the interface between the sidewall 110 made of a polycrystalline silicon film and the semiconductor substrate 101. However, in the LPCVD apparatus of the first embodiment, as described above, the adsorbed water molecules are completely removed in the nitrogen purge chamber where the dew point is always kept at −100 ° C. or lower, and then transported to the deposition furnace. Since the system is used, the polycrystalline silicon film 110 can be formed without growing a natural oxide film. Therefore, the impurity is smoothly diffused into the semiconductor substrate 101, and a uniform junction between the source and drain regions can be formed with good controllability.
[0051]
Next, as shown in FIGS. 6A, 6B and 6C, the silicon nitride film 105 and the silicon oxide film 104 shown in FIG. 5B are removed. At this time, the silicon nitride film 107 forming the gate electrode side wall insulating film 160 is also slightly etched, but since the width is as small as about several tens of nm, only the upper portion is slightly etched, and most of the silicon nitride film 107 is mostly etched. Remains as.
[0052]
Next, in order to prevent a short circuit between the source electrode and the drain electrode due to the polycrystalline silicon film 110, the gate electrode region 103 'is formed at both ends in the longitudinal direction using a known lithography technique and processing technique. A part of the polycrystalline silicon film 110 located away from the channel region 130 is removed. At this time, only the polycrystalline silicon film 110 in that region needs to be removed. However, in the first embodiment, both ends of the gate electrode region 103 ′ are partially removed by F / 3 in the longitudinal direction of the gate electrode. Removed. This will be described below.
[0053]
The layout for removing the polycrystalline silicon film 110 should be performed in consideration of the fact that a misalignment of approximately F / 3 occurs with respect to the gate electrode region 103 '. This is to prevent the polycrystalline silicon film 110 from remaining due to misalignment. As described above, the photoresist for removing the polycrystalline silicon film 110 is formed in such a manner that the gate electrode is inwardly extended from both ends of the gate electrode region 103 'in the longitudinal direction of the gate electrode region 103' by about F / 3. The layout needs to be set so that a region to be removed is set in the longitudinal direction outside of the region 103 '. Therefore, as a result, both ends of the gate electrode region 103 'are removed by about F / 3. Further, since both ends of the gate electrode region 103 'are etched, there is no particular deterioration in device characteristics. In this manner, the surfaces of the semiconductor substrate 101 in the regions 140a and 140b where the polycrystalline silicon film 110 has been removed and the regions 145a and 145b where both ends of the gate electrode region 103 ′ have been removed are exposed.
[0054]
Next, a resist 150 is patterned to implant a second conductivity type impurity into the gate electrode region 103 'and the source and drain regions, and a second conductivity type impurity 111 is implanted using the resist 150 as a mask. At this time, in consideration of the diffusion of the impurity 111 in the horizontal direction, the resist 150 is patterned so that the impurity is implanted into a region about 100 nm to 200 nm inside both ends of the channel region 130 with respect to the longitudinal direction of the gate electrode. . Next, ions of the second conductivity type impurity 111 are implanted to form the source and drain regions 112. In the first embodiment, the gate electrode region 103 'is doped simultaneously with the doping of the polysilicon film sidewall 110 for forming the source and drain regions 112.
[0055]
The thickness of the gate electrode region 103 'made of the polycrystalline silicon film was 200 to 250 nm, and the height of the side wall 110 made of the polycrystalline silicon film near the gate electrode was 200 to 300 nm. For this reason, the ion implantation conditions are as follows: for an N-channel transistor, phosphorus ions are converted into 2 × 10 ^Fifteen From 1 × 10 ¹⁶ / Cm ² The injection was performed at a moderate amount. As for the P-channel transistor, boron ions are converted to energy of about 10 KeV to about 30 KeV by 2 × 10 ^Fifteen From 1 × 10 ¹⁶ / Cm ² The injection was performed at a moderate amount. Here, although not shown, a screen oxide film of 5 to 30 nm may be formed on the entire surface before impurity implantation for the purpose of removing contaminants (contamination) at the time of impurity implantation. The energy of the impurity implantation is set so that the impurity is implanted only into the polycrystalline silicon film side wall 110.
[0056]
Next, as shown in FIGS. 7B and 7C, in order to activate the impurity 111 implanted in the gate electrode region 103 ′ and the sidewall 110 and diffuse the impurity 111 into the silicon substrate 101, And heat treatment. Thus, source / drain regions 112 composed of the stacked diffusion layers 1121 and the in-substrate diffusion layers 1122 are formed. The conditions of the heat treatment are as follows: a heat treatment at a temperature of about 800 ° C. to 950 ° C. for about 10 minutes to 60 minutes, or a rapid heat treatment at a temperature of about 900 ° C. to 1100 ° C. for about 10 seconds to 60 seconds. At the same time as activating 111, a junction is formed by solid-phase diffusion from sidewall 110 made of a polycrystalline silicon film into silicon substrate 101. In this way, impurity ions 111 are implanted into sidewalls 110 made of a polycrystalline silicon film stacked higher than channel region 130, and impurities are solid-phase diffused from sidewalls 110 into silicon substrate 101. To form a bond. That is, since the impurity 111 is not directly injected into the silicon substrate 101, a junction leak current due to a crystal defect does not occur, and the junction leak current can be reduced. Here, as a guide of the heat treatment conditions, it is necessary to diffuse the junction positions formed in the source and drain regions 112 in the horizontal direction to such an extent that the junction positions are not separated from the gate electrode region 103 ′ (channel region 130). Specifically, it is necessary to diffuse the gate electrode side wall insulating film 160 composed of the silicon oxide film 106 and the silicon nitride film 107 in the lateral direction beyond the width thereof. In order to improve the performance of the transistor, the junction depth is made as small as possible to suppress the short channel effect, and the source and drain regions 112 are formed so as not to be offset with respect to the gate electrode in order to obtain a high drive current. Need to be formed. For example, in the case where the width of the gate electrode sidewall insulating film 160 is 20 nm, when impurity diffusion of the N-channel transistor and the P-channel transistor is performed by a single heat treatment, the diffusion is performed at about 800 ° C. for about 60 minutes to about 875 ° C. for about 10 minutes. Has been found to be optimal. Thus, the in-substrate diffusion layer 1122 and the first gate electrode portion 1031 doped with impurities are formed. Here, the first gate electrode portion 1031 and the in-substrate diffusion layer 1122 are formed only in the channel region 130, and the regions 120 other than the channel region 130 are not doped with impurities. The stack layer 110 remains. The first gate electrode portion 1031 and the second gate electrode portion 1032 constitute the gate electrode 103. Therefore, in the region 120, almost no capacitance is generated between the gate electrode 103 and the source / drain region 112, so that the capacitance associated with the gate electrode 103 and the source / drain region 112 is smaller than in the conventional example. can do.
[0057]
Next, as shown in FIG. 7B, a silicon oxide film 113 having a thickness of about 50 to 100 nm is formed by a CVD method. Next, in order to prevent a short circuit between the source electrode and the drain electrode in the previous step, the active layer regions 140a and 140b exposed by removing the polycrystalline silicon film 110 and both ends of the gate electrode region 103 'are removed. The silicon oxide film 113 is patterned so that the exposed active regions 145a and 145b are completely covered with the silicon oxide film 113.
[0058]
Specifically, using a well-known lithography technique and a processing technique, the gate electrode 103 is positioned F / 3 inward from both ends 141a and 141b in the longitudinal direction of the gate electrode 103 in a direction perpendicular to the longitudinal direction of the gate electrode 103. The silicon oxide film 113 in the region inside 103 is removed. That is, the silicon oxide film 113 is formed so as to overlap the gate electrode 103 from both ends 141a and 141b in the longitudinal direction of the gate electrode 103 to F / 3, which is the alignment accuracy in the longitudinal direction inside the gate electrode 103. Thus, silicon oxide film 113 is laid out. For this reason, even if the misalignment occurs in the longitudinal direction of the gate electrode 103, the active regions 140a and 140b and the active regions 145a and 145b can be reliably covered with the silicon oxide film 113.
[0059]
This step is a very important step in this embodiment. FIGS. 9A and 9B illustrate how the gate electrode 103, the source and drain regions 112, and the semiconductor substrate 101 are short-circuited when the silicon oxide film 113 is not used. FIG. 9A is a plan layout view when the silicon oxide film 113 is not formed in FIG. 7A, and FIG. 9B is a view showing the source and drain regions 112 in the longitudinal direction of the gate electrode in FIG. 9A. FIG. 7 is a cross-sectional view taken along line BB ′ along the active layer region of FIG. As shown in FIGS. 9A and 9B, since the active regions 140a and 140b and the active regions 145a and 145b are not covered by the silicon oxide film 113, the metal film 114 becomes active regions 140a, 140b and 145a. , 145b. Therefore, for example, as shown in FIG. 9B, the source and drain regions 112 and the semiconductor substrate 101 in the active region 140a, and the gate electrode 103 and the semiconductor substrate 101 in the active region 145b are formed by the metal film 114, respectively. I will short out.
[0060]
In the semiconductor device of the first embodiment, since the gate electrode 103 is formed in self-alignment with the element isolation region 109, such active regions 140a and 140b are always formed around the gate electrode 103. . For this reason, unlike the conventional example in which element isolation regions are formed at both ends in the longitudinal direction of the gate electrode, such active regions 140a, 140b, 145a, and 145b are formed at both ends of the gate electrode 103 by a silicon oxide film. If not covered with an insulating film such as 113, the gate electrode 103 and the source / drain regions 112 are short-circuited to the semiconductor substrate 101 by the metal film 114.
[0061]
By forming the silicon oxide film 113 as described above, the metal film 114 is not formed on the surfaces of the active regions 140a and 140b and the active regions 145a and 145b. Therefore, the gate electrode 103 and the semiconductor substrate 101 are not short-circuited, and the source / drain region 112 and the semiconductor substrate 101 are not short-circuited.
[0062]
Next, by a well-known salicide process, a titanium silicide film 114 is selectively formed as an example of a refractory metal film on the gate electrode 103 and the source and drain regions 112 where the silicon oxide film 113 is not formed. I do. In this embodiment, the titanium silicide film 114 made of titanium metal was used as the high melting point metal film. However, the present invention is not limited to this. As another high melting point metal film, a high melting point film using cobalt, nickel, platinum or the like may be used. good. Further, a high melting point metal film such as tungsten, titanium, titanium nitride, tantalum, or the like, or aluminum, copper, or an alloy thereof, or a material in which an impurity such as silicon or palladium is added to these metals or alloys may be used. .
[0063]
Next, as shown in FIGS. 8A, 8B and 8C, after an interlayer insulating film 115 is formed by a known method, a contact hole 116 is opened at a predetermined position of the interlayer insulating film 115. . Although not shown, if the contact plug and the upper wiring are formed by a known method, the semiconductor device of the first embodiment is completed.
[0064]
As described above, in the method of manufacturing a semiconductor device according to the first embodiment, the element isolation region 109 is formed in a self-aligned manner with respect to the gate electrode 103. For this reason, as shown in FIG. 2A, the distance a between the gate electrode 103 and the element isolation region 109 can be set to be equal to or smaller than the alignment deviation (F / 3). That is, as in the conventional example shown in FIG. 2B, it is necessary to lay out the positions of the gate electrode 304 and the element isolation region 302 in consideration of the misalignment (F / 3) of the element isolation region 302 with respect to the gate electrode 304. There is no. Therefore, in the first embodiment, as compared with the conventional example shown in FIG. 2B, the width of the active layer region of the source / drain region 112 (the upper end of the diffusion layer 1122 in the substrate, which is continuous with the stacked diffusion layer 1121). Width) can be reduced to about F / 3, so that the junction capacitance associated with the source / drain regions 112 can be reduced. Specifically, when the minimum processing dimension (corresponding to the design rule and the technology node) F is 180 nm, in the conventional semiconductor device shown in FIG. 2B, the alignment deviation (F / 3) is about 60 nm, Assuming that the width α of the active region (diffusion layer in the substrate) through which a minimum necessary current flows to make the drain region 308 function as an electrode is 30 nm, the width of the active region (diffusion layer in the substrate) 3082 of the source / drain region 308 Is required to be approximately F / 3 + α = 90 nm, but in the semiconductor device of the first embodiment of the present invention, as shown in FIG. 2A, the minimum required for the source / drain region 112 to function as an electrode. The active layer region (diffusion layer in the substrate) 1122 of the source / drain region 112 can be formed with the width α of the active layer region in which the current flows is 30 nm. Therefore, in the semiconductor device according to the first embodiment of the present invention, a semiconductor device having an active region width a of the source / drain region 112 which is １ ／ of the conventional example can be realized. Therefore, the junction capacitance associated with the source and drain regions 112 can be reduced to about 1/3 as compared with the conventional example.
[0065]
On the other hand, in the method in which the element isolation region is formed in a self-aligned manner with respect to the gate electrode, as described above, the short-circuit between the gate electrode and the semiconductor substrate, and the source / drain region and the semiconductor substrate at both ends of the gate electrode. Is short-circuited, but by covering both ends of the gate electrode 103 with the silicon oxide film 113, this problem can be prevented.
[0066]
At present, many integrated circuits in which a logic circuit and an analog circuit are mixed are produced. In the analog circuit, a protective film for preventing the formation of a metal film on the gate electrode is formed. A mask for forming the protective film and the silicon of the semiconductor device of the first embodiment constituting the logic circuit are formed. Since it can also serve as a mask for forming the oxide film 113, the number of masks does not increase. Therefore, an integrated circuit in which a logic circuit including the semiconductor device of the first embodiment and an analog circuit are mixed can be formed without increasing the cost. Furthermore, these manufacturing steps can be manufactured without using a special process device.
[0067]
(Embodiment 2)
Second Embodiment Similar to the semiconductor device of the first embodiment, the second embodiment provides a semiconductor device having a structure in which the area of the active region of the source and drain regions is reduced to reduce the junction capacitance, and a method of manufacturing the same. It is. In addition, the present invention provides a semiconductor device in which the capacitance between the gate electrode and the source and drain electrodes is reduced as compared with the semiconductor device of the first embodiment, and a method for manufacturing the same.
[0068]
First, the configuration of the semiconductor device according to the second embodiment will be described with reference to FIGS. 14 (a), (b), and (c). FIG. 14A shows a planar layout thereof, FIG. 14B shows a cross section in the BB ′ direction in FIG. 14A, and FIG. The cross sections in the direction C ′ are shown.
[0069]
The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment only in the structure of the stacked diffusion layer of the source and drain regions and the position where the contact hole for the upper wiring to the source and drain regions is provided. The other structure is the same. Therefore, here, the structure of the source and drain stacked diffusion layers will be mainly described. Note that the same components as those of the semiconductor device of the first embodiment have the same reference numbers as those of the semiconductor device of the first embodiment, and a detailed description thereof will be omitted.
[0070]
As shown in FIG. 14C, the stacked diffusion layer 1711 of the source / drain region 171 is formed in the source / drain active layer region (the stacked diffusion layer 1711 of the diffusion layer 1712 in the substrate) similarly to the semiconductor device of the first embodiment. Over the element isolation region 109. In the semiconductor device of the second embodiment, the region 180 near the gate electrode 103 in the stacked diffusion layer 1711 is thinner than in the other region 181, and the width of the region 180 near the gate electrode 103 is different from that in the other region 181. It is almost the same as the thickness of the diffusion layer 1711. As described above, the semiconductor device according to the second embodiment has a smaller area in which the stacked diffusion layer 1711 of the source / drain region 171 faces the gate electrode 103 than the semiconductor device according to the first embodiment. Therefore, the capacitance associated with the gate electrode 103 and the source / drain region 171 can be reduced.
[0071]
Next, a procedure for manufacturing the semiconductor device of the second embodiment will be described with reference to FIGS. 10 (a), (b) and (c) to FIGS. 14 (a), (b) and (c). In FIGS. 10 (a), (b), (c) to FIGS. 14 (a), (b), (c), each diagram (a) is a diagram showing a planar layout, and each diagram (b) Is a cross-sectional view taken along the line BB 'of the corresponding sectional view (a), and each figure (c) is a cross-sectional view taken along the line CC' of the corresponding figure (a). is there.
[0072]
The method of manufacturing the semiconductor device of the second embodiment is the same as that of the first embodiment except for the method of manufacturing the stacked diffusion layers of the source and drain regions. Steps after the formation of the insulating film will be described.
[0073]
First, as shown in FIGS. 10B and 10C, a gate insulating film 102, a gate electrode region 103 ', a silicon oxide film 106, and a silicon nitride film are formed on a semiconductor substrate 101 in the same manner as in the manufacturing method of the first embodiment. A gate electrode side wall insulating film 160 composed of the film 107 and an element isolation region 109 are formed.
[0074]
Next, a polycrystalline silicon film 170 for forming a stacked diffusion layer is deposited to a thickness of about 50 to 200 nm using a method in which a natural oxide film does not grow at the interface between the polycrystalline silicon film 170 and the surface of the semiconductor substrate 101. .
[0075]
Next, after a resist 165 is applied to the entire surface, a developing process is performed until the polycrystalline silicon film 170 on the gate electrode region 103 ′ is exposed. The thickness of the gate electrode region 103 'is 200 to 300 nm, and the thickness of the silicon nitride film 105 on the gate electrode 103' is 50 to 200 nm. There is a step of 250 to 500 nm with respect to the location. For this reason, by setting the development processing conditions (time-critical parameters) of the resist 165 to appropriate conditions, the resist 165 is left at a position other than the position where the gate electrode region 103 ′ is formed. The resist 165 can be patterned.
[0076]
Here, the patterning of the resist 165 will be described in detail. In order to apply the resist 165 flat and hard to be affected by the step of the underlayer, a low viscosity (4.5 cp) chemically amplified negative resist TDUR-N908 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) is used as the resist 165. After applying at a low rotation speed of 1000 to 3000 rpm, pre-baking (baking after application) was performed at 80 to 130 ° C. for 90 seconds. Then, although not shown, the resist 165 is applied flat. If the viscosity of the resist 165 is 5 cp or less, the resist 165 can be applied evenly without being affected by the step of the underlayer. However, it is preferable to use a resist having as low a viscosity as possible from the viewpoint of flattening. Next, the resist is developed (etched) with a 0.1 N aqueous solution of tetramethylammonium hydroxide (TMAH, manufactured by Sumitomo Chemical Co., Ltd.), which is a developing solution having a concentration lower than that used in a normal developing process. . The reason why the concentration is set lower than usual is that the resist is patterned with good controllability by reducing the etching rate. Since the etching rate of the developing solution with respect to the resist 165 is 9 nm per minute, the etching is controlled until the polycrystalline silicon film 170 on the gate electrode region 103 'is exposed by controlling the etching time, as shown in FIG. Thus, patterning is performed so that the resist 165 remains at a portion other than the portion where the gate electrode region 103 'is formed. In the second embodiment, the developing process is used for etching the resist 165. However, the present invention is not limited to this, and a dry etching method may be used. However, the development process is an effective method because the cost is lower than that of dry etching because the same device as the coating device can be used and a vacuum device is not used.
[0077]
Next, as shown in FIGS. 11B and 11C, using the resist 165 as a mask, the polycrystalline silicon film 170 on the exposed gate electrode region 103 ′ is etched to a portion near the surface of the resist 165. The reason that this etching is kept near the surface of the resist 165 is that the silicon nitride film 107 forming the gate electrode sidewall insulating film 160 is removed when the silicon nitride film 105 is removed in a later step. This is to prevent it. For this etching, RIE (Reactive Ion Etching) that can be processed anisotropically was used. However, the present invention is not limited to this, and a chemical dry etching method may be used. Next, the silicon nitride film 105 is removed. At this time, the silicon nitride film 107 constituting a part of the gate electrode side wall insulating film 160 is also slightly etched, but most of its surface (in this case, most of the side surfaces) is covered with the polycrystalline silicon film 170. And the width is as small as about several tens of nm, the upper portion is only slightly etched, and most of the silicon nitride film 107 remains as a part of the gate electrode sidewall insulating film 160.
[0078]
Next, as shown in FIGS. 12A, 12B and 12C, the polycrystalline silicon film 170 around the gate electrode side wall insulating film 160 is removed to form a thin region near the gate electrode region 103 '. A polycrystalline silicon film 170 corresponding to the stacked diffusion layer having 180 is formed. The etching conditions were set so that the thickness of the polycrystalline silicon film 170 in the region 180 was equal to or smaller than that at the time of deposition. The width of this region 180 is equal to the thickness of the polycrystalline silicon film 170 initially deposited due to the feature of the LPCVD method as a forming method. This is because the polycrystalline silicon film 170 formed by the LPCVD method is very excellent in step coverage, so that the polycrystalline silicon film 170 formed on the gate electrode side wall insulating film 160 and the polycrystalline silicon film 170 formed on the element isolation region 109 respectively. The thickness is almost equal, and the polycrystalline silicon film 170 on the gate electrode side wall insulating film 160 is etched in the direction in which the gate electrode side wall insulating film 160 extends over the entire thickness direction to form the region 180. Because you do. Next, the resist 165 is removed.
[0079]
Next, as shown in FIGS. 13A, 13B, and 13C, similarly to the first embodiment, in order to prevent a short circuit between the source region and the drain region, well-known lithography technology and processing technology are used. Is used to remove part of the polycrystalline silicon film 170 formed at both ends in the longitudinal direction of the gate electrode region 103 '. At the same time, patterning of the polycrystalline silicon film 170 in a direction perpendicular to the longitudinal direction of the gate electrode region 103 'is performed at the same time. At this time, only the polycrystalline silicon film 170 in that region may be removed. However, in the semiconductor device of the second embodiment, as in the semiconductor device of the first embodiment, one end of the gate electrode region 103 'is removed. The portion is also removed by about F / 3 in the longitudinal direction of the gate electrode region 103 '. This will be described below.
[0080]
The layout for removing the polycrystalline silicon film 170 should be performed in consideration of the fact that an alignment deviation of about F / 3 always occurs with respect to the gate electrode region 103 '. In order to prevent the polycrystalline silicon film 170 from remaining due to this alignment shift, a photoresist for removing the polycrystalline silicon film 170 is formed in advance at both ends of the gate electrode region 103 'in the longitudinal direction of the gate electrode region 103'. It is necessary to lay out such that a region to be removed in the longitudinal direction outside of the gate electrode region 103 ′ is set from a plane which is approximately F / 3 inward from the gate electrode region 103 ′. By doing so, both ends of the gate electrode region 103 'are removed by about F / 3. In addition, since both ends of the gate electrode region 103 'are etched, there is no particular deterioration in device characteristics.
[0081]
Next, as shown in FIGS. 14A, 14B and 14C, similarly to the semiconductor device of the first embodiment, the gate electrode 103, the diffusion layer 1712 in the substrate, the high-melting-point silicide film 114, and the interlayer insulating film are formed. A film 115 and a contact hole 116 are formed. Although not shown, the semiconductor device of this embodiment is completed by forming the upper wiring.
[0082]
As described above, in the method for manufacturing a semiconductor device according to the second embodiment, the gate electrode 103 and the source / drain regions 171 are formed without using a special process device as compared with the semiconductor device according to the first embodiment. A semiconductor device with a reduced capacitance can be manufactured.
[0083]
In the semiconductor device of the first embodiment shown in FIG. 1, a stacked diffusion layer 1121 having a width equal to or larger than the deposition thickness of the polycrystalline silicon film 110 cannot be obtained. However, in the second embodiment shown in FIG. Patterning of the polycrystalline silicon film 170 in a direction perpendicular to the longitudinal direction of the film 103 can be freely performed by lithography. In the semiconductor device of the first embodiment shown in FIG. 1, the width of the stacked diffusion layer 1121 of the source / drain regions 112 is limited to about the thickness of the deposited polycrystalline silicon film 110. In order to prevent an increase in contact resistance due to a decrease in the contact area between the stacked diffusion layer 1121 and the contact, the contact hole 116 needs to be formed close to the gate electrode 103. However, in the semiconductor device according to the second embodiment shown in FIG. 14, the width of the stacked diffusion layer 1711 of the source / drain regions 171 can be freely laid out, so that the contact hole 116 is larger than in the semiconductor device of the first embodiment. Can be formed at a position sufficiently distant from the gate electrode 103 and at a desired position. Therefore, the capacitance associated with the gate electrode 103 and the source and drain regions 171 can be reduced.
[0084]
In particular, when a series transistor is formed, the semiconductor device of the second embodiment has a greater effect than the semiconductor device of the first embodiment. It is described below.
[0085]
FIGS. 15A and 15B are cross-sectional views in a direction perpendicular to the longitudinal direction of the gate electrode when a series transistor is formed. FIG. 15A shows the semiconductor device of the first embodiment, and FIG. 15B shows the semiconductor device of the second embodiment. As shown in FIG. 15A, in the semiconductor device according to the first embodiment, the width of the polycrystalline silicon film 110 (see FIG. 5) cannot be made larger than the deposition thickness, so that the distance between the adjacent gate electrodes 103, 103 is increased. Is larger than twice the deposited film thickness of the polycrystalline silicon film 110, the stacked diffusion layers 1121 and 1121 are not directly connected as shown in FIG. Connection with the upper wiring composed of Therefore, for example, it is necessary to further use a metal wiring to connect the adjacent drain regions (electrodes) 112, 112. On the other hand, in the semiconductor device of the second embodiment shown in FIG. 15B, since the polycrystalline silicon film 170 (see FIG. 12) can be laid out freely, for example, the adjacent transistor can be used without using the upper wiring. The drain regions 171 and 171 can be connected. Therefore, since the upper wiring does not have to be used for connecting the adjacent drain regions 171, 171 and the degree of freedom is improved, a fine semiconductor element can be formed.
[0086]
(Embodiment 3)
The semiconductor device according to the third embodiment is basically similar in structure to the semiconductor device according to the first embodiment, but has a dynamic threshold (DT) in which a gate electrode and a well region are connected. The difference is that the current driving capability is improved as a MOSFET.
[0087]
First, the configuration of the semiconductor device according to the third embodiment will be described with reference to FIGS. 16 (a), (b), and (c). The semiconductor device of the third embodiment is obtained by electrically connecting the gate electrode and the shallow well region of the semiconductor device of the first embodiment. FIG. 16A shows a planar layout thereof, FIG. 16B shows a cross section in the BB ′ direction in FIG. 16A, and FIG. The cross sections in the direction C ′ are shown. Note that, in the plan layout diagram of FIG. 16A, in order to clarify the positional relationship between the contact hole 217 and the stacked diffusion layer 2141 of the gate electrode 205, the source and drain regions 214, the contact regions 240a and 240b, etc. The metal wiring 219 and the metal plug 218 are omitted.
[0088]
In the semiconductor substrate 201 of the first conductivity type, a deep well region 202 of the second conductivity type and a shallow well region 203 of the first conductivity type are formed, and the shallow well region 203 is separated by an element isolation region 212 for each element. Electrically isolated. Here, the first conductivity type means N-type or P-type. When the first conductivity type is N-type, the second conductivity type means P-type. When the first conductivity type is P-type, The second conductivity type means N-type.
[0089]
In a part of the shallow well region 203, a gate electrode 205 made of a semiconductor film doped to the second conductivity type is formed via a gate insulating film 204. On the shallow well region 203, contact regions 240a and 240b located at both longitudinal ends of the gate electrode 205 are formed. The gate insulating film 204 and the gate electrode are not present on the contact regions 240a and 240b. The contact regions 240a and 240b connect the gate electrode 205 and the shallow well region 203. The first conductive type high concentration diffusion layer regions 213a and 213b are formed to include the contact regions 240a and 240b, respectively, and the first conductive type high concentration diffusion layer regions 213a and 213b are shallow with the metal plug 218. Ohmic connection can be made with the well region 203. Here, in FIG. 16B, the high concentration diffusion layer regions 213a and 213b are formed so as to cover the entire contact regions 240a and 240b. However, the present invention is not limited to this, and at least the metal plug 218 is formed. May be formed in a region in contact with the shallow well region 203. The reason is that the gate electrode 205 and the shallow well region 203 are connected via the metal plug 218, but the high concentration diffusion layer is formed so that the entire region where the metal plug 218 and the shallow well region 203 are in contact does not form a Schottky junction. This is because the regions 213a and 213b need only be formed. The concentration of the impurity of the first conductivity type in the high concentration diffusion layer regions 213a and 213b is 1 × 10 ²⁰ ~ 1 × 10 ²¹ / Cm ³ It is about. Further, the first conductivity type impurity for forming the high concentration diffusion layer regions 213a and 213b is not doped into the gate electrode 205. Therefore, since the second conductivity type impurity in the gate electrode 205 and the first conductivity type impurity do not cancel each other and the effective channel width does not decrease, it is possible to prevent a reduction in drive current.
[0090]
In order to connect the gate electrode 205 and the source / drain regions 214 to the upper metal wiring 219, a metal plug 218 is formed by opening a contact hole at a predetermined position of the interlayer insulating film 216. At this time, a contact hole for connecting the gate electrode 205 and the upper metal wiring 219 is formed so as to straddle the gate electrode 205 and the contact regions 240a and 240b as shown in FIG. A metal plug 218 is embedded in the contact hole. Thus, the gate electrode 205 and the upper metal wiring 219 can be connected, and the gate electrode 205 and the shallow well region 203 can be reliably connected via the metal plug 218. The gate electrode 205 and the shallow well region 203 are connected at two contact regions 240a and 240b at both ends in the longitudinal direction of the gate electrode 205. Therefore, the voltage applied to the gate electrode 205 can be transmitted to the shallow well region 203 from two locations more efficiently than in the case where the gate electrode and the shallow well region are connected at one location. Voltage delay is reduced and high-speed operation becomes possible.
[0091]
The source and drain regions 214 are adjacent to the gate electrode side wall insulating film 210 and almost all of them are located above the interface between the gate insulating film 204 and the surface of the shallow well region 203 as in the semiconductor device of the first embodiment. are doing. The source / drain region 214 includes a stacked diffusion layer 2141 located above the interface between the gate insulating film 204 and the surface of the shallow well region 203, and a diffusion layer in a shallow well region 203 (hereinafter referred to as a “diffusion layer”). , 2142). On the gate electrode 205 and the stacked diffusion layer 2141, a metal film 215 is formed over the entire region inside by F / 3 from both ends in the longitudinal direction of the gate electrode 205. Here, F is the minimum processing size. The metal film 215 is, for example, a high melting point metal film such as tungsten, titanium, titanium nitride, and tantalum; a high melting point metal silicide film such as titanium silicide, cobalt silicide, nickel silicide, and platinum silicide; or aluminum, copper, Any of these alloys, or those obtained by adding impurities such as silicon and palladium to these metals and alloys may be used.
[0092]
The distance between the gate electrode 205 and the element isolation region 212 is set to be F / 3 or less, where F is the minimum processing dimension. Therefore, in the semiconductor device of the third embodiment, the activation of the in-substrate diffusion layer 2142 of the source / drain region 214 is the same as in the semiconductor device of the first embodiment described with reference to FIGS. The layer width can be reduced. Therefore, the junction capacitance can be reduced to about 1/3 of the junction capacitance of the semiconductor device of the conventional example (Japanese Patent Laid-Open No. 2000-82815).
[0093]
In the DTMOSFET in which the gate electrode 205 is connected to the shallow well region 203 as in the semiconductor device of the third embodiment, the effect of reducing the capacitance (active layer capacitance) of the in-substrate diffusion layer 2142 in the source / drain region 214 is obtained. Is very large. Because the DTMOS connects the gate electrode 205 and the shallow well region 203, when a voltage is applied to the gate electrode 205, the source region (electrode) 214 and the shallow well region 203, and the drain region (electrode) Junction capacitance is generated between the shallow well region 203 and the shallow well region 203, respectively. In particular, twice the capacitance between the source electrode 214 and the shallow well region 203 occurs between the drain electrode 214 and the shallow well region 203 due to the Miller effect during the switching operation of the transistor. This is, in total, three times the junction capacitance of a non-DTMOS regular structure transistor. Therefore, it is very important for DTMOS to reduce the junction capacitance, that is, to reduce the junction area, for increasing the speed of the device.
[0094]
Next, a method for manufacturing the semiconductor device of the third embodiment will be described with reference to FIGS. 17 to 25, each diagram (a) is a diagram showing a planar layout, and each diagram (b) is a cross-sectional view taken along the line BB 'of the corresponding diagram (a). , Each drawing (c) is a cross-sectional view taken along the line CC ′ of the corresponding drawing (a).
[0095]
First, as shown in FIGS. 17B and 17C, a second conductive type deep well region 202 and a first conductive type shallow well region 203 are formed in a semiconductor substrate 201. At this time, the impurity concentration near the surface of the shallow well region 203 is adjusted so as to obtain a desired threshold voltage. Next, a gate insulating film 204, a polycrystalline silicon film 205 'serving as a gate electrode region, a silicon oxide film 206, and a silicon nitride film 207 are sequentially formed on the shallow well region 203, and thereafter, by photolithography and etching. The gate electrode region 205 'and the like are patterned. Next, after depositing a silicon oxide film 208 of about 10 nm and a silicon nitride film 209 of about 10 nm, the first gate electrode side wall insulating film 210 is formed by etching back. Next, after depositing a silicon oxide film 211 for a second gate sidewall insulating film to a thickness of about 30 nm, this is also etched back to form a second gate sidewall insulating film 211.
[0096]
Next, as shown in FIGS. 18B and 18C, a region of the semiconductor 201 covered with the silicon nitride film 207, the first gate electrode side wall insulating film 210, and the second gate electrode side wall insulating film 211. The region of the semiconductor substrate 201 where the other surface is exposed is etched to form a groove of 300 to 700 nm. At this time, the bottom of the groove is located between the shallow well region 203 and the deep well region 202, and the shallow well region 203 can be completely separated by the groove, and the deep well region 202 is etched so as not to be separated by the groove. Conditions are set. The etching conditions are such that the etching rate of the semiconductor substrate 201 is very high with respect to the silicon oxide film or the silicon nitride film, that is, the etching condition has a large selectivity. Therefore, the silicon nitride film 207 and the silicon oxide film 208 are hardly etched. Next, an element isolation region 212 is formed by embedding a silicon oxide film in the groove by the CVD method. Next, the silicon oxide film is polished by CMP (Chemical Mechanical Polishing) using the silicon nitride film 207 on the gate electrode 205 as a stopper. Thereafter, the silicon oxide film is etched with hydrofluoric acid until the surface of the silicon oxide film approaches the vicinity of the surface of the semiconductor substrate 201. At this time, the silicon oxide film 211 serving as the second gate electrode side wall insulating film is completely removed, and the active layer in the region where the silicon oxide film 211 was located is exposed. Part of the active layer will be part of the source and drain regions in a later step. Although the upper portion of the silicon oxide film 208, which is a part of the first gate electrode side wall insulating film 210, is slightly etched, its width is as small as 10 nm. Since it is sufficiently smaller than the film or the silicon oxide film 211, only the upper portion is slightly removed and not all is lost. Thus, the element isolation region 212 is formed in a self-aligned manner with respect to the gate electrode region 205 '.
[0097]
Next, after a polycrystalline silicon film as a material of the stacked diffusion layer 214 (see FIG. 23C) is formed on the entire surface by the LPCVD method, anisotropic etch back is performed, and FIGS. As shown in (b) and (c), a side wall 220 made of a polycrystalline silicon film is formed. The deposition thickness of the polycrystalline silicon film and the etch-back conditions are adjusted so that the width of the sidewall 220 is larger than the width of the active region of the source and drain regions. When forming the side wall 220 made of the polycrystalline silicon film, it is important to form the natural oxide film so as not to grow on the interface between the side wall 220 and the surface of the shallow well region 203. When a natural oxide film grows at the interface between the active region surfaces of the source and drain regions of the shallow well region 203 and the deposited polycrystalline silicon film, ions are implanted in a later step to form a portion of the side wall 220 made of the polycrystalline silicon film. After introducing an impurity serving as a donor or an acceptor into the shallow well region 203 by heat treatment to form a junction by thermally diffusing the impurity into the shallow well region 203, the natural oxide film acts as a diffusion barrier for the impurity, thereby inhibiting uniform impurity diffusion. You. Therefore, the junction depth of the source and drain regions becomes non-uniform, which causes the transistor characteristics to vary.
[0098]
In the third embodiment, a polycrystalline silicon film for the sidewall 220 is formed by an LPCVD apparatus including a preliminary exhaust chamber, a nitrogen purge chamber whose dew point is always kept at −100 ° C. or lower, and a deposition furnace. Therefore, it is possible to grow the polycrystalline silicon film so that a natural oxide film does not grow. Since a specific method is the same as that for forming the semiconductor device of the first embodiment, the description is omitted here.
[0099]
Next, as shown in FIG. 20, the silicon nitride film 207 and the silicon oxide film 206 (see FIG. 19B) are removed. At this time, the silicon nitride film 209 forming the gate electrode side wall insulating film 210 is also slightly etched, but since the width is as small as about several tens of nm, only the upper portion is slightly etched, and most of it is used as the side wall insulating film. Will remain. Next, in order to prevent a short circuit between the source region (source electrode) and the drain region (drain electrode), a well-known lithography technique and a processing technique are used to form both ends of the gate electrode area 205 ′ in the longitudinal direction. A part of the polycrystalline silicon film 220 is removed. Further, part of the gate electrode 205 at both ends in the longitudinal direction of the gate electrode is removed to form contact regions 240a and 240b connecting the gate electrode 205 (see FIG. 16B) and the shallow well region 203.
[0100]
Next, as shown in FIGS. 21A, 21B and 21C, the sidewall 220 serving as the gate electrode region 205 'and the stacked diffusion layer 214 of the source and drain regions (see FIG. 16B). In order to implant a second conductivity type impurity, a resist 250 is patterned, and a second conductivity type impurity 260 is implanted into the gate electrode region 205 ′ and the side wall 220 using the resist 250 as a mask. At this time, in consideration of the diffusion of the impurity of the second conductivity type in the lateral direction, the impurity is implanted into the resist 250 into a region 100 nm to 200 nm inside both ends 241a and 241b in the longitudinal direction of the gate electrode region 205 '. Is patterned. In the third embodiment, the gate electrode 205 (see FIG. 16B) is simultaneously formed with the doping of the second-conductivity-type impurity into the side wall 220 made of a polycrystalline silicon film for forming the source and drain regions 214. The gate electrode region 205 'is doped with a second conductivity type impurity to form it.
[0101]
Next, as shown in FIG. 22B, first conductive type diffusion layers 213a, 213b (for ohmic connection) are connected to contact regions 240a, 240b for connecting the gate electrode 205 and the shallow well region 203, respectively. In order to form FIG. 23B), an impurity 261 of the first conductivity type is implanted. As shown in FIG. 22B, the resist 251 covers the entire gate electrode region 205 from a position F / 3 away from the gate electrode ends 241a and 241b of the gate electrode region 205 ′ in the direction of the contact regions 240a and 240b. Thus, patterning is performed, and impurities 261 of the first conductivity type are implanted into portions of contact regions 240a and 240b apart from gate electrode region 205 ′. As described above, the first conductivity type impurity is added to a region away from the gate electrode region 205 'from a position away from the gate electrode ends 241a and 241b in the direction of the contact regions 240a and 240b by a distance of about F / 3 corresponding to the alignment accuracy. By implanting 261, even if an alignment shift occurs due to a process fluctuation or the like, the impurity 261 of the first conductivity type is not doped into the gate electrode region 205 ′. Therefore, the driving force of the element can be prevented from deteriorating because it is not offset by the impurities of the second conductivity type in the gate electrode 205 (see FIGS. 16B and 23B).
[0102]
In the third embodiment, a CMOSFET (complementary MOSFET) is formed. Therefore, when donor impurities are implanted into the source, drain, and gate electrodes of the N-channel element, the gate electrode of the P-channel element is connected to the N-type conductive element. At the same time, donor impurities are implanted into the contact region for connection to the shallow well region, and acceptor impurities are implanted into the source, drain, and gate electrodes of the P-channel device. A step of simultaneously implanting acceptor impurities into a contact region for connecting to a shallow well region of conductivity type is performed. Therefore, it is possible to perform an ion implantation step for connecting the gate electrode and the shallow well region without adding a new step.
[0103]
The thickness of the gate electrode region 205 'made of the polycrystalline silicon film was 200 to 250 nm, and the height of the side wall 220 made of the polycrystalline silicon film near the gate electrode was 200 to 300 nm. For this reason, the ion implantation conditions are as follows: for an N-channel transistor, phosphorus ions are converted to energy of about 20 KeV to 80 KeV by 2 × 10 ^Fifteen From 1 × 10 ¹⁶ / Cm ² The injection was performed at a moderate amount. As for the P-channel transistor, boron ions are converted to energy of about 10 KeV to about 30 KeV by 2 × 10 ^Fifteen From 1 × 10 ¹⁶ / Cm ² The injection was performed at a moderate amount. Here, although not shown, a screen oxide film of 5 to 30 nm may be formed on the entire surface before impurity implantation for the purpose of removing contaminants (contamination) at the time of impurity implantation. The energy of the impurity implantation is set so that the impurity is implanted only into the side wall 220 made of the polycrystalline silicon film.
[0104]
Next, as shown in FIGS. 23B and 23C, the impurity 260 implanted into the gate electrode region 205 ′ and the sidewall 220 is activated, and the impurity 260 is diffused into the shallow well region 203. Therefore, heat treatment is performed. As a result, a source / drain region 214 composed of the stacked diffusion layer 2141 and the in-substrate diffusion layer 2142 which is a diffusion layer in the shallow well 203 is formed. At this time, the impurity 261 implanted into the shallow well region 203 for forming the high concentration diffusion layer regions 213a and 213b is also activated and diffused. The heat treatment is performed at a temperature of about 800 ° C. to 950 ° C. for about 10 to 60 minutes, or at a temperature of about 900 ° C. to about 1100 ° C. for about 10 to 60 seconds. And a solid phase diffusion from the sidewall 220 made of the polycrystalline silicon film to the shallow well region 203 to form a junction. In this way, impurity ions are implanted into sidewall 220 made of a polycrystalline silicon film stacked higher than the channel region, and impurities are solid-phase diffused from sidewall 220 to shallow well region 203 to form a junction. I do. That is, since the impurity is not directly injected into the shallow well region 203, a junction leak current due to a crystal defect does not occur, and the junction leak current can be reduced. Here, as a guide for the heat treatment conditions, it is necessary to diffuse the junction positions in the lateral direction formed in the source and drain regions 214 to such an extent that they do not separate from the gate electrode 205 (channel region). Specifically, the gate electrode sidewall insulating film 210 composed of the silicon oxide film 208 and the silicon nitride film 209 needs to be diffused in the lateral direction beyond the width thereof. In order to improve the performance of the transistor, the junction depth is made as small as possible to suppress the short channel effect, and the source and drain regions are not offset with respect to the gate electrode 205 to obtain a high drive current. 214 must be formed. For example, in the case where the width of the gate electrode side wall insulating film 210 is 20 nm, when impurity diffusion of an N-channel transistor and a P-channel transistor is performed by a single heat treatment, about 800 to 60 minutes to about 875 ° C. and about 10 minutes. Has been found to be optimal. Thus, the in-substrate diffusion layer 2142 and the impurity-doped gate electrode 205 are formed.
[0105]
Next, as shown in FIG. 23B, a silicon oxide film 270 having a thickness of about 50 to 100 nm is formed by the CVD method. Next, the contact regions 240a and 240b from which the polycrystalline silicon film 220 has been removed in order to prevent a short circuit between the source region 214 (source electrode) and the drain region 214 (drain electrode) in the previous step are formed by the silicon oxide film 270. Cover completely.
[0106]
Specifically, using a well-known lithography technique and a processing technique, the gate electrode 205 is positioned F / 3 inward from both ends 241a and 241b in the longitudinal direction of the gate electrode 205 from a plane perpendicular to the longitudinal direction of the gate electrode 205. The silicon oxide film 270 in the region in the inner direction of 205 is removed. Then, contact regions 240a and 240b from which polycrystalline silicon film 220 has been removed in order to prevent a short circuit between the source electrode and the drain electrode are completely covered with silicon oxide film 270. The layout is such that the silicon oxide film 270 is formed on the region having a length of about F / 3, which is the alignment accuracy, inward from the gate electrode ends 241a and 241b. Even if an alignment shift occurs, the polycrystalline silicon film 220 is removed to prevent a short circuit between the source electrode and the drain electrode, and the contact regions 240a and 240b can be surely covered with the silicon oxide film 270. This step is very important for preventing a short circuit between the source / drain region 214 and the shallow well region 203, and will be described in detail in Embodiment 1 with reference to FIGS. 9 (a) and 9 (b). Since the description has been made using the above, the description is omitted here.
[0107]
Next, a titanium silicide film 215 is selectively formed as a refractory metal film on the portion of the gate electrode 205 from which the silicon oxide film 270 has been removed and on the source and drain regions 214 by a well-known salicide process. In the third embodiment, silicide made of titanium metal is used as the refractory metal film. However, the present invention is not limited to this, and other materials such as cobalt, nickel, and platinum may be used. Alternatively, a high-melting point metal film such as tungsten, titanium, titanium nitride, or tantalum, or aluminum, copper, or an alloy thereof, or a material in which an impurity such as silicon or palladium is added to these metals or alloys may be used. .
[0108]
Next, as shown in FIGS. 24A, 24B and 24C, after an interlayer insulating film 216 is formed by a known method, a contact hole 217 is opened at a predetermined position of the interlayer insulating film 216. . At this time, the contact hole 217 to the gate electrode 205 is formed so as to straddle a part of both ends in the longitudinal direction of the gate electrode 205 and the contact regions 240a and 240b. By doing so, the gate electrode 205 and the shallow well region 203 can be reliably connected via the metal plug 218 (see FIG. 25B) formed later.
[0109]
Next, as shown in FIGS. 25A, 25B and 25C, a contact metal plug 218 and an upper metal wiring 219 are formed by a well-known method to complete the semiconductor device of the third embodiment. .
[0110]
(Embodiment 4)
The configuration of the semiconductor device of the fourth embodiment will be described with reference to FIGS.
[0111]
The semiconductor device according to the fourth embodiment is obtained by electrically connecting the gate electrode and the shallow well region of the semiconductor device according to the second embodiment. 26A shows a plan layout thereof, FIG. 26B shows a cross section taken along the line BB ′ in FIG. 26A, and FIG. 26C shows a cross section taken along line C-B in FIG. The cross sections in the direction C ′ are shown. 26A. In the plan layout diagram of FIG. 26A, the upper metal wiring 219 and the metal wiring 219 are formed in order to clarify the positional relationship between the gate electrode 205, the source / drain regions 171, the contact regions 240a and 240b, and the contact holes 217. The plug 218 is omitted.
[0112]
The semiconductor device according to the fourth embodiment is different from the semiconductor device according to the third embodiment in that the contact holes to the source / drain regions 171, the stacked diffusion layers 1711, the in-substrate diffusion layers 1712, and the source / drain regions 171 are formed. All other parts have the same structure, except for the location where they are provided. Therefore, in FIGS. 26 (a), (b) and (c), the same components as those of the second embodiment shown in FIGS. 16 (a), (b) and (c) are denoted by the same reference numerals. And the description is omitted. Here, only the structure of the source and drain regions 171 and the positional relationship of the contact holes provided thereon will be described.
[0113]
The source / drain regions 171 are composed of a stacked diffusion layer 1711 and a diffusion layer 1712 in the substrate, similarly to the semiconductor device of the second embodiment. The stacked diffusion layer 1711 is formed over the source and drain active regions and the element isolation region 212 of the in-substrate diffusion layer 1712. In the semiconductor device of the fourth embodiment, the thickness of the stacked diffusion layer 1711 is smaller in the region 180 near the gate electrode 205 than in other regions, and the width of the region 180 is the thickness of the stacked diffusion layer 1711 in other regions. Is almost the same as Thus, the semiconductor device according to the fourth embodiment has a smaller area in which the stacked diffusion layer 1711 faces the gate electrode 205 as compared with the semiconductor device according to the third embodiment. Therefore, the capacitance associated with the gate electrode 205 and the source / drain region 171 can be reduced.
[0114]
The method of manufacturing a semiconductor device according to the fourth embodiment is different from the method of manufacturing a semiconductor device according to the third embodiment only in the procedure for forming the stacked diffusion layer 1711 of the source / drain regions 171, and therefore, detailed description is omitted. I do.
[0115]
The semiconductor device of the fourth embodiment can be manufactured by combining the manufacturing procedure of the semiconductor device of the third embodiment with the manufacturing procedure of forming the stacked diffusion layer 1171 of the source / drain regions 117 described in the second embodiment. is there.
[0116]
【The invention's effect】
As is clear from the above, according to the semiconductor device of the present invention, the shortest distance between the gate electrode and the element isolation region is F / 3 or less, so that the source and drain regions are smaller than the conventional semiconductor device. The junction area can be reduced, so that the junction capacitance of the source and drain regions can be reduced.
[0117]
Further, according to the method of manufacturing a semiconductor device of the present invention, the element isolation region can be formed with respect to the gate electrode by using the first sidewall insulating film and the second sidewall insulating film without using a special manufacturing device. It can be formed in a self-aligned manner. Therefore, the active layer area of the source region and the drain region can be reduced, and a semiconductor device having a small junction capacitance can be easily formed. Further, since the insulating film is formed on the active region from which a part of the polycrystalline silicon film has been removed, a short circuit between the source region and the drain region and a short circuit between the source and drain regions and the well region (semiconductor substrate). Can be reliably prevented.
[Brief description of the drawings]
FIGS. 1A, 1B, and 1C are diagrams illustrating a semiconductor device according to a first embodiment of the present invention;
FIGS. 2A and 2B are diagrams illustrating active layer widths of source and drain regions of the semiconductor device according to the first embodiment of the present invention and a conventional semiconductor device.
FIGS. 3A, 3B, and 3C are diagrams illustrating a procedure for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIGS. 4A, 4B, and 4C are diagrams illustrating a procedure for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIGS. 5A, 5B, and 5C are diagrams illustrating a procedure for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIGS. 6A, 6B, and 6C are diagrams illustrating a procedure for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIGS. 7A, 7B, and 7C are diagrams illustrating a procedure for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIGS. 8A, 8B, and 8C are diagrams illustrating a procedure for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIGS. 9A and 9B are diagrams illustrating the necessity of a silicon oxide film in a procedure for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIGS. 10A, 10B, and 10C are diagrams illustrating a procedure for manufacturing a semiconductor device according to a second embodiment of the present invention;
FIGS. 11A, 11B, and 11C are diagrams illustrating a procedure for manufacturing a semiconductor device according to a second embodiment of the present invention;
FIGS. 12A, 12B, and 12C are diagrams illustrating a procedure for manufacturing a semiconductor device according to Embodiment 2 of the present invention;
FIGS. 13A, 13B, and 13C are diagrams illustrating a procedure for manufacturing a semiconductor device according to Embodiment 2 of the present invention;
FIGS. 14A, 14B, and 14C are diagrams illustrating a semiconductor device according to a second embodiment of the present invention and a procedure for manufacturing the semiconductor device.
FIGS. 15A and 15B are diagrams illustrating a case where a series transistor is formed in the semiconductor device according to the first and second embodiments of the present invention.
FIGS. 16 (a), (b) and (c) are diagrams illustrating a semiconductor device according to a third embodiment of the present invention.
FIGS. 17A, 17B, and 17C are diagrams illustrating a procedure for manufacturing the semiconductor device according to the third embodiment of the present invention;
FIGS. 18A, 18B, and 18C are diagrams illustrating a procedure for manufacturing a semiconductor device according to a third embodiment of the present invention.
FIGS. 19A, 19B, and 19C are diagrams illustrating a procedure for manufacturing a semiconductor device according to a third embodiment of the present invention.
FIGS. 20A, 20B, and 20C are diagrams illustrating a procedure for manufacturing a semiconductor device according to Embodiment 3 of the present invention;
FIGS. 21A, 21B, and 21C are diagrams illustrating a procedure for manufacturing a semiconductor device according to a third embodiment of the present invention;
FIGS. 22A, 22B, and 22C are diagrams illustrating a procedure for manufacturing a semiconductor device according to Embodiment 3 of the present invention;
FIGS. 23A, 23B, and 23C are diagrams illustrating a procedure for manufacturing a semiconductor device according to Embodiment 3 of the present invention;
FIGS. 24A, 24B, and 24C are diagrams illustrating a procedure for manufacturing a semiconductor device according to Embodiment 3 of the present invention;
FIGS. 25A, 25B, and 25C are diagrams illustrating a procedure for manufacturing a semiconductor device according to Embodiment 3 of the present invention;
FIGS. 26 (a), (b) and (c) are diagrams illustrating a semiconductor device according to a fourth embodiment of the present invention.
FIGS. 27A and 27B are diagrams illustrating a conventional semiconductor device.
[Explanation of symbols]
101, 201 silicon semiconductor substrate
102, 204 Gate insulating film
104, 106, 108, 109, 113, 206, 208, 211, 212, 270 silicon oxide film
103 'gate electrode region not doped with impurities
103, 205 Gate electrode
105, 107, 207, 209 Silicon nitride film
110, 170, 220 Polycrystalline silicon film
111, 260 Second conductivity type impurities
112,171,214 Stacked diffusion layer
114,215 Refractory metal silicide film
115, 216 interlayer insulating film
116, 217 Contact hole
118,218 Metal plug
119, 219 Upper metal wiring
130 channel area
150, 165, 250, 251 resist
180, 225 Region where the thickness of the stacked layer is thin
202 Deep well region of second conductivity type
203 Shallow well region of first conductivity type
213a, 213b High-concentration diffusion layer region of first conductivity type
240a, 240b contact area
261 First conductivity type impurity

Claims (10)

In a semiconductor substrate, an active region, an element isolation region, a source region, and a drain region are provided directly or indirectly, a gate insulating film is provided on the active region, and a gate electrode is provided on the gate insulating film. In semiconductor devices,
A semiconductor device, wherein a minimum processing dimension is F, and a shortest distance between the gate electrode and the element isolation region is F / 3 or less. The semiconductor device according to claim 1,
The source region and the drain region are formed on an active region and a part of the element isolation region, respectively, so as to be located above an interface between the active region and the gate insulating film. A semiconductor device comprising a conductive material. The semiconductor device according to claim 2,
A semiconductor device, wherein a thickness of a region of the conductor near the gate electrode is smaller than a thickness of another region of the conductor. The semiconductor device according to claim 2, wherein
A semiconductor device, wherein the conductor is a stacked diffusion layer made of a polycrystalline silicon film. The semiconductor device according to claim 1, wherein
A deep well region of the first conductivity type formed in the semiconductor substrate;
A shallow well region of the second conductivity type formed in the deep well region of the first conductivity type and partitioned by the element isolation region;
The active region is provided in the shallow well region,
A semiconductor device, wherein the gate electrode and the shallow well region of the second conductivity type are electrically connected. The semiconductor device according to claim 5,
A semiconductor device, wherein the gate electrode and the shallow well region are electrically connected at two places at both ends in the longitudinal direction of the gate electrode. A step of sequentially forming a gate insulating film, a gate electrode, and an insulating film on the gate electrode on the semiconductor substrate;
Forming a first gate electrode side wall insulating film and a second gate electrode side wall insulating film sequentially positioned from the gate electrode side on the side of the gate electrode;
Using the insulating film on the gate electrode, the first gate electrode side wall insulating film and the second gate electrode side wall insulating film as a mask, etching the semiconductor substrate to form a groove;
Burying an insulating film in the trench to form an element isolation region;
Removing the second gate electrode side wall insulating film;
Forming a polycrystalline silicon film on a part of the active region and the element isolation region so as to be located above the interface between the gate insulating film and the active region;
Removing a portion of the polycrystalline silicon film at both ends in the longitudinal direction of the gate electrode,
Forming an insulating film on the active region in the region where the polycrystalline silicon film has been removed. The method of manufacturing a semiconductor device according to claim 7,
The step of forming the polycrystalline silicon film includes:
Depositing a polycrystalline silicon film having a thickness greater than the distance between the gate electrode and the element isolation region over the entire surface;
Etching the polycrystalline silicon film on the gate electrode until the polycrystalline silicon film disappears. The method of manufacturing a semiconductor device according to claim 7,
The step of forming the polycrystalline silicon film includes:
A step of depositing a polycrystalline silicon film on the entire surface;
A step of flatly applying a resist on the polycrystalline silicon film,
A step of reducing the thickness of the resist so that the insulating film on the gate electrode region is exposed;
Patterning the resist,
Etching the region of the polycrystalline silicon film near the gate electrode using the resist as a mask until the region becomes thinner than the film thickness of the polycrystalline silicon film when it is deposited. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 7,
After forming the polycrystalline silicon film, forming a gate electrode by removing a part of the gate electrode region at both longitudinal ends of the gate electrode region for forming the gate electrode,
Removing a part of the polycrystalline silicon film and forming a contact region for connecting the gate electrode to the shallow well region of the second conductivity type;
Depositing an interlayer insulating film on the entire surface;
Forming the contact hole over the gate electrode and the contact region by removing a portion of the interlayer insulating film on a portion of the gate electrode and the interlayer insulating film on the contact region; ,
Burying a conductive material in the contact hole.

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