JP2004309281A - Inspection circuit and inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To clearly demarcate the cause of a failure occurring owing to an influence of power source noise. <P>SOLUTION: When an inspection start command is inputted, a logic block 21 controls a high-speed sequencer 22 and a selector 23, and starts inspection processing of a semiconductor integrated circuit 1. Hereby, the high-speed sequencer 22 generates retrieval key data and a retrieval timing signal based on a retrieval condition set by the logic block 21, and inputs them into a CAM block 11 through the selector 23. The CAM block 11 executes retrieval processing continuously based on the retrieval key data and the retrieval timing signal. In this case, the logic block 21 outputs data in a built-in register to a test control part 31 based on a control signal of the test control part 31. This invention can be applied to the semiconductor integrated circuit for executing noise-resistance inspection. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an inspection circuit and an inspection method, and more particularly to an inspection circuit and an inspection method capable of clearly isolating a cause of a failure due to the influence of power supply noise.
[0002]
[Prior art]
In recent years, the operation of LSI (Large Scale Integration) has become unstable due to the increase in power consumption inside the LSI and the accompanying generation of noise due to the increase in submicron size, large scale, and high operating frequency. Increased. Therefore, it has become necessary to test a noise resistance by inputting a test pattern to an LSI and comparing expected values output from the LSI.
[0003]
As shown in FIG. 1, on the same LSI, a block A which is a circuit group (for example, a DRAM (Dynamic Random Access Memory)) which consumes a large amount of power and can be a noise source, and a block A which consumes less power than the block A Block B, which is a group of circuits (for example, logic circuits) that is likely to malfunction due to the influence of noise generated from block A, coexists. Therefore, in the above-described noise resistance inspection, as disclosed in Japanese Patent Application Laid-Open No. H11-163873, it is proposed to inspect a plurality of blocks separately, a block A that can be a noise source, and an influence of noise generated from the block A. It is necessary to separate and inspect the block B to be received.
[0004]
Therefore, first, only the block B that does not consume power consumption is operated without operating the block A that can be a noise source, and only the block B is inspected. Thus, the block B can be inspected in a state where noise from the block A is not generated. Next, without operating the block B, only the circuit group A that consumes much power and can be a noise source is operated, and only the block A is inspected.
[0005]
[Patent Document 1]
JP-A-2002-40113
[0006]
[Problems to be solved by the invention]
However, the inspection of the block A that can be a noise source described above usually requires the use of a logic block around the block A. This logical block is included in block B that does not consume power. Therefore, when a failure occurs in the inspection of the block A that can be a noise source, it is either a failure of the block A that can be the noise source, or the peripheral logic block B malfunctions due to the noise generated by the block A. There was a problem that it was difficult to judge clearly.
[0007]
The present invention has been made in view of such a situation, and it is an object of the present invention to clearly identify the cause of a failure due to the influence of power supply noise.
[0008]
[Means for Solving the Problems]
An inspection circuit according to the present invention includes a determination unit that determines whether an inspection command for inspecting a semiconductor integrated circuit has been received, and data for operating a first block when the determination unit determines that the inspection command has been received. , And output means for continuously outputting the data generated by the generation means to the first block, wherein the first block is operated by the data output by the output means. Sometimes, the second block is inspected.
[0009]
The first block may be configured by a CAM (Content Addressable Memory).
[0010]
When the determination unit determines that the inspection command has been received, the determination unit further includes a setting unit that sets a search condition for performing a search operation on the first block, and the generation unit includes a setting unit that sets the search condition based on the search condition set by the setting unit. Data can be generated.
[0011]
The search condition may be a search operation interval of the first block, contents of data generated by the generation unit, a position of a search target block in the first block, or designation of a mask function of the first block. can do.
[0012]
When it is determined by the determining means that the inspection command has been received, the data output by the output means is selected and output to the first block. When the determining means determines that the inspection command has not been received, the second processing is performed. The information processing apparatus may further include a selection unit that selects data output from the block and outputs the data to the first block.
[0013]
An inspection method according to the present invention includes a determining step of determining whether an inspection command for inspecting a semiconductor integrated circuit has been received, and operating the first block when it is determined that the inspection command has been received by the processing of the determining step. And an output step of continuously outputting the data generated by the processing of the generation step to the first block. The first step is performed by the data output by the processing of the output step. When the block is operating, the second block is checked.
[0014]
In the present invention, when it is determined that an inspection command for inspecting the semiconductor integrated circuit has been received, data for operating the first block is generated, and the generated data is output continuously to the first block. Is done. Then, when the first block is operating with the output data, the second block is inspected.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described below. The correspondence between constituent elements described in the claims and specific examples in the embodiments of the present invention is as follows. This description is for confirming that a specific example supporting the invention described in the claims is described in the embodiment of the invention. Therefore, even if there is a specific example which is described in the embodiment of the invention but is not described here as corresponding to the configuration requirement, the fact that the specific example is It does not mean that it does not correspond to the requirement. Conversely, even if a specific example is described here as corresponding to a configuration requirement, this means that the specific example does not correspond to a configuration requirement other than the configuration requirement. not.
[0016]
Furthermore, this description does not mean that the invention corresponding to the specific examples described in the embodiments of the invention is all described in the claims. In other words, this description is an invention corresponding to the specific example described in the embodiment of the invention, and the existence of the invention not described in the claims of this application, that is, It does not deny the existence of the invention added by the amendment.
[0017]
The inspection circuit according to claim 1 includes a first block (for example, the CAM block 11 in FIG. 3) that can be a noise source and a second block (for example, FIG. 3) that receives noise from the first block. A logic block 21) for testing a semiconductor integrated circuit (for example, the semiconductor integrated circuit 1 in FIG. 2), and determining whether a test command for testing the semiconductor integrated circuit has been received. For example, when it is determined by the determination unit that the inspection command has been received by the logic block 21 in FIG. 3, the generation unit that generates data for operating the first block (for example, the processing in step S43 in FIG. 9 is performed) The high-speed sequencer 22 shown in FIG. 3 to be executed and the data generated by the generating means are continuously output to a first block (for example, the CAM block 11 shown in FIG. 3). Output means (for example, the high-speed sequencer 22 in FIG. 3 for executing the processing in step S44 in FIG. 9), and when the first block is operated by the data output from the output means, The block is inspected.
[0018]
The setting circuit sets a search condition for performing a search operation on the first block (for example, the CAM block 11 in FIG. 3) when the determination circuit determines that the inspection command has been received. (For example, the logic block 21 of FIG. 3 for executing the processing of step S42 of FIG. 9), wherein the generation unit generates data based on the search condition set by the setting unit.
[0019]
The inspection circuit according to claim 5, wherein when the determination unit determines that the inspection command is received, the data output by the output unit (for example, the high-speed sequencer 22 of FIG. 3 executing the processing of step S24 of FIG. 8). Is selected and output to the first block (for example, the CAM block 11 in FIG. 3). If the determination unit determines that the inspection command has not been received, the second block (for example, the logical block 21 in FIG. 3) ) Is further provided with a selecting means (for example, the selector 23 in FIG. 3) for selecting data output from the first block (for example, the CAM block 11 in FIG. 3) and outputting the data to the first block (for example, the CAM block 11 in FIG. 3).
[0020]
The inspection method according to claim 6, wherein the first block that can be a noise source (for example, the CAM block 11 in FIG. 3) and the second block that receives noise from the first block (for example, FIG. 3) (For example, the semiconductor integrated circuit 1 shown in FIG. 2) having the logic block 21), and determining whether or not a test command for testing the semiconductor integrated circuit has been received ( For example, a generation step of generating data for operating the first block (for example, the CAM block 11 of FIG. 3) when it is determined that the inspection command has been received by the processing of the determination step in step S6 of FIG. (For example, step S43 in FIG. 9) and the data generated by the processing in the generation step are stored in a first block (for example, CAM block 1 in FIG. 3) ) And an output step (for example, step S44 in FIG. 9) that outputs the second block when the first block is operated by the data output by the processing of the output step. It is characterized by inspecting.
[0021]
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0022]
FIG. 2 shows a configuration example of a semiconductor integrated circuit 1 to which the present invention is applied. Note that, in the example of FIG. 2, wiring, buses, and the like are omitted. In the case of the example of FIG. 2, the semiconductor integrated circuit 1 includes CAM (Content Addressable Memory) blocks 11-1 to 11-8 divided into eight blocks (hereinafter, when these need not be individually distinguished, they are simply CAM blocks). 11) and a low power consumption block 12 including a logic block 21 (FIG. 3) for supplying data to the CAM block 11.
[0023]
The CAM block 11 group is arranged in the order of CAM block 11-1, CAM block 11-2, CAM block 11-3, and CAM block 11-4 in order from the left. The CAM block 11-5, the CAM block 11-6, the CAM block 11-7, and the CAM block 11-8 are arranged in this order. The CAM block 11 is configured by a CAM or the like that performs a search operation using the search key data supplied from the logical block 21 as a key and outputs an address that hits the search key data. Therefore, the CAM block 11 is a block that consumes the largest amount of power (for example, 10 W to 20 W) in the semiconductor integrated circuit 1 when a search operation is performed due to its configuration. A block that can be a source.
[0024]
The low power consumption block 12 is more physically from the CAM blocks 11-2, 11-3, 11-6 and 11-7 than from the CAM blocks 11-1, 11-4, 11-5 and 11-8. CAM blocks 11-1 to 11-8, which are positions close to. The small power consumption block 12 is configured by a logic block 21 that supplies data to the CAM block 11 and the like, and consumes less power than the CAM block 11.
[0025]
As described above, the semiconductor integrated circuit 1 includes the CAM block 11 that consumes a large amount of power and the small block 12 that consumes a small amount of power. Therefore, the small power consumption block 12 is easily affected by the noise generated from the CAM block 11, and may malfunction.
[0026]
FIG. 3 shows a detailed configuration example of the semiconductor integrated circuit 1. In the example of FIG. 3, the semiconductor integrated circuit 1 includes a CAM block 11 and a small power consumption block 12 including a logic block 21, a high-speed sequencer 22, and a selector 23.
[0027]
The CAM block 11 includes one or a plurality of CAMs. In this case, for convenience of explanation, the CAM block 11 will be described as one CAM. The CAM block 11 synchronizes the search key data input from the selector 23 with the search timing (SRCH) signal and mask supplied from the selector 23 in synchronization with the system clock (CLK) supplied from the test control unit 31. Based on the (MASK) signal, a search is made from data registered in the CAM block 11 in advance. The CAM block 11 has a mask function as shown in FIG. 4 as a search function when performing a search operation.
[0028]
FIG. 4 shows a configuration example of the CAM block 11. In the example of FIG. 4, the CAM block 11 registers 72 bits of data at each address. The CAM block 11 can set any bits (for example, 12 bits) of the 72-bit data as a mask portion, and do not set them as search targets at the time of search. This is called a mask function. Accordingly, the CAM block 11 uses the mask function based on the mask signal from the selector 23 and recognizes only the 60 bits of the registered data as the search target, and recognizes the search target portion at the time of the search. Then, the CAM block 11 searches the search target portion for data that matches the input search key data.
[0029]
The CAM block 11 outputs search result data to the logical block 21 via the internal bus 42 when data matching the input search key data is found in the CAM block 11. The search result data includes a hit (HON) signal indicating that there is data matching the search key data, a multi-hit (MHON) signal indicating that there is a plurality of data matching the search key data, and search key data. , A hit address (HHA (Highest Hit Address)) signal indicating the smallest (highest priority) address among the addresses of the data that matches the data address.
[0030]
A test control unit 31 is arranged outside the semiconductor integrated circuit 1. The test control unit 31 supplies a system clock (CLK) to the CAM block 11, the logic block 21, and the high-speed sequencer 22. Further, the test control unit 31 supplies a control (CNTL) signal, a chip enable (CEN) signal, a read / write (RWN) signal, and the like for controlling the semiconductor integrated circuit 1 to the logic block 21.
[0031]
The control signal is composed of various commands. The various commands include a search command for instructing a search process in the semiconductor integrated circuit 1, an entry command for registering data searched for in the search process in the CAM block 11 in advance, and an instruction for starting a test process of the semiconductor integrated circuit 1. And a read command for reading data of a register built in the logic block 21. The chip enable signal is a signal for controlling the operation state of each unit of the semiconductor integrated circuit 1, and is input not only to the logic block 21 but also to each unit of the semiconductor integrated circuit 1, although illustration and description are omitted. The read / write signal is a signal for instructing a register included in the logical block 21 to write or read data. The mask signal is a signal for setting a mask function of the CAM block 11.
[0032]
Further, the test control unit 31 writes the search key data to the register of the logical block 21 via the data bus 41. The test control unit 31 writes predetermined data for the test of noise resistance to the register of the logical block 21 via the data bus 41, and reads the data written to the register via the data bus 41. . The test control unit 31 can inspect the state of the logical block 21 by verifying the data read from the register of the logical block 21.
[0033]
The logic block 21 has a register (not shown) inside, and writes data into the register and reads data from the register under the control of the test control unit 31. The logic block 21 performs various processes of the semiconductor integrated circuit 1 based on the control signal, the chip enable signal, and the read / write signal input from the test control unit 31 in synchronization with the system clock from the test control unit 31. Control.
[0034]
Specifically, the logic block 21 determines what command the control signal input from the test control unit 31 is. When the control signal input from the test control unit 31 is a search command, the logic block 21 synchronizes with the system clock from the test control unit 31 to search key data, various signals (chip enable signal, search timing signal, , And a mask signal) to the CAM block 11 via the selector 23. Then, the logic block 21 outputs the search result data from the CAM block 11 to an external circuit (not shown) via the data bus 43.
[0035]
When the control signal input from the test control unit 31 is an entry command, the logic block 21 synchronizes the data from the test control unit 31 with the system clock from the test control unit 31 via the selector 23, Output to the CAM block 11. When the control signal input from the test control unit 31 is a test start command, the logic block 21 controls the high-speed sequencer 22 and the selector 23 to start the test processing of the semiconductor integrated circuit 1. When the control signal supplied from the test control unit 31 is a read command, the logic block 21 outputs data written in a built-in register to the test control unit 31 via the data bus 41.
[0036]
Further, the logic block 21 sets search conditions for the search executed by the CAM block 11 in the inspection processing of the semiconductor integrated circuit 1 and supplies the search conditions to the high-speed sequencer 22. The search conditions that can be set by the logical block 21 include the search interval of the search executed in the CAM block 11, the content (bit configuration) of the search key data, the mask function of the CAM block 11, and the CAM block divided into eight blocks. Among the items 11-1 to 11-8 (FIG. 2), there are positions of CAM blocks to be searched.
[0037]
By changing these search conditions, due to the nature of the CAM block 11, the power consumption of the CAM block 11 in the search operation changes. For example, when the setting of the search interval is changed to a large value, the load on the search operation of the CAM block 11 is reduced, so that the power consumption of the CAM block 11 is smaller than before changing the search interval. Further, when the search key data composed of all 0s is changed to the search key data composed of a mixture of 0s and 1s, the power consumption of the CAM block 11 is lower than before the change of the search key data. , More. Further, when the mask function described above with reference to FIG. 4 is set, the power consumption of the CAM block 11 is smaller than when the mask function is not set. As described above, the inspection of the semiconductor integrated circuit 1 can be performed under various power consumptions. That is, it is possible to inspect a defect of the semiconductor integrated circuit 1 caused by the magnitude of the power consumption.
[0038]
When setting the position of the CAM block 11 to be searched, as described above with reference to FIG. 2, as in the CAM block 11-2, 11-3, 11-6, or 11-7, The influence of noise at a position physically close to the logical block 21 and the influence of noise at a position physically far from the logical block 21 such as the CAM blocks 11-1, 11-4, 11-5 and 11-8. For example, physical influences can be inspected.
[0039]
The high-speed sequencer 22 is provided for testing the semiconductor integrated circuit 1. When a control signal for starting the test is received from the logic block 21, the high-speed sequencer 22 continuously searches the CAM block 11. That is, in the inspection processing of the semiconductor integrated circuit 1, the logic block 21 merely instructs the high-speed sequencer 22 to start the inspection and the search condition, and after the instruction is input, the high-speed sequencer 22 Regardless (independently), based on the search condition supplied from the CAM block 11, search key data, a search timing signal, a mask signal, and the like are generated and synchronized with a system clock from the test control unit 31. , To the CAM block 11 via the selector 23.
[0040]
The selector 23 selects an input on the high-speed sequencer 22 side when there is a control signal for starting a test from the logical block 21, and outputs various data and signals from the high-speed sequencer 22 to the CAM block 11. When there is no control signal from the logic block 21 to start the test, the selector 23 selects an input on the logic block 21 side and outputs various data and signals from the logic block 21 to the CAM block 11.
[0041]
Next, a normal search operation of the semiconductor integrated circuit 1 will be described with reference to the timing chart of FIG.
[0042]
In the example of FIG. 5, in CLK, CEN, RWN, and SRCH, the rising state of the edge of each signal is the H (High) state, and the falling state of the edge is the L (Low) state. CLK indicates the timing of a system clock supplied from the test control unit 31 to each unit of the semiconductor integrated circuit 1, and CNTL indicates the timing at which a 14-bit command signal is input from the test control unit 31 to the logic block 21. DAT indicates the timing at which 72-bit data is input from the test control unit 31 to the logic block 21.
[0043]
CEN indicates the timing of the system enable signal supplied from the test control unit 31 to the logic block 21, and changes from the L state to the H state at the timing of the rising edge of the system clock. At this time, the semiconductor integrated circuit 1 is in an operable state. RWN indicates the timing of a read / write signal supplied from the test control unit 31 to the logic block 21. If the RWN is at the H level at the timing of the rising edge of CLK, data is read from the register of the logic block 21. Conversely, if RWN is at the L level at the timing of the rising edge of CLK, it indicates that data is written to the register of the logic block 21.
[0044]
SRCH indicates the timing of the search timing signal supplied from the logical block 21 to the CAM block 11. HHA indicates the timing at which search result data including the hit address signal from the CAM block 11 is output to the logical block 21 via the internal bus 42, and OD indicates the timing from the logical block 21 to the CAM block 11 23 shows the timing at which the search result data of 23 bits is output to an external circuit (not shown) via the data bus 43. In the example of FIG. 5, various signals other than the system clock are output with a slight delay from the system clock due to delay.
[0045]
In the example of FIG. 5, a system clock is supplied from the test control unit 31 to the logic block 21 and the CAM block 11. As indicated by CNTL and DAT, the test control unit 31 inputs a search command and search key data to the logic block 21 in synchronization with the timing of the falling edge of T0 of the system clock. Then, as indicated by CEN, the system enable signal that was in the L state goes into the H state in synchronization with the timing of the rising edge of the system clock T0, and the semiconductor integrated circuit 1 enters the operable state. At this time, as indicated by RWN, since the read / write signal supplied from the test control unit 31 to the logical block 21 is in the L state, the search key data is written to the register of the logical block 21.
[0046]
Therefore, in response to the search command input from the test control unit 31 in synchronization with the timing of the falling edge of the system clock T0, the logic block 21 determines that the search operation is to be started, and The search key data and the search timing signal are supplied to the CAM block 11 via the selector 23 in synchronization with the timing of the rising edge.
[0047]
As shown in SRCH, the search timing signal goes to the L state in synchronization with the timing of the rising edge of T1, which is the next clock after the search command is input to the CAM block 11. The CAM block 11 starts the search process from this timing a (the timing of the falling edge of the search timing signal). The CAM block 11 is preset so as to output search result data to the logic block 21 with a delay of three clocks after the input of the search command. When there is data that matches the input search key data, the CAM block 11 raises the rising edge of T3 of the system clock three clocks after the input of the search command to the semiconductor integrated circuit 1, as indicated by HHA. At the timing, the search result data is output to the logical block 21 via the internal bus 42.
[0048]
The logic block 21 is preset to output the search result data from the CAM block 11 to an external circuit (not shown) via the data bus 43 with a delay of four clocks after the input of the search command. . Therefore, as indicated by OD, the logic block 21 outputs the search result data from the CAM block 11 to the external circuit at the timing of the rising edge of T4 of the system clock four clocks after the input of the search command, as indicated by OD. I do.
[0049]
As described above, the search processing is executed in the semiconductor integrated circuit 1. At this time, the search result data output from the logic block 21 via the data bus 43 may be unstable depending on conditions such as voltage, temperature, and operating frequency. In such a case, a noise resistance test is performed. First, the semiconductor integrated circuit 1 (that is, both the CAM block 11 and the logic block 21) is continuously searched to perform an inspection. However, in this inspection, since the logic block 21 also operates continuously, the state of the logic block 21 cannot be inspected, and it is clearly known which part of the semiconductor integrated circuit 1 is defective. It is not possible.
[0050]
Therefore, only the logical block 21 is operated without performing the search operation on the CAM block 11, and it is checked whether the operation of the logical block 21 itself is normal. As a result, if it is confirmed that the search result data is normal, the cause of the instability of the search result data is that the circuit of the CAM block 11 itself in the semiconductor integrated circuit 1 is unstable, or Although the circuit and operation are normal, there are two possible causes that the logic block 21 malfunctions due to noise generated by the operation of the CAM block 11.
[0051]
Therefore, it is necessary to perform a test to clearly determine whether the logic block 21 is affected by the noise of the CAM block 11.
[0052]
The inspection operation of the semiconductor integrated circuit 1 will be described with reference to the timing chart of FIG. In FIG. 6, parts corresponding to those in FIG. 5 are denoted by corresponding reference numerals, and description thereof will be omitted, but in FIG. 6, the SRCH includes a high-speed sequencer in the CAM block 11. 2 shows the timing of a search timing signal supplied from the CPU 22.
[0053]
In the example of FIG. 6, the system clock is supplied from the test control unit 31 to the logic block 21, the CAM block 11, and the high-speed sequencer 22. As indicated by CNTL, the test control unit 31 inputs a test start command to the logic block 21 in synchronization with the timing of the falling edge of T0 of the system clock. Further, as indicated by CEN, the system enable signal which has been in the L state becomes the H state in synchronization with the timing of the rising edge of the system clock T0, and the semiconductor integrated circuit 1 becomes operable. At this time, as indicated by RWN, since the read / write signal supplied from the test control unit 31 to the logical block 21 is in the L state, the test control unit 31 transmits predetermined data for inspecting the logical block 21. The data is written to the register of the logic block 21.
[0054]
Therefore, in response to the input of the search command from the test control unit 31 in synchronization with the timing of the falling edge of the system clock T0, the logic block 21 determines that the test operation is to be started, and the high-speed sequencer 22 and the selector 23 executes an inspection process.
[0055]
The high-speed sequencer 22 generates search key data based on the control of the logic block 21 and generates a search timing signal and search key data from the timing of the rising edge of T1, which is the next clock to which the test start command is input. The data is supplied to the CAM block 11 via the selector 23. Then, the high-speed sequencer 22 controls the search timing signal from the H state to the L state in synchronization with the timing of the falling edge of the clock after T1 of the system clock.
[0056]
Accordingly, as shown in the SRCH, the CAM block 11 starts the search operation at the falling edge timings b-1, b-2, b-3,... Of the search timing signal. That is, the CAM block 11 continuously performs the search operation based on the search timing signal from the high-speed sequencer 22. As a result, the power supply voltage inside the semiconductor integrated circuit 1 drops from the rising edge of the system clock T2 at which the search is started, and a situation where noise is most severe is realized.
[0057]
On the other hand, as shown in CNTL, the test control unit 31 starts from the timing of the falling edge of T1 of the system clock next to the timing (falling edge of T0) at which the test start command is written into the register of the logic block 21. A read command is input to the logic block 21 for each clock. That is, at the timing of the falling edge of T1 of the system clock, the read command 0 is input, and as shown by CEN, the system enable signal in the L state is synchronized with the timing of the rising edge of T1 of the system clock. Then, the state becomes the H state, and the semiconductor integrated circuit 1 enters the operable state. At this time, as indicated by RWN, the read / write signal supplied from the test control unit 31 to the logical block 21 is in the H state, so that the logical block 21 receives the read command 0 as indicated by DAT. The data 0 corresponding to the read command 0 is read from the register in synchronization with the timing of the rising edge of T5 after four clock delays from the timing of the falling edge of T1 that has been performed, and the test control unit is connected via the data bus 41. 31.
[0058]
Similarly, at the timing of the falling edge of T2 of the system clock, the read command 1 is input, and as indicated by CEN, the system enable signal in the L state changes to the timing of the rising edge of T2 of the system clock. Synchronously, the state changes to the H state, and the semiconductor integrated circuit 1 enters an operable state. At this time, as indicated by RWN, the read / write signal supplied from the test control unit 31 to the logical block 21 is in the H state, and therefore, the logical block 21 receives the read command 1 as indicated by DAT. The data 1 corresponding to the read command 1 is read from the register and output to the test control unit 31 via the data bus 41 in synchronization with the timing of the rising edge of T6 four clocks after the completion.
[0059]
Also at the subsequent timing, the logic block 21 repeats the process of outputting data corresponding to the read command from the system control unit 31 to the system control unit 31 four clocks after the input of the read command.
[0060]
As described above, by continuously operating the CAM block 11 by the high-speed sequencer 22, the logic block 21 can be operated in the worst condition of the power supply and the like, and the state of the logic block 21 can be inspected. Therefore, at this time, by verifying the data output to the test control unit 31, if the logic block 21 does not operate normally, for example, if the data is unstable, the logic block 21 It is found that the influence is caused by a problem such as a power supply line, and a countermeasure against the influence can be taken.
[0061]
On the other hand, even if the logic block 21 is operated in the worst state of the power supply or the like, if the logic block 21 is operating normally, it is determined that there is a problem on the CAM block 11 side. Measures can be taken.
[0062]
In the above-described noise immunity inspection operation, predetermined data is written to the register of the logic block 21 in synchronization with the timing of the falling edge of T0 of the system clock, and then the predetermined data is read. In this case, a control signal for writing data to the register of the logic block 21 and a control signal for reading data from the register of the logic block 21 are alternately output to perform the noise resistance test. Good.
[0063]
Next, the processing of the semiconductor integrated circuit 1 will be described with reference to the flowchart of FIG.
[0064]
The test control unit 31 inputs a control signal, a system enable signal, a read / write signal, and the like to the logic block 21, and inputs data to the logic block 21 via the data bus 41.
[0065]
When the control signal is input from the test control unit 31, the logic block 21 determines in step S1 whether the control signal input from the test control unit 31 is a search command or not. If it is determined that the input control signal is a search command, the process proceeds to step S2, and the CAM block 11 is searched. The search processing of the CAM block 11 will be described with reference to the flowchart of FIG.
[0066]
In step S21, the logic block 21 outputs the search key data, the search timing signal, the mask signal, and the like from the test control unit 31 to the CAM block 11 via the selector 23, and proceeds to step S22.
[0067]
In step S22, the CAM block 11 inputs the search key data from the logical block 21 in synchronization with the system clock from the test control unit 31, and performs the search based on the search timing signal and the mask signal from the logical block 21. Key data is searched from data registered in the CAM block 11 in advance, and the process proceeds to step S23.
[0068]
If the CAM block 11 finds in the step S23 that data matching the input search key data is present in the CAM block 11, the CAM block 11 sends the search result data hit signal, multi-hit signal and hit address signal to the internal bus 42. Then, the data is output to the logic block 21 and the process proceeds to step S24.
[0069]
In step S24, the logic block 21 outputs the search result data from the CAM block 11 to an external circuit (not shown) via the data bus 43, ends the process, and returns to step S3 in FIG. As described above, the search processing of the semiconductor integrated circuit 1 ends.
[0070]
On the other hand, if it is determined in step S1 of FIG. 7 that the control signal input from the test control unit 31 is not a search command, the process of step S2 is skipped, and the process proceeds to step S3.
[0071]
In step S3, the logic block 21 determines whether the control signal input from the test control unit 31 is an entry command. If it is determined in step S6 that the control signal input from the test control unit 31 is an entry command, the logic block 21 proceeds to step S4, and transmits the data from the test control unit 31 through the selector 23. , And output to the CAM block 11, and the process proceeds to step S5.
[0072]
In step S5, the CAM block 11 inputs data from the logical block 21 in synchronization with the system clock from the test control unit 31, registers the data in a free address of the CAM block 11, and proceeds to step S6. . On the other hand, when it is determined in step S3 that the control signal input from the test control unit 31 is not an entry command, the processing in steps S4 and S5 is skipped, and the logic block 21 proceeds to step S6.
[0073]
In step S6, the logic block 21 determines whether or not the control signal input from the test control unit 31 is a test start command, and the control signal input from the test control unit 31 is a test start command. If it is determined, the logic block 21 proceeds to step S7 to start a noise resistance inspection process. This noise resistance inspection processing will be described with reference to the flowchart in FIG. Note that when the test control unit 31 inputs the test start command, it simultaneously writes predetermined data into a register included in the logical block 21.
[0074]
In step S41, the logic block 21 sets the semiconductor integrated circuit 1 to the test mode, and proceeds to step S42. That is, the logic block 21 executes control to cause the selector 23 to select data from the high-speed sequencer 22. Further, the logical block 21 supplies a high-speed sequencer 22 with an instruction of a search interval, an instruction of the CAM block 11 to be searched, an instruction of the content of the search key data, and an instruction of the mask function of the CAM block 11. Control for causing the CAM block 11 to be searched.
[0075]
In step S43, the high-speed sequencer 22 generates search key data based on the instruction of the content of the search key data based on the control from the logical block 21, and the process proceeds to step S44. Then, in step S44, the high-speed sequencer 22 outputs the generated search key data, the mask signal, and the search timing signal to the CAM block 11 to be searched through the selector 23, and proceeds to step S45.
[0076]
In step S45, the CAM block 11 continuously searches for search key data from the high-speed sequencer 22 from data registered in the CAM block 11 in advance based on the search timing signal from the high-speed sequencer 22.
[0077]
On the other hand, the test control unit 31 outputs a control signal as a test start command to the logic block 21 and then outputs a control signal as a read command to the logic block 21 every clock.
[0078]
In response to this, the logic block 21 reads out the predetermined data written in the register at the same time as the control signal as the test start command by the test control unit 31 in step S46, and 31. Thus, the test control unit 31 can evaluate the data in the register of the logical block 21 and check the state of the logical block 21.
[0079]
The processing in steps S45 and S46 is processing that is executed in parallel and continuously. A control signal, which is a noise resistance test end command, is input from the test control unit 31 to the logic block 21, and in step S47, the logic block The process is repeated continuously until it is determined that the inspection process ends.
[0080]
If it is determined in step S47 that the inspection processing is to be ended, the process returns to step S1 in FIG. 7, and the subsequent processing is repeated.
[0081]
As described above, the CAM block 11 is continuously searched by the high-speed sequencer 22, so that in the semiconductor integrated circuit 1, in the state where the noise is the most intense, that is, in the state where the condition such as the power supply is the worst, the logic becomes The block 21 can be operated and the logic block 21 can be checked.
[0082]
Therefore, when the logic block 21 is operated without performing a search operation on the CAM block 11 and it is confirmed that the operation is normal, the circuit of the CAM block 11 in the semiconductor integrated circuit 1 becomes unstable. It is possible to clarify the cause of whether there is, or whether the operation of the CAM block 11 itself is normal, but the logic block 21 malfunctions due to noise when the CAM block 11 operates. That is, in the noise resistance test, the above-described test for inspecting the logical block 21 when the CAM block 11 is continuously operated is performed, the inspection for both the CAM block 11 and the logical block 21 is performed, and only the logical block 21 is operated. When used in combination with an inspection or the like, the cause of the failure of the semiconductor integrated circuit 1 can be clearly specified. As a result, a response corresponding to the cause can be taken promptly.
[0083]
Furthermore, by changing the search conditions of the CAM block 11 in the inspection processing, it is possible to inspect the influence of the CAM block 11 operating under each search condition. For example, by changing the search interval, the power consumption of the CAM block 11 can be changed for inspection. By specifying the CAM block 11 to be searched, the influence on the physical position from the logical block 21 can be checked. The effect of the contents (bit-dependent) of the search key data can be checked. Further, by changing the setting of the mask function, the influence on the mask function can be inspected. These inspections can further clarify the cause of the defect.
[0084]
Note that, in this specification, the steps shown in the flowchart include not only processes performed in chronological order according to the described order, but also processes executed in parallel or individually, although not necessarily performed in chronological order. Including.
[0085]
【The invention's effect】
As described above, according to the present invention, the cause of a failure due to the influence of power supply noise can be clearly identified.
[Brief description of the drawings]
FIG. 1 illustrates a conventional method for testing a semiconductor integrated circuit.
FIG. 2 is a block diagram illustrating a configuration example of a semiconductor integrated circuit to which the present invention has been applied.
FIG. 3 is a block diagram showing a detailed configuration example of the semiconductor integrated circuit of FIG. 2;
FIG. 4 is a diagram illustrating a mask function of the CAM block in FIG. 3;
FIG. 5 is a timing chart illustrating a search operation of the semiconductor integrated circuit of FIG. 2;
FIG. 6 is a timing chart illustrating an inspection operation of the semiconductor integrated circuit of FIG. 2;
FIG. 7 is a flowchart illustrating processing of the semiconductor integrated circuit of FIG. 2;
FIG. 8 is a flowchart illustrating a CAM block search process in step S2 of FIG. 7;
FIG. 9 is a flowchart illustrating a noise resistance inspection process in step S7 of FIG. 7;
[Explanation of symbols]
Reference Signs List 1 semiconductor integrated circuit, 11-1 to 11-8 CAM block, 12 low power consumption block, 21 logic block, 22 selector, 23 high-speed sequencer, 31 test control unit, 41 data bus, 42 internal bus, 43 data bus

Claims (6)

An inspection circuit for inspecting a semiconductor integrated circuit having a first block that can be a noise source and a second block that receives noise from the first block,
Determining means for determining whether or not a test command for testing the semiconductor integrated circuit has been received;
Generating means for generating data for operating the first block when the determining means determines that the inspection command has been received;
Output means for continuously outputting the data generated by the generation means to the first block,
An inspection circuit that inspects the second block when the first block is operating based on the data output by the output unit. The inspection circuit according to claim 1, wherein the first block is configured by a CAM (Content Addressable Memory). A setting unit that sets a search condition for performing a search operation on the first block when the determination unit determines that the inspection command has been received,
The inspection circuit according to claim 1, wherein the generation unit generates the data based on the search condition set by the setting unit. The search condition is a search operation interval of the first block, a content of the data generated by the generation unit, a position of a search target block in the first block, or a mask function of the first block. 4. The test circuit according to claim 3, wherein When it is determined by the determining means that the inspection command has been received, the data output by the output means is selected and output to the first block, and it is determined by the determining means that the inspection command has not been received. 2. The inspection circuit according to claim 1, further comprising: a selection unit that selects data output from the second block and outputs the selected data to the first block. An inspection method for inspecting a semiconductor integrated circuit having a first block that can be a noise source and a second block that receives noise from the first block,
A determining step of determining whether a test command for testing the semiconductor integrated circuit has been received;
A generating step of generating data for operating the first block when it is determined that the inspection command has been received by the processing of the determining step;
An output step of continuously outputting the data generated by the processing of the generation step to the first block,
An inspection method for inspecting the second block when the first block is operating based on the data output by the processing of the output step.

Images