JP2004309174A - Scan test pattern input method and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a scan test pattern input method capable of minimizing tester memory capacity for storing test patterns and reproducing all the test patterns created by ATPG. <P>SOLUTION: Flip flops, a storage element inside a semiconductor integrated circuit, are connected in a chain shape to constitute a scan chain 101. When signals in a scan clock unit outputted from a random pattern generator 102 for generating pseudo random signals at prescribed periods are matched with patterns in a scan clock unit inputted to the scan chain 101 of the ATPG patterns, a scan clock selection decoder 103 supplies a clock for inputting the signals in a scan clock unit outputted from the random pattern generator 102. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a scan test method for a scan-designed semiconductor integrated circuit and a configuration for realizing the scan test method.
[0002]
[Prior art]
2. Description of the Related Art As a technique for facilitating a test of a semiconductor integrated circuit, conventionally, flip-flops such as storage elements in a semiconductor integrated circuit are connected in a chain and a flip-flop connected in a chain using a shift register (hereinafter referred to as scan). (Referred to as Patent Documents 1 to 4, for example).
[0003]
When performing a scan test, first, the scan chain is switched to the shift operation, and while a periodic clock is input to the scan chain, a signal value, which is a test pattern, is applied periodically from the outside in synchronization with the clock, and the chain is switched. A test pattern is set in the scan chain by sequentially shifting the connected flip-flops. After that, the scan chain is switched to the normal operation, and the combination circuit is actually operated. Then, the scan chain is shifted again to sequentially output response patterns from the scan data output terminal. The above processing is repeated for each test pattern set in the scan chain.
[0004]
Test pattern data required for the test is stored in a memory in a tester outside the circuit, and is read from the memory and set in a scan chain prior to the test. Usually, a scan chain is divided into a plurality of scan chains, and all the scan chains are simultaneously shifted by a scan clock. Then, every time the scan clock is applied, the test pattern data stored in the tester is sequentially taken into each scan chain in parallel.
[0005]
A test pattern to be set in a flip-flop at the time of a test is generally generated by ATPG (Automatic Test Pattern Generator; test generation program) in which various types of test patterns are generated in consideration of all the possibilities, and the generated test patterns are generated for each test pattern. The desired test is executed by sequentially setting the flip-flops connected in a chain. The ATPG software tool is a very effective means in that it can generate various test patterns that guarantee almost perfect failure detection rates for various manufacturing failure (failure) models.
[0006]
FIG. 6 is a block diagram showing a configuration example of a conventional scan test. A scan chain in which flip-flops and the like, which are storage elements in a semiconductor integrated circuit (LSI chip) 70, are connected in a chain is formed. Are sequentially shifted to set and output values. The scan chain is divided into a plurality (32 in the figure) and configured as a scan chain bundle 71. On the other hand, the tester 72 has a tester memory 73 and a scan clock generator. The tester memory 73 stores a test pattern generated by ATPG.
[0007]
When performing a scan test, first, test pattern data stored in a tester memory 73 is input to a scan chain bundle 71 composed of 32 scan chains in parallel in 32 bits in synchronization with a scan clock. Thus, a test pattern is set in the scan chain bundle 71. Then, a predetermined scan test is executed for each set test pattern.
[0008]
[Patent Document 1]
JP-A-10-197603
[Patent Document 2]
JP 2000-258500 A
[Patent Document 3]
JP 2002-174518 A
[Patent Document 4]
US Patent No. 6,327,687
[0009]
[Problems to be solved by the invention]
In the configuration of FIG. 6, when a scan test is performed, test patterns stored in the tester memory 73 are sequentially shifted and input from the input side of a scan chain bundle 71 composed of 32 scan chains in accordance with an external scan clock. However, in order to set the values of all the flip-flops that have been scanned, as the tester memory 73 provided externally, a memory capacity equal to the number of flip-flops is required, and these memories are previously stored. Since an operation of storing the test pattern is required, a large cost is required for the test (tester).
[0010]
For example, if the failure detection target by the ATPG tool is a possible failure in a particular part of the circuit, only very few scan cells (flip-flops) are designated to detect this particular failure. , Many remaining scan cells (flip-flops) in the scan chain are filled with don't care values (random values that may be “0” or “1”) and stored in one tester memory. Therefore, even though there are many values that do not need to be specified in the test pattern, they must all be stored in the tester memory as don't care values. A large capacity tester memory 73 is required.
[0011]
In Patent Document 2 or Patent Document 3, instead of using a pattern generator in which a pattern to be generated in advance is set, a pseudo-random generator capable of generating a random pattern is used, and a random pattern is used for a scan chain. Is described, but this method is not always an efficient test method because an optimal pattern is not always set as a test pattern.
[0012]
Patent Document 4 discloses that a test pattern generated by the ATPG is compressed and stored in a tester memory, and the compressed data is decompressed during a test and set as a test pattern in a scan chain. Although a technique for reducing the memory area is described, there is a problem that hardware for decompression is required, and not all of the compressed ATPG patterns can be reproduced by the decompression hardware.
[0013]
In view of the above problems, an object of the present invention is to provide a scan test pattern input method capable of minimizing a tester memory capacity for storing test patterns and reproducing all test patterns generated by ATPG. .
[0014]
[Means for Solving the Problems]
The present invention relates to a method of inputting a scan test pattern to a scan chain in which flip-flops, which are storage elements in a semiconductor integrated circuit, are connected in a chain, wherein a scan pattern is output from a random pattern generator that generates a pseudo-random signal of a predetermined period. The scan clock unit when the random pattern signal in the scan clock unit matches the scan clock unit pattern input to the scan chain of the ATPG pattern generated by the ATPG (test generation program) or has a don't care relationship The ATPG pattern is set in the semiconductor integrated circuit by sequentially shifting the random pattern signal of (1) into the scan chain.
[0015]
The scan test pattern input device according to the present invention comprises: a random pattern generating means for generating a pseudo random signal of a predetermined period to output a random pattern signal in scan clock units to a scan chain in a semiconductor integrated circuit; When the random pattern signal of the scan clock unit output from the scan pattern unit matches the pattern of the scan clock unit input to the scan chain of the ATPG pattern generated by the ATPG (test generation program) or has a don't care relationship, Test pattern input control means for inputting a random pattern signal in scan clock units output from the random pattern generator to the scan chain.
[0016]
Further, the semiconductor integrated circuit of the present invention includes a scan chain in which flip-flops as storage elements inside the semiconductor integrated circuit are connected in a chain, a random pattern generator for generating a pseudo-random signal of a predetermined period, and a random pattern generator for generating the random pattern. When the scan clock unit random pattern signal output from the device and the scan clock unit pattern input to the scan chain of the ATPG pattern generated by the ATPG (test generation program) match or have a don't care relationship, A scan clock selection decoder for supplying a clock for shifting the random pattern signal in scan clock units to the scan chain to the scan chain.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing a first embodiment of the present invention, in which a scan chain 101 in which flip-flops and the like, which are storage elements in a semiconductor integrated circuit, are connected in a chain, and a pseudo random signal of a predetermined period is generated. A random pattern generator 102 that outputs a signal when the signal on the ATPG pattern input to the scan chain 101 matches the signal output from the random pattern generator 102 from the random pattern generator 102 to the scan chain 101. A scan clock selection decoder 103 that supplies a clock to be input to the scan chain 101 is provided.
[0018]
The scan chain 101 is composed of m (m is 1 or 2 or more) scan chains, and an m-bit random pattern signal is output from the random pattern generator 102 every clock, and each of the m-bit random pattern signals is output. The bits correspond to the m scan chains, and one bit in the m-bit random pattern signal is input to the corresponding scan chain every clock for the m scan chains.
[0019]
A clock signal and a scan clock selection signal are input to the scan clock selection decoder 103, and the clock signal input when the scan clock selection signal permits (selects) transmission of the scan clock is used as a scan shift clock as a scan chain clock. 101. The scan clock selection signal is generated based on the ATPG pattern and the pseudo-random signal generated from the random pattern generator 102, stored in a tester memory or the like, read out when the test pattern is set, and input to the scan clock selection decoder 103. You.
[0020]
The random pattern generator 102 is composed of, for example, a combination of a shift register and an EX-OR circuit, and generates a random pulse train of a certain period determined by the configuration by applying a clock pulse to the combination, or from the outside. A circuit that can be controlled may be used, or a signal may be directly applied from the outside. Since the pattern of the random signal output from the random pattern generator 102 can be estimated in advance, if the ATPG pattern set in the scan chain 101 is determined, the data for selectively controlling the scan clock can be determined in scan clock units.
[0021]
For example, scan clock selection control data for each ATPG pattern is stored in the tester memory, and for each ATPG pattern set in the scan chain 101, the corresponding scan clock selection control data is used as a scan clock selection signal for the random pattern generator 102. By reading in synchronization with the generation of a random signal in units of clocks, a desired ATPG pattern can be set in the scan chain 101.
[0022]
FIG. 2 is a schematic diagram showing the principle of the scan test pattern input operation of the present embodiment. FIG. 2 illustrates a case where the scan chain 101 is configured as a chain bundle including six scan chains.
[0023]
An ATPG pattern generated by an ATPG (test generation program) and input to the scan chain 101 every time a scan clock is input includes (0xx0xx), (1xx0x1),. (× is a don't care value), and the 6-bit random signal pattern output from the random pattern generator 102 for each clock (t1, t2, t3,...) Is (010011), (110010), (101001),. Is shown.
[0024]
Since the random signal pattern (010011) in the clock (t1) matches or has a don't-care relationship with the ATPG pattern (0xx0xx) input by the first scan clock, the scan clock selection decoder 103 A selection signal is input. Therefore, at the clock (t1), the scan clock is supplied from the scan clock selection decoder 103 to the scan chain 101, and the signals "0, 1, 0, 0, 1, 1" are supplied to the six scan chains in synchronization with the scan clock. Shift input.
[0025]
Next, since the random signal pattern (110010) in the clock (t2) does not match the ATPG pattern (1 × 0 × 1) input in the second scan clock, the scan clock selection decoder 103 supplies the scan clock selection signal to the scan clock selection decoder 103. Is not entered. Therefore, at the clock (t2), the scan clock is not supplied from the scan clock selection decoder 103 to the scan chain 101, and the random signal pattern (110010) is discarded.
[0026]
Next, since the random signal pattern (101001) at the clock (t3) matches or has a don't-care relationship with the ATPG pattern (1 ×× 0 × 1) input at the second scan clock, the scan clock selection decoder 103 Is supplied with a scan clock selection signal. Accordingly, at the clock (t3), the scan clock is supplied from the scan clock selection decoder 103 to the scan chain 101, and the signals "1, 0, 1, 0, 0, 1" are synchronized with the scan clock to the six scan chains. Shift input. Thereafter, by repeating the same operation, a desired ATPG pattern is set in the scan chain 101.
[0027]
Therefore, the tester memory stores, for each generated ATPG pattern, the clock number data to be adopted as the scan clock from among the pseudo random signals in scan clock units generated from the random pattern generator 102, for generating the pseudo random signal. The time point is stored as a reference (clock numbers t1, t3,... In the case of the embodiment), and the clock from the time when the generation of the pseudo-random signal in scan clock units is started to set the ATPG pattern in the semiconductor integrated circuit. The ATPG pattern can be set by sequentially inputting the pseudo-random signal when the count value matches the scan value to the scan chain.
[0028]
Alternatively, a shift register is used as a tester memory, and for each ATPG pattern generated in the shift register, a clock to be adopted is set to “1” (or “1” (or “0”) in the pseudo random signal in scan clock units generated from the random pattern generator 102. “0”), the clocks that are not adopted are stored in order from the start of the clock as “0” (or “1”) (1, 0, 1,... The data is read out in synchronization with the unit pseudo-random signal generation clock, and if it is "1" (or "0"), the scan clock unit pseudo-random signal at that time is input to the scan chain, and "0" (or "1"). ), The pseudo random signal in the unit of the scan clock at that time is discarded, so that the A PG pattern may be set.
[0029]
FIG. 3 is a flowchart showing the scan test pattern input operation of the present embodiment. Note that FIG. 3 assumes a case where clock number data used as a scan clock is stored in the tester memory. Hereinafter, the scan test pattern input operation of the present embodiment will be described with reference to FIGS.
[0030]
The tester memory stores data (for example, clock numbers t1 and t3) corresponding to a clock number from the start of pseudo-random signal generation to be employed as a scan clock among pseudo-random signals in scan clock units generated from the random pattern generator 102 and employed as a scan clock. ,...) Are stored corresponding to the ATPG pattern set in the scan chain 101. When the clock input for setting the ATPG pattern to the semiconductor integrated circuit is started (step S1), the first clock number (t1 in the embodiment) is read from the tester memory (step S2).
[0031]
Simultaneously with the start of the clock input, the random pattern generator 102 outputs a pseudo-random signal in scan clock units in synchronization with the input clock (step S3), and counts the number of input clocks from the start of the clock input. (Step S4).
[0032]
Next, the clock number read from the tester memory is compared with the input clock count value from the start of clock input (step S5). If the two match, the scan clock selection decoder 103 sends the shift clock to the scan chain 101. After inputting the pseudo random signal in scan clock units generated corresponding to the clock input to the scan chain 101 (step S6), it is determined whether all clock numbers stored in the tester memory have been read out. Is determined (step S7).
[0033]
On the other hand, when the clock number read from the tester memory and the input clock count value do not match, the shift clock from the scan clock selection decoder 103 to the scan chain 101 is stopped, and the scan clock generated corresponding to the clock input is stopped. The unit pseudo random signal is discarded (step S8).
[0034]
If all the clock numbers stored in the tester memory have not been read out in Step 7, or if Step 8 has been executed, the next clock number is read from the tester memory (Step S9), and Steps 3 to 8 are performed. repeat. When all the clock numbers stored in the tester memory have been read out in step 7, the test pattern setting ends (step S10). These processes can also be realized by software processing by a program.
[0035]
According to the present embodiment, the test pattern memory for scan test stores clock numbers (t1, t2, t3,...) From the time when the random pattern generator 102 starts generating a random pattern in scan clock units. Which clock number is adopted as the scan clock of the scan chain 101 is stored in correspondence with the generated ATPG pattern, and the random pattern generator 102 starts the shift input operation of the scan chain 101 by the clock signal. By reading from the time point, an ATPG pattern as expected can be set.
[0036]
Also, as a tester memory, for each generated ATPG pattern, clock number data to be adopted as a scan clock from among pseudo random signals in scan clock units generated from the random pattern generator 102 (in the above embodiment, the clock number t1 is used). , T3,...) Is sufficient, the test pattern information is compressed, and the tester memory is reduced.
[0037]
FIG. 4 is a block diagram showing a second embodiment of the present invention. In the present embodiment, after flip-flops in the semiconductor integrated circuit (LSI chip) 100 are scanned, the flip-flops are scanned into a plurality (three in this embodiment) of groups (scan chain bundles) 111 to 113 composed of, for example, 32 scan chains. To divide. Each of the scan chain bundles (hereinafter, chain bundles A, B, and C) is configured to be controllable by an independent scan clock.
[0038]
In the present embodiment, the pseudo-random signal in scan clock units (32 bits) output from the random pattern generator 102 that generates a pseudo-random signal of a predetermined cycle is input to the chain bundles A, B, and C in parallel. . On the other hand, the scan clock selection decoder 103 decodes, for example, a 2-bit clock selection control signal input from the tester 130, thereby forming a chain bundle to which a 32-bit pseudo-random signal output from the random pattern generator 102 is to be input. And supplies a scan clock only to the selected chain bundle. Therefore, the pseudo random signal in scan clock units is input only to the chain bundle selected for each clock.
[0039]
When the pseudo-random signal in scan clock units (32 bits) output from the random pattern generator 102 does not match any of the test patterns in the scan clock units (32 bits) of the chain bundles A, B, and C , The scan clock is not supplied to any of the chain bundles A, B, and C, and the pseudo random signal in the unit of the scan clock is discarded.
[0040]
In the case of the first embodiment, since all scan chains are controlled by the same clock when the scan test pattern is set, all the flip-flops are in the operating state during the scan shift, and the power consumption increases. In general, power supply design is performed in consideration of normal operation.For this reason, when the number of scan chains increases, power consumption drops more than expected when setting scan test patterns, causing problems such as power supply voltage drop. However, the circuit may not operate normally.
[0041]
In the present embodiment, the number of scan flip-flops operating simultaneously can be reduced by selecting and controlling a scan clock at the time of scan shift, thereby selecting a scan chain (chain bundle) to be operated. The power consumption at the time of shifting can be suppressed, and in addition to the effect of compressing the test pattern information, the effect of suppressing the malfunction of the circuit caused by the increase in power consumption can be expected.
[0042]
FIG. 5 is a schematic diagram showing the principle of the scan test pattern input operation of the present embodiment. FIG. 5 shows a case where each of the chain bundles A, B, and C is configured as a chain bundle composed of six scan chains, and ATPG patterns are sequentially input from left to right in the figure. Shall be.
[0043]
In FIG. 5, the ATPG pattern input to each of the chain bundles A, B, and C every time the scan clock is input is (1 × 0 × 1), (0 ××× 1) in the chain bundle A. ,..., (× 0 × 110 ×), (× 0 × 110),..., For the chain bundle C, (× 1 ×××), (0 ×××××),. (× is a don't care value), and the 6-bit random signal pattern output from the random pattern generator 102 for each clock (t1, t2, t3,...) Is (010011), (110010), ( 101001),.
[0044]
Since the random signal pattern (010011) at the clock (t1) matches or has a don't-care relationship with the ATPG pattern (0xx0xx) input by the first scan clock of the chain bundle B, the tester memory 131 , A 2-bit clock selection control signal for selecting the chain bundle B is input to the scan clock selection decoder 103. Accordingly, at the clock (t1), the scan clock is supplied from the scan clock selection decoder 103 to the chain bundle B, and the signals “0, 1, 0, 0, 1, 1” are input to the six scan chains of the chain bundle B. You.
[0045]
Next, the random signal pattern (110010) in the clock (t2) is the ATPG pattern (1 × 0 × 1) input by the first scan clock of the chain bundle A, and the second scan of the chain bundle B. Since it does not match any of the ATPG pattern (× 0 × 110) input by the clock and the ATPG pattern (× 1 × XXX) input by the first scan clock of the chain bundle C, the tester memory 131 A clock selection control signal that does not select any chain bundle is input to the scan clock selection decoder 103. Therefore, at the clock (t2), the scan clock from the scan clock selection decoder 103 is not supplied to any chain bundle, and the random signal pattern (110010) is discarded.
[0046]
Next, since the random signal pattern (101001) at the clock (t3) matches or does not care with the ATPG pattern (1 × 0 × 1) input by the first scan clock of the chain bundle A, A 2-bit clock selection control signal for selecting the chain bundle A is input from the tester memory 131 to the scan clock selection decoder 103. Accordingly, at the clock (t3), the scan clock is supplied from the scan clock selection decoder 103 to the chain bundle A, and the signals "1, 0, 1, 0, 0, 1" are input to the six scan chains of the chain bundle A. You.
[0047]
Hereinafter, by repeating the same operation, a desired ATPG pattern is set for each of the chain bundles A, B, and C. Therefore, for example, the clock adopted as the scan clock is set to “1” and the clock not adopted is set to “0” and stored sequentially from the clock start (in the above embodiment, the chain bundle A is 0, 0, 1,..., And the chain bundle B is 1, 0, 0,..., The chain bundle C is provided with a shift register for each chain bundle, and is synchronized with the clock from the clock input start time for setting the ATPG pattern in the semiconductor integrated circuit. The ATPG pattern can be set by reading the value of each shift register and sequentially inputting the generated pseudo-random signal in scan clock units to the corresponding chain bundle.
[0048]
Usually, a pattern generated by the ATPG test includes a lot of don't care values (either 0 or 1), and in many cases, it is necessary to set the value to a specific value (0 or 1). There are very few flip-flops. As the don't care value increases, the probability that the pattern generated by the random pattern generator of the present invention is input to any one of the scan bundles increases, and it is possible to set a scan test pattern with a small pattern memory capacity and extremely efficient. Become.
[0049]
Further, in two or more of the chain bundles A, B, and C, the test pattern in scan clock units matches the scan clock unit pseudo-random signal output from the random pattern generator 102 or has a don't care relationship. In some cases, a scan clock can be supplied to a plurality of chain bundles having the same or don't care relationship, and the pseudo-random signal can be simultaneously input to two or more chain bundles. In this case, although the clock selection control signal has three bits, the number of times of generating a pseudo-random signal in scan clock units can be reduced, thereby increasing the compression efficiency.
[0050]
In the present embodiment, at the time of a test after setting a scan test pattern, XOR circuits 121 to 123 that take an exclusive OR of test data output from each scan chain for each group (chain bundle), and XOR Although the configuration including the MUX 124 for outputting the output results from the circuits 121 to 123 to the tester memory 131 is shown, these configurations are well known in the art, and are directly related to the features of the present invention (test pattern setting). Since it is not related, the detailed description is omitted.
[0051]
Further, in the present embodiment, a random pattern generator is used as the test pattern generating means. However, the present invention is not particularly limited to the random pattern generator, and corresponds to, for example, the number of scan chain bundles. Any test pattern generating means capable of generating a combination pattern can be used.
[0052]
Further, in the present embodiment, the number of scan chains in each scan chain bundle is all set equal, but the number of scan chains in each scan chain bundle is not necessarily equal, and the number of scan chains in each scan chain bundle is not necessarily equal. The number of scan chains can be different.
[0053]
In that case, the test pattern generating means may reduce the number of scan chains smaller than that if at least the configuration is such that a test pattern signal in scan clock units can be output to the scan chain bundle having the maximum number of scan chains. A scan chain bundle can be handled by selecting the number of bits equal to the number of scan chains from the bundle. Alternatively, test pattern generating means may be provided individually for each scan chain bundle.
[0054]
【The invention's effect】
According to the present invention, a clock number from the time when the random pattern generator starts generating a random pattern in units of scan clocks, and which clock number are used as the scan clocks of the scan chain, are used in the test memory for the scan test. This is stored in association with the generated ATPG pattern, and is read out from the point in time at which the random pattern generator starts the shift input operation of the scan chain by the clock signal, whereby the ATPG pattern can be set. Therefore, it is sufficient for each generated ATPG pattern to have a memory capacity large enough to store clock number data used as a scan clock from among pseudo random signals in scan clock units generated from the random pattern generator. Test pattern information is compressed, and less tester memory is required.
[0055]
Also, when a scan chain is divided into a plurality of scan chain bundles, a scan chain bundle to be operated can be selected by selecting and controlling a scan clock at the time of a scan shift, and the number of scan flip-flops operating simultaneously can be selected. Therefore, power consumption during scan shift can be suppressed, and in addition to the effect of compressing test pattern information, the effect of suppressing malfunction of the circuit can be expected.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of the present invention.
FIG. 2 is a schematic diagram for explaining a scan test pattern input operation according to the first embodiment.
FIG. 3 is a flowchart illustrating a scan test pattern input operation according to the embodiment;
FIG. 4 is a block diagram showing a second embodiment of the present invention.
FIG. 5 is a schematic diagram for explaining a scan test pattern input operation according to the second embodiment.
FIG. 6 is a block diagram showing a configuration example of a conventional scan test.
[Explanation of symbols]
100 LSI chip
101 scan chain
102 random number generator
103 Scan clock selection decoder
111-113 Scan chain bundle
121-123 XOR circuit
124 multiplexer
130 tester
131 tester memory

Claims (20)

In a method of inputting a scan test pattern to a scan chain in which flip-flops as storage elements inside a semiconductor integrated circuit are connected in a chain,
The scan clock unit when the test pattern signal generated in the scan clock unit matches the pattern of the scan clock unit input to the scan chain of the ATPG pattern generated by the ATPG (test generation program) or has a don't care relationship. A scan test pattern input method, wherein the ATPG pattern is set in the semiconductor integrated circuit by sequentially shifting the test pattern signal into the scan chain. The scan chain is composed of m (m ≧ 2) scan chains, and outputs at least m bits of test pattern signals in scan clock units at each clock. Each bit of the test pattern signal and the m number of scan chains are output. A scan chain corresponding to the scan chain, and each bit of the m-bit test pattern signal is input in parallel to the corresponding scan chain for each clock for the m scan chains. 2. The scan test pattern input method according to claim 1, wherein: The scan chain is divided into n (n ≧ 2) scan chain bundles composed of m (m ≧ 2) scan chains, and at least m bits of test pattern signals in scan clock units are output every clock. Each bit of the test pattern signal corresponds to the m scan chains in each scan chain bundle, and the m scan chains in each scan chain bundle correspond to the m scan chains every one clock. 2. The scan test pattern input method according to claim 1, wherein each one bit in the m-bit test pattern signal is input in parallel to the corresponding scan chain in each of the scan chain bundles. The scan chain is divided into n (n ≧ 2) scan chain bundles including a scan chain bundle composed of different numbers of scan chains, and for each scan chain bundle, each scan chain bundle includes one scan clock bundle. A test pattern signal of the scan clock unit consisting of bits equal to the number of scan chains is output, and each bit of the test pattern signal corresponds to the scan chain in each scan chain bundle. 2. The method according to claim 1, wherein each bit of the test pattern signal is input in parallel to the corresponding scan chain in each of the scan chain bundles for each clock for the scan chains in the scan chain. The described scan test pattern input method. 5. The scan test pattern input method according to claim 1, wherein the test pattern signal is output from a random pattern generator that generates a pseudo-random signal having a predetermined period. A test pattern generating means for outputting a test pattern signal in scan clock units to a scan chain in the semiconductor integrated circuit; and the test pattern signal in scan clock units output from the test pattern generating means is provided by an ATPG (test generation program). When the generated ATPG pattern matches or has a don't-care relationship with a scan clock unit pattern input to the scan chain, a scan pattern unit test pattern signal output from the test pattern generation unit is input to the scan chain. And a test pattern input control means. The test pattern input control means includes: a clock for generating the test pattern signal in scan clock units having a match or don't care relationship with an ATPG pattern set on a scan chain among clocks from the start of the test pattern signal generation. A tester memory storing information, and a scan for supplying a clock for shifting the test pattern signal in scan clock units to the scan chain based on the clock information read from the tester memory to the scan chain. The scan test pattern input device according to claim 6, further comprising a clock selection decoder. The tester memory stores a clock number for generating a test pattern signal in scan clock units corresponding to an ATPG pattern set on a scan chain among clock numbers from the start of the test pattern signal generation. The scan test pattern input device according to claim 7, wherein: The tester memory sets a clock to be used to "1" (or "0") among test pattern signals in scan clock units generated from the test pattern generation means in accordance with an ATPG pattern set on a scan chain. 8. The scan test pattern input device according to claim 7, wherein the scan test pattern input device is constituted by a shift register that stores the clock not adopted as "0" (or "1") in order from the start of the clock. The scan chain is composed of m (m ≧ 2) scan chains, and the test pattern generating means outputs at least m bits of a test pattern signal in units of the scan clock every clock, and outputs the test pattern signal. Each bit corresponds to the m scan chains, and each bit in the m-bit test pattern signal is parallel to the corresponding scan chain every clock for the m scan chains. The scan test pattern input device according to any one of claims 6 to 9, wherein the scan test pattern input device is inputted. The scan chain is divided into n (n ≧ 2) scan chain bundles composed of m (m ≧ 2) scan chains, and the test pattern generator generates at least m bits of the scan chain every clock. A test pattern signal in scan clock units is output, and each bit of the test pattern signal corresponds to the m scan chains in each scan chain bundle, and the m scan chains in each scan chain bundle are output. 7. The scan chain according to claim 6, wherein each one bit of the m-bit test pattern signal is input in parallel to the corresponding scan chain in each of the scan chain bundles every clock. 10. The scan test pattern input device according to any one of items 9. The scan chains are divided into n (n ≧ 2) scan chain bundles including scan chain bundles composed of different numbers of scan chains, and the test pattern generator outputs each scan chain bundle every clock. The test pattern signal in the unit of the scan clock composed of bits equal to the number of the scan chains in the scan chain is output, and each bit of the test pattern signal corresponds to the scan chain in each of the scan chain bundles. The method according to claim 1, wherein each bit in the test pattern signal is input in parallel to the corresponding scan chain in each of the scan chain bundles every clock for the scan chain in the chain bundle. 10. The scan test pattern input device according to any one of 6 to 9. The test pattern generation unit is configured as a random pattern generation unit that outputs a random pattern signal in scan clock units to a scan chain inside the semiconductor integrated circuit by generating a pseudo random signal of a predetermined cycle. The scan test pattern input device according to any one of claims 6 to 12. A scan chain in which flip-flops as storage elements in a semiconductor integrated circuit are connected in a chain, a test pattern generator for generating a test pattern signal of a predetermined period, and a test in scan clock units output from the test pattern generator When receiving a signal indicating that the pattern signal and the pattern of the ATPG pattern generated by the ATPG (test generation program) in the scan chain input to the scan chain match or don't care, the scan clock A semiconductor integrated circuit, comprising: a scan clock selection decoder that supplies a clock for shifting and inputting a unit test pattern signal to the scan chain to the scan chain. The scan chain is composed of m (m ≧ 2) scan chains, and the test pattern generator outputs at least m bits of a test pattern signal for each scan clock in units of the scan clock. Each bit corresponds to the m scan chains, and each bit in the m-bit test pattern signal is parallel to the corresponding scan chain every clock for the m scan chains. The semiconductor integrated circuit according to claim 14, wherein the signal is input to the semiconductor integrated circuit. The scan chain is divided into n (n ≧ 2) scan chain bundles composed of m (m ≧ 2) scan chains, and the test pattern generator generates at least m bits of the scan chain every clock. A test pattern signal in scan clock units is output, and each bit of the test pattern signal corresponds to the m scan chains in each scan chain bundle, and the m scan chains in each scan chain bundle are output. 15. The method according to claim 14, wherein each one bit of the m-bit test pattern signal is input in parallel to the corresponding scan chain in each of the scan chain bundles every clock for a scan chain. A semiconductor integrated circuit as described in the above. The scan chains are divided into n (n ≧ 2) scan chain bundles including scan chain bundles composed of different numbers of scan chains, and the test pattern generator outputs each scan chain bundle every clock. A test pattern signal in the unit of the scan clock, which is composed of bits equal to the number of scan chains in the scan chain, is output. Each bit of the test pattern signal corresponds to the scan chain in each scan chain bundle, and each scan The method according to claim 1, wherein each bit in the test pattern signal is input in parallel to the corresponding scan chain in each of the scan chain bundles every clock for the scan chain in the chain bundle. 15. The semiconductor integrated circuit according to 14. The test pattern generator is configured as a random pattern generator that outputs a random pattern signal in scan clock units to a scan chain inside the semiconductor integrated circuit by generating a pseudo random signal of a predetermined period. The scan test pattern input device according to any one of claims 14 to 17, wherein: A process of outputting a test pattern signal in scan clock units from the test pattern generating means every time a clock is input;
A clock number counting process for counting the clock from the start of the test pattern signal generation;
A tester that stores a clock number at which a test pattern signal in scan clock units having a match or don't care relationship with an ATPG pattern set on a scan chain is generated from clock numbers from the start of the test pattern signal generation. A process of reading the clock number stored first from the memory;
A test pattern signal in scan clock units generated when the counted clock number matches the clock number read from the tester memory is input to the scan chain, and the next clock number is read from the tester memory. Scan clock unit pattern input processing to be read out,
A program for causing a computer to execute the scan clock unit pattern input processing until all clock numbers stored in the tester memory are read. 20. The program according to claim 19, wherein the test pattern signal is output from a pseudo-random pattern signal generation unit having a predetermined period.

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