JPH10170609A - Logic integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logic integrated circuit which does not cause correlation in which relation between test pattern signals entered into an inspected object is always constant, and detects larger number of troubles. SOLUTION: This circuit includes an inspected circuit assembly 104 having a plurality of shift resistors in which an inspected circuit is connected to a plurality of flip-flops, and a random number pattern generator 101 and a code compressor 102 which consist of linear feedback shift resistors. A clock dividing circuit 103 is combined in a tested LSI in which the inspected circuit assembly 104, the random number pattern generator 101, and the code compressor 102 are connected each other using scan chains 105, 106, and the shift clock which is impressed to the random number pattern generator 101 is also impressed to the clock dividing circuit. The clock dividing circuit changes the period of the shift clock into, for example 1/2, 1/4, 1/8, according to signals entered from a clock control pin, and impresses it to the code compressor 102 and the plural shift resistors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic integrated circuit, and more particularly, to a logic integrated circuit having a configuration enabling a self test.

[0002]

2. Description of the Related Art In recent years, the number of input test patterns is expected to reach an enormous number with an increase in the scale of a logic circuit, and is expected to exceed the limit value of test data stored in a tester. To address this problem, as a method for more efficiently inspecting a scan-designed LSI, a BIST method in which a test is performed by incorporating an execution control circuit for testing inside a circuit under test is applied.

FIG. 4 is a conceptual diagram of a BIST. BIST
Now, a pseudo-random number test pattern generator 401 for giving a large amount of patterns to the circuit under test 402 designed for scanning,
It is composed of a code compressor 403 for compressing the output response sequence and judging pass / fail by comparing only the final code. Normal,
The pattern generator and the pattern compressor include a linear feedback shift register (Linear Feedback Sh).
if Register (hereinafter abbreviated as LFSR). The pattern generator using the LFSR can generate all patterns except for all 0s in a pseudo-random manner. Pseudo random number pattern generator using LFSR (Random Pattern Generator)
FIG. 2 shows an example of an RPG (hereinafter abbreviated as RPG).
FIG. 3 shows an example of a “Ture Register” (hereinafter abbreviated as MISR).

Next, an outline of test processing performed in the above-mentioned conventional BIST in the pseudo random number test pattern generator, the circuit under test, and the code compressor will be described with reference to FIGS. 18, 8 and 9. FIG. 18 is a diagram showing the configuration of the LSI to be inspected. The LSI to be tested is RPG10
1, a MISR 102 and a circuit under test 104. The output from each register of the RPG 101 is given to a circuit under test 104 by a scan chain 105, and scans a test pattern into a plurality of shift registers formed by connecting a plurality of flip-flops in the circuit under test 104. At the end of the test, the test output in the circuit under test 104 is written to each flip-flop constituting the shift register, and the test results stored in the flip-flop are sequentially shifted, scanned out through the scan chain 106, and stored in the MISR 102. , MIS
It is compression-coded by R102. Reference numeral 107 denotes a clock signal, which is supplied to the RPG 101, the MISR 102, and each shift register in the circuit under test 104.

Next, a test procedure will be described. RPG, MI
The same clock signal 107 is applied to the SR and each shift register of the circuit under test. That is, the shift clock shift-scans the RPG, the MISR and the circuit under test at the same timing. The transition of the state of the data scanned in the RPG and the shift register including a plurality of flip-flops when a pseudo random number pattern is input at this clock timing will be described with reference to FIGS. FIG. 8 is a state transition diagram of the scan-in data of the RPG and the flip-flop when the same shift clock is applied to the RPG, the MISR and the circuit under test.

FIG. 9 is a diagram showing a schematic internal configuration of a circuit under test. FIG. 9 mainly shows a configuration relating to the application of the pseudo random number pattern to the circuit under test, and omits the configuration relating to the output from the circuit under test to the MISR.

In the schematic diagram shown in FIG. 8, the RPG is a register 801, a register 802, a register 803, a register 8
04, a register 805, and a register 806. The register 801 stores the flip-flops 811, 812, 813, 814, 8 by the scan chain 871.
15, 816. The register 802 stores the flip-flops 821, 822, 823, 824, 8 by the scan chain 872.
25,826. The register 803 stores the flip-flops 831, 832, 833, 834, and 8 by the scan chain 873.
35, 836. The register 804 stores the flip-flops 841, 842, 843, 844, 8 by the scan chain 874.
45 and 846. The register 805 stores the flip-flops 851, 852, 853, 854, 8 by the scan chain 875.
55 and 856 are connected to the shift register. The register 806 is connected to flip-flops 861, 862, 863, 864, 8 by a scan chain 876.
65 and 866.

(1) is a state at the time of the first pseudo random number pattern generation. Since the shift clocks of the RPG, the MISR, and the scan chain are the same, the input pattern generated in the register 801 is scanned into the flip-flop 811 as it is. (2) is a state when the second pseudo random number pattern is generated. The test pattern stored in the register 801 is shifted to the register 802,
01 stores a newly generated pseudo random number pattern. Similarly, the scan-in data stored in the flip-flop 811 is also scanned in (shifted) into the flip-flop 812, and the data in the register 802 is also scanned into the flip-flop 821. This operation is sequentially repeated, and the test pattern is scanned into each flip-flop of the plurality of shift registers. A state where the above operation is repeated six times is shown in (6).

Next, FIG. 9 will be described with reference to FIG. In FIG. 9, flip-flops 811, 812,
.. Correspond to the shift register composed of flip-flops 811 to 816 in FIG. 8, and the flip-flop 811 is a register 801 of the RPG.
Scans in random number data. Dotted lines connecting the flip-flops 811, 812, 813,... Indicate that random number data is sequentially shifted. The output of each flip-flop is input to the circuit to be inspected.
The same applies to flip-flops 821, 822, 823,..., Flip-flops 831, 832, 833,..., Flip-flops 851, 852, 853,. The random number data from the RPG is sequentially input to the circuit under test via each flip-flop, and at a certain point in time, the output of the circuit under test is stored in each of the flip-flops. The connection for storing the output of the inspection target circuit in each flip-flop is omitted in the drawing.
The output of the circuit under test stored in each flip-flop is shifted on the shift register by the shift clock,
Input to MISR. At the same time, the random number data from the RPG is sequentially input to each flip-flop by the shift clock, and is input to the inspection target circuit.

Next, a certain correlation occurs between the scan-in data of the flip-flops of the respective shift registers connected to the adjacent registers in the RPG by a scan chain. A description will be given of the fact that it becomes impossible to detect. Referring to (6) of FIG. 8, when the shift clocks of the RPG, the MISR, and the flip-flop are input at the same timing, the scan-in of the flip-flop of each shift register connected to the adjacent register in the RPG by the scan chain is performed. It can be seen that there is a constant upward sloping correlation between data. Here, as an example, the register 80
The description will be made using flip-flops 813, 822, 831 connected to 1, 802, 803. When test patterns are applied at the same clock timing, the test patterns input to the flip-flop 813, the flip-flop 822, and the flip-flop 831 are always the same. The flip-flops 813, 822, 8 shown in FIG.
Since a correlation occurs that the test pattern applied to the test circuit 31 is always the same, the flip-flop 822 and the flip-flop 831
Scan-in data is always applied with the same test pattern. As a result, the output value of the EOR element 901 is always fixed at 0, and the diagnostic path of the second input pin of the AND element 904 to which the output data of the EOR element 901 is input is not activated. Indicates a failure such as a disconnection). Prior to diagnosing a product-level logic integrated circuit, the logic integrated circuit where the fault is actually located is input with various signal patterns to obtain a signal pattern that can actually detect the fault. Is
This refers to the fault that is actually located.

In the conventional BIST method, as described above, a pseudo random number pattern is generated, and scan-in data is applied while sequentially shifting and scanning the generated pattern, so that the pattern is connected as an arbitrary shift register. There is a certain correlation between the scan-in data of the flip-flop that is connected and the scan-in data of the flip-flop connected as a shift register adjacent to the shift register, and even if a large number of patterns are input, a failure occurs. The phenomenon that the detection rate does not improve occurs.

As a method for solving this phenomenon, US Pat.
Instead of connecting the scan chains directly from each register of the RPG by the method described in 59832, the scan-in data is extracted from a plurality of arbitrary registers, input to the EOR element, and the output pin is scanned. There is a method of canceling the correlation of scan-in data by linking with a chain.

[0013]

The above prior art is based on R
Since an EOR element is added to all shift registers of the PG, circuit overhead increases. Further, since the logic for canceling the correlation is physically incorporated in the logic circuit, the form of the correlation cannot be externally operated. An object of the present invention is to provide a logic integrated circuit which has a small circuit overhead, eliminates the occurrence of a correlation that the relationship between test pattern signals input to a test object is always the same, and can detect more faults. It is in.

[0014]

In order to solve the above problems, the present invention comprises a circuit to be tested, a plurality of shift registers formed by connecting a plurality of flip-flops, and a linear feedback shift register. A random number pattern generator and a code compressor are incorporated. The input side of each of the shift registers is connected to a register at a predetermined bit position of the random number pattern generator, and the output side of each of the shift registers is connected to the code compressor. A shift clock is provided to the random number pattern generator, the code compressor, and the plurality of shift registers, and outputs of the flip-flops of the plurality of shift registers are input to the inspection target circuit. The output of the circuit under test is supplied to each flip-flop of the plurality of shift registers at a designated time. In the logic integrated circuit configured to be force to enter the shift clock to generate the shift clock of a different pattern from the shift clock,
A clock control circuit for supplying the generated shift clock to the code compressor and the plurality of shift registers is incorporated. Further, the clock control circuit is a frequency dividing circuit that generates a shift clock having a different cycle in accordance with an externally applied control signal. Further, the clock control circuit is configured to generate shift clocks of different patterns according to an externally applied control signal. Further, an output signal from a register at a specific bit position of the random number pattern generator is used as the externally applied control signal.

[0015]

FIG. 1 shows a first embodiment. The LSI to be inspected includes an RPG 101, a MISR 102, a clock frequency dividing circuit 103, and a circuit under test 104. R
A scan chain 105 connects each flip-flop in the circuit under test 104 from each register of the PG 101 and scans in a test pattern. After the test is completed, the test result stored in the flip-flop is scanned in scan chain 1.
06, scan-out, store in MISR 102 and compression-encode. In this embodiment, the clock timing of the RPG 101 and the shift timing of the MISR 102 and the scan chain are operated by using the clock control pin 109 to shift the shift timing by using a clock signal dividing circuit for shifting, thereby eliminating the correlation. .

The clock frequency dividing circuit 10 used here
3 will be described with reference to FIG. Input pin 50 to frequency divider
3 is connected to a shift clock signal line. As shown in FIG. 5, the clock signal is supplied to flip-flops 521, 522, and 523.
, The cycle of the shift clock is changed to 1/2 of the cycle of the output of the flip-flop 521, 1/4 of the cycle of the output of the flip-flop 522, and 1/8 of the cycle of the output of the flip-flop 523. Can be. The changed signals are applied to control pins 501, 5
02, and the selected clock signal is transmitted from 505 and input as a clock signal for each MISR and shift scan.

FIG. 6 shows a time chart of the output pins 511, 512, 513 of each flip-flop in the frequency dividing circuit and the input clock signal. Due to the configuration of the frequency dividing circuit, the output pin 511 of the flip-flop 521 generates a pulse only half the number of the input shift clock signal. The output pin 512 of the flip-flop 522 becomes １ ／ times, and the output pin 513 of the flip-flop 523 becomes １ ／ times. The control pins 501 and 502 of the control circuit for operating these four types of clock timings are controlled according to the clock control mode shown in FIG. 7 to select appropriate clock timings.

Next, the test procedure will be described. The case of the normal mode shown in FIG. 7 has already been described with reference to FIG. 8 and FIG. First, the case of the 1/2 mode shown in FIG. 7 will be described. 501 of the control pin of the clock timing control circuit
Is set to 0, and 1 to 502. At this time, as shown in FIG. 7, the shift timing of the MISR and the flip-flop is input at a cycle of 1/2 of the number of clocks of the RPG, and a test pattern is applied to each flip-flop. FIG. 10 shows the state transition of data scanned in the RPG and the shift register including a plurality of flip-flops at this time. (1) is a state when the first pseudo random number pattern is generated. As shown in the time chart of pin 511 in FIG. 7, the first shift clock is RPG, M
Since both the ISR and the scan chain are input, the input pattern generated in the register 801 is scanned into the flip-flop 811 as it is. (2) is a state at the time of the second pseudo-random number pattern generation. The test pattern stored in the register 801 is shifted to the register 802, and the newly generated pseudo random number pattern is stored in the register 801. However, the clock signal is not input to the MISR and the scan chain as shown in the time chart of the 511 pin in FIG.
The scan-in data stored in is stored as it is. (3) is a state at the time of the third pseudo random number pattern generation. The test pattern stored in the register 801 is shifted to the register 802, the data stored in the register 802 is shifted to the register 803, and the newly generated pseudo random number pattern is stored in the register 801. According to FIG. 7, the third shift clock is RP
G, the MISR, and the scan chain are input, so that the flip-flop 812
11 is scanned in and flip-flop 8
11, data of the register 801 is scanned in the flip-flop 821, and data of the register 803 is scanned in the flip-flop 831. This operation is sequentially repeated, and the test pattern is scanned into each flip-flop. A state where the above operation is repeated six times is shown in (6).

In (6), it can be seen that a correlation different from that shown in FIG. 8 occurs when the shift clocks of the MISR and the flip-flop are set to half the number of RPGs. Referring to (6), the same test pattern is always input to the flip-flop 813, the flip-flop 832, and the flip-flop 851 when the pseudo-random number pattern is scanned into each flip-flop with a shift clock having a cycle of RPG 1/2. When a test is executed by inputting a system clock in this state, the outputs of the EOR element 902 and the EOR element 903 shown in FIG. 9 are always fixed to 0, and therefore, the hypothetical faults 915 and 916 cannot be detected. But,
Since the hypothetical faults 915 and 916 are detected when the test is executed at the same timing of the previous RPG, MISR, and flip-flop clocks, there is no problem if they cannot be detected in the 1/2 mode. As for a hypothetical fault that could not be detected in the first test at the normal clock timing and the second test at the 1/2 clock timing, it cannot be detected at the clock timing of the two states that have been executed. Detection is required. At this time, in the test in the normal mode described above, the same data is always input to the flip-flop 82.
10, different data are scanned in the flip-flop 831 as shown in FIG.
Since the output pin of the OR element 901 is not always fixed at 0, the path of the second input pin of the AND element is activated and the hypothetical fault 911 can be detected. By repeating this test a plurality of times with different clock timings, more hypothetical faults can be detected. FIG. 11 shows a 1/4 state transition. Description is omitted. However, in this embodiment, only the number of idle rotations determined by the logic of the clock frequency dividing circuit formed in the circuit can be specified, and the number of idle rotations cannot be dynamically specified. In addition, the number of idle rotations (here, the idle rotation means that the shift clock to the RPG and the shift clock to the flip-flop constituting the shift register are different from each other,
As the setting of (the signal input from the G register to the flip-flop is thinned out) increases, the scale of the clock frequency dividing circuit and the number of control signals increase, so that the circuit overhead increases.

FIG. 12 shows a second embodiment. LSI to be inspected
An RPG 1201, a MISR 1202, a clock control circuit 1203, and a circuit under test 1204 are configured. The pseudo random number pattern generated in the RPG 1201 is scanned through a scan chain 1205 into a plurality of shift registers formed by connecting a plurality of flip-flops in the circuit under test 1204 to execute a test. Scan out from each flip-flop through scan chain 1206
The data is compressed and stored in 1202. In this embodiment, the diagnosis control signal 1208 partially cuts off the RPG clock, thereby
Only G is idled to eliminate the correlation between flip-flops.

A control circuit for cutting off clock signals other than the shift clock input to the RPG will be described with reference to FIG. MISR 1303, internal flip-flop 1304
The AND element 1301 is connected to the clock signal line to be input to. An output pin of the AND element 1301 to which the clock signal line is connected is input as a clock signal of each MISR 1303 and the internal flip-flop 1304. RPG130
The control signal 1302 is connected to the AND element 1301 in order to cut off the clock signal to the MISR 1303 and the internal flip-flop 1304 when the idle rotation of No. 5 is performed. Control signal 1
302 is set to 1 during the normal shift scan operation,
When the RPG 1305 is idle, 0 is set. By setting 0, the clock signal input to the MISR 1303 and the internal flip-flop 1304 is cut off,
The shift operation of the SR 1303 and the internal flip-flop 1304 can be stopped. Therefore, the data is shifted by the RPG 1305, and the data of the MISR 1303 and the internal flip-flop 1304 is held as it is. FIG. 14 shows a time chart of a clock signal input to the RPG 1305, the MISR 1303, and the internal flip-flop 1304 when a test pattern is input.

FIG. 14A shows an input test pattern when RPG idle rotation is not performed. As in the first embodiment, an input pattern is scanned into each flip-flop while a pseudo random number pattern is sequentially shifted without performing idle rotation of an RPG, and a test is executed by inputting a system clock.
In this case as well, as in FIG.
Correlations occur in flip-flops 813, 822, 831 to which a pattern is input from the register of the PG.
Therefore, the hypothetical fault 911 shown in FIG. 9 cannot be detected.

Next, a test pattern is input to each flip-flop at the clock timing shown in the time chart (2). The time chart (2) is a time chart in the single idle rotation mode of the RPG. The time chart of (2) will be described. One pseudo random number is generated by the RPG 1305, and the idle control pin 1302 is set to 0 each time the register of the RPG 1305 is shifted once. By setting the idle control pin 1302 to 0, only the shift clock of the RPG 1305 is input, and the shift clocks of the MISR 1303 and the internal flip-flop 1304 are cut off.
Keep the data that is being scanned in. Further, when one pseudo random number is generated, the idle control pin 1
302 is set to 1. By setting the idle control pin 1302 to 1, the shift clock of the MISR 1303 and the internal flip-flop 1304 is also input, and the shift operation is performed. By repeating this operation, the number of shifts of the RPG 1305 becomes the MISR 1303 and the internal flip-flop 1
This is twice the number of shifts of 304. The state transition of the internal flip-flop at this time is the same as the clock timing of the half cycle of the first embodiment, and is shown in FIG. In this process, the correlation generated in the test pattern input in (1) is resolved, and the hypothetical fault 911 shown in FIG.
Can be detected.

In (3), a test pattern of two idle turns is described. The above processing is repeated an appropriate number of times while changing the clock timing, so that the failure detection rate can be improved. Further, in this embodiment, the logic for the number of times of idling is not incorporated in the logic circuit from the beginning, and the number of times of idling can be dynamically set for an infinite number of times by an input signal.

FIG. 15 shows a third embodiment. In the RPG idling control methods of the first and second embodiments, the idling control is always performed by externally applying a control signal (control signals 501 and 502 in FIG. 5 and control signal 1302 in FIG. 13). Embodiment 3 is an embodiment in which the correlation between flip-flops is eliminated without using a control signal. This will be described with reference to FIG. As in the second embodiment, the RPG 150
1, a MISR 1502, a clock control circuit 1503, and a circuit under test 1504. RPG15
Scan chain 15
05, a test pattern is scanned into a plurality of shift registers formed by connecting a plurality of flip-flops in the circuit under test 1504 to execute a test, and a test result is transmitted from each flip-flop to the scan chain 15.
06 and scans out the data in the MISR 1502. In the second embodiment, the normal / idling control is performed by the idling control signal from the outside.
The correlation is canceled by inputting the pseudo random number pattern generated by the PG 1501 to the AND element 1602.

The control circuit will be described with reference to FIG. RP
If 1 is generated by the pseudo random number generated in G1602, the data of each RPG 1602, MISR 1604, and internal flip-flop 1603 are shift-scanned. If 0 is generated by the pseudo random number, the shift clock signal is input by RPG 1602 to shift the data, and the MISR 16
04, since the shift clock signal is cut off by the flip-flop 1603, the data is not shifted and scanned,
Keep the entered data as it is.

FIG. 17 shows an input example of a pseudo random number pattern in the third embodiment. In this case, the first bit data of the LFSR of the RPG is used as a signal for switching the RPG idle mode. (1) is a state in which an initial pattern is input to the RPG. In this state, data is set only in the RPG, and 0 is set in each flip-flop. It is assumed that the test is started from this state. (2)
Fig. 5 shows an example of pattern setting when generating the first pseudo random number pattern.
In (1), since the first bit of the RPG is 1, the shift clock of the MISR and each flip-flop is input. Therefore, the test pattern stored in the generated RPG is scanned into each flip-flop. (3) shows a pattern setting example when the second pseudo random number pattern is generated. RP
The data in G is shifted by one bit because the shift clock is input, but the pseudo random number pattern (R
Since the first bit of the PG is 0, the MISR and the system clock of each flip-flop are cut off, and the data in the flip-flop is held without being shifted. This process is repeated six times in the state (6). In (6), it can be seen that the correlation generated by the shift scan described above does not occur. By continuing this process and applying a large amount of test patterns, a sufficient failure detection rate can be obtained. In this method, a pseudo-random number pattern is generated from a normal RPG, and the correlation between flip-flops generated when a test pattern is applied to flip-flops by shift scan can be eliminated. Further, since the control pin is not used for selecting the normal clock / RPG idle rotation process and no control pattern is required, the input test pattern can be simplified.

[0028]

According to the present invention, when diagnosing an LSI to be inspected having a BIST (built-in self-test), a plurality of shift registers constituted by connecting a plurality of internal flip-flops to a test pattern by a shift scan operation. By eliminating the correlation between flip-flops generated when a test pattern is applied by scan-in / scan-out, more failures can be detected and the failure detection rate can be improved. Further, since the form of the correlation can be changed for each pattern group or in any case, the correlation can be externally operated to improve the failure detection rate. Further, the number of times of changing the correlation can be unlimited.
Furthermore, since the control circuit for canceling the correlation can be realized by a small-scale and simple circuit, there is an effect that the circuit overhead can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an LSI used in a first embodiment.

FIG. 2 is a diagram illustrating an example of an internal circuit of an RPG.

FIG. 3 is a diagram illustrating an example of an internal circuit of a MISR.

FIG. 4 is a diagram showing the concept of BIST (Built-in Self Test).

FIG. 5 is a diagram illustrating an internal configuration of a clock frequency dividing circuit used in the first embodiment.

6 is a diagram showing a time chart of a clock of the clock frequency dividing circuit of FIG. 5;

FIG. 7 is a diagram showing a clock timing assignment table of the clock frequency dividing circuit of FIG. 5;

FIG. 8 is a diagram showing a state transition diagram of the scan-in data of the RPG and the flip-flop when the same shift clock is applied to the RPG, the MISR and the circuit under test.

FIG. 9 is a diagram showing a schematic internal configuration of a circuit under test.

FIG. 10 is a diagram showing a state transition diagram of a 1/2 clock mode used in the first embodiment.

FIG. 11 is a diagram showing a state transition diagram of a ク ロ ッ ク clock mode used in the first embodiment.

FIG. 12 is a diagram illustrating a configuration of an LSI used in a second embodiment.

FIG. 13 is a diagram illustrating an internal configuration of a clock control circuit used in the second embodiment.

FIG. 14 is a time chart of a clock control circuit clock used in the second embodiment.

FIG. 15 is a diagram illustrating a configuration of an LSI used in a third embodiment.

FIG. 16 is a diagram illustrating an internal configuration of a clock control circuit used in a third embodiment.

FIG. 17 is a diagram showing a state transition diagram of an RPG and a flip-flop used in the third embodiment.

FIG. 18 is a diagram showing a configuration of a conventionally used LSI.

[Explanation of symbols]

101, 1201, 1305, 1501, 1602 R
PG 102, 1202, 1303, 1502, 1604 M
ISR 103 Clock frequency dividing circuit 104, 1204, 1504 Circuit under test 105, 106, 871-876, 1205, 120
6, 1505, 1506 scan chains 107, 503, 504, 1207, 1507, 160
6 RPG clock signal 108, 505, 1209, 1509, 1607 MI
Clock signal for SR / internal flip-flop 109, 501, 502, 1208, 1302, 150
8, 1605 Clock control signal 401 Pattern generator 402 Circuit under test 403 Code compressor 511 to 513 Frequency-divided clock signal 521 to 523 Frequency-dividing flip-flop 801, 802, 803, 804, 805, 806 R
Registers in PG 811-816, 821-826, 831-836, 8
41 to 846, 851 to 856, 861 to 866 Flip-flop 901 to 903 EOR element 904, 1301, 1601 AND element 911 to 916 Assumed fault 1203, 1503 Clock control circuit 1304, 1603 Internal flip-flop

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03K 19/00 H01L 27/04 T

Claims (4)

[Claims] 1. A circuit to be inspected, a plurality of shift registers formed by connecting a plurality of flip-flops, a random number pattern generator and a code compressor constituted by a linear feedback shift register are incorporated. An input side of the shift register is connected to a register at a predetermined bit position of the random number pattern generator, and an output side of each shift register is connected to a register at a predetermined bit position of the code compressor, respectively. A shift clock is applied to the code compressor and the plurality of shift registers. Outputs of the flip-flops of the plurality of shift registers are input to the circuit to be inspected. In a logic integrated circuit configured to be output to each flip-flop of the shift register, A clock control circuit for inputting the shift clock, generating a shift clock having a different pattern from the shift clock, and supplying the generated shift clock to the code compressor and the plurality of shift registers. Logic integrated circuit. 2. The logic integrated circuit according to claim 1, wherein the clock control circuit is a frequency dividing circuit that generates a shift clock having a different cycle according to a control signal supplied from the outside. circuit. 3. The logic integrated circuit according to claim 1, wherein said clock control circuit generates shift clocks of different patterns according to an externally applied control signal. 4. The logic integrated circuit according to claim 2, wherein an output signal from a register at a specific bit position of the random number pattern generator is used as the externally applied control signal. .