JP2004303809A - Capacitor, storage device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor wherein deterioration due to an inprint phenomenon is extremely hard to be caused. <P>SOLUTION: The capacitor is provided with a lower electrode 160 kept in a state of electrically floating, a ferroelectric layer 170 arranged on the lower electrode 160, an upper electrode 180 which is arranged opposite to the prescribed surface of the lower electrode 160 interposing the ferroelectric layer 170 and constitutes an auxiliary capacitor AC together with the lower electrode 160 and the first ferroelectric layer 170, and a second upper electrode 180 which is arranged opposite to the prescribed surface of the lower electrode 160 interposing the ferroelectric layer 170 and constitutes a memory capacitor MC together with the lower electrode 160 and the ferroelectric layer 170. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a capacitor having a ferroelectric layer, a memory device, and an electronic device.
[0002]
[Background technology]
2. Description of the Related Art As a conventional ferroelectric capacitor, there is a capacitor disclosed in Japanese Patent Application Laid-Open No. 2002-34391. Patent Document 1 discloses that a ferroelectric thin film having a uniform titanium element concentration is formed by forming a film so that the concentration of the titanium element contained in the ferroelectric thin film has a gradient and performing heat treatment after the film formation. A ferroelectric capacitor is disclosed.
[0003]
[Patent Document 1]
JP, 2002-343793, A [Problems to be solved by the invention]
However, in the conventional ferroelectric capacitor disclosed in the above-mentioned patent document, it is extremely difficult to control the concentration of the titanium element in the ferroelectric thin film to be uniform, so that a ferroelectric capacitor having good hysteresis characteristics is required. It was difficult to obtain.
[0004]
Therefore, an object of the present invention is to provide a capacitor, a memory device, and an electronic device that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous embodiments of the present invention.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, according to a first aspect of the present invention, a lower electrode having a first surface and kept in an electrically floating state and a first region on the first surface include: A first ferroelectric layer provided on the lower electrode, a second ferroelectric layer provided on the lower electrode in a second region on the first surface, and a first ferroelectric layer The first ferroelectric layer and the first upper electrode forming the first capacitor are provided to face the first region with the first ferroelectric layer interposed therebetween. And a second ferroelectric layer and a second upper electrode constituting a second capacitor. This makes it possible to provide a highly reliable capacitor that has very little influence of the internal electric field.
[0006]
Further, the first ferroelectric layer and the second ferroelectric layer may be provided integrally. Thus, damage to the ferroelectric layer can be prevented, and a capacitor with good characteristics can be provided.
[0007]
According to a second aspect of the present invention, there is provided a memory device comprising the above-mentioned capacitor. The memory device includes a ferroelectric memory including the capacitor, an embedded device including the capacitor and a logic circuit, and a semiconductor device including the capacitor.
[0008]
In addition, the memory device preferably further includes a data control unit that writes data to the second capacitor by providing a potential difference between the first upper electrode and the second upper electrode. Thus, the influence of the imprint phenomenon can be reduced, so that a malfunction of the memory device can be prevented.
[0009]
Further, in the memory device, in a third region on the first surface, the third ferroelectric layer provided on the lower electrode is opposed to the third region with the third ferroelectric layer interposed therebetween. And a lower electrode, a third ferroelectric layer, and a third upper electrode forming a third capacitor, wherein the data control unit includes a first upper electrode, a third upper electrode, Data may be written to the third capacitor by providing a potential difference therebetween. As a result, the influence of the imprint phenomenon can be reduced and the size of the memory device can be reduced.
[0010]
Further, the first capacitor may have a different capacity from the second capacitor and the third capacitor. Thus, the number of other capacitors corresponding to the first capacitor can be increased, so that the size of the memory device can be further reduced.
[0011]
According to the third aspect of the present invention, a lower electrode having a first surface, a first ferroelectric layer provided on the lower electrode in a first region on the first surface, A second ferroelectric layer provided on the lower electrode and a second ferroelectric layer provided on the lower electrode, the second ferroelectric layer being provided so as to face the first region with the first ferroelectric layer interposed therebetween; A first upper electrode forming a first ferroelectric layer and a first capacitor; and a lower electrode and a first ferroelectric layer provided opposite to a second region with the second ferroelectric layer interposed therebetween. A second upper electrode forming the body layer and the second capacitor, and a data controller for writing data to the second capacitor by providing a potential difference between the first upper electrode and the second upper electrode. A memory device comprising: Thus, the influence of the imprint phenomenon can be reduced, so that a malfunction of the memory device can be prevented.
[0012]
According to a fourth aspect of the present invention, there is provided an electronic apparatus including the above memory device. The electronic device includes a personal computer, a game machine, a portable information terminal, a portable communication device, an IC card, and other devices provided with the above memory device.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described through embodiments of the present invention with reference to the drawings, but the following embodiments do not limit the invention according to the claims and are described in the embodiments. Not all combinations of features are essential to the solution of the invention.
[0014]
FIG. 1 is a diagram illustrating an example of a circuit configuration of a memory device 100 according to the first embodiment of the present invention. In this example, a ferroelectric memory having a cross-point type memory cell structure will be described as an example of a memory device.
[0015]
The memory device 100 includes a memory cell array 110 having a plurality of memory cells 140, a word line control unit 120 which is an example of a data control unit for writing data to the memory cells 140, or reading data written to the memory cells 140, and a bit line. And a line control unit 130. The memory cell 140 has a memory capacitor MC and an auxiliary capacitor AC. The memory capacitor and the auxiliary capacitor included in the memory cell 140 controlled by the n-th (n is a positive integer) word line WLn and the m-th (m is a positive integer) bit line BLn are stored in the memory capacitor MCnm and the auxiliary capacitor, respectively. AC nm.
[0016]
The word line control unit 120 is electrically connected to the upper electrode 180 (see FIG. 2) of the memory capacitor MC via the word line WL. In addition, the bit line control unit 130 is electrically connected to the upper electrode 180 (see FIG. 2) of the auxiliary capacitor AC via the bit line BL. Then, the n-th word line WLn is selected by the word line control unit 120 and the m-th bit line BLm is selected by the bit line control unit 130, so that the memory cells 140 corresponding to the word line WLn and the bit line BLm are stored. Data is written to the included memory capacitor MCnm, or data written to the memory capacitor MCnm is read.
[0017]
FIG. 2 is a diagram illustrating an example of the structure of the memory cell array 110 in the memory device 100 according to the first embodiment. FIG. 2A is a top view of the memory cell array 110. FIG. FIGS. 2B and 2C are a sectional view taken along the line AA 'and a sectional view taken along the line BB' in FIG. 2A, respectively.
[0018]
The memory cell array 110 includes a base 150, a lower electrode 160, a ferroelectric layer 170, an upper electrode 180 having a first metal layer 182 and a second metal layer 184, and an insulating layer 190. Is done. Further, the memory cell array 110 includes a plurality of word lines WL and a plurality of bit lines BL substantially orthogonal to the plurality of word lines WL and formed of the second metal layer 184. The plurality of word lines WL are electrically connected to the upper electrode 180 of the auxiliary capacitor AC, and the plurality of bit lines BL are electrically connected to the upper electrode 180 of the memory capacitor MC.
[0019]
The base 150 is, for example, a substrate made of an inorganic material such as a metal or a semiconductor or an organic material such as a polyimide, or a transistor, a capacitor, an element such as a diode, a conductive layer such as a wiring and an electrode, a gate insulating film, It includes those in which a dielectric layer such as an interlayer insulating film and a capacitor dielectric film is formed. In this example, the word line control unit 120 and the bit line control unit 130 (see FIG. 1) are provided on the base 150, and the base 150 electrically connects with the memory cell array 110 via the word lines WL and the bit lines BL. Connected.
[0020]
The lower electrode 160 is shared by the memory capacitor MC and the auxiliary capacitor AC. That is, one lower electrode 160 and a predetermined upper electrode 180 provided opposite to the lower electrode 160 constitute a memory capacitor MC. And the upper electrode 180 constitute an auxiliary capacitor AC. Further, in this example, the lower electrode 160 is shared by the plurality of memory cells 140. That is, the lower electrode 160 is shared by the plurality of memory capacitors MC and the plurality of auxiliary capacitors AC. Specifically, the memory cell array 110 may be configured to include one lower electrode 160 and a plurality of upper electrodes 180 provided to face a predetermined surface of the lower electrode 160. Further, the memory cell array 110 may be configured to have one lower electrode 160 for a plurality of upper electrodes 180 provided below a predetermined word line WL or bit line BL.
[0021]
In addition, it is desirable that the lower electrode 160 be kept electrically floating. The electrically floating state refers to a case where the lower electrode 160 is not electrically connected to a conductive member capable of supplying power to the lower electrode 160 or a state where power is supplied to the lower electrode 160 from the lower electrode 160. This includes the case where there is a means for electrically separating the conductive member from the conductive member. Specifically, it is desirable that the lower electrode 160 be kept electrically floating between the operation of writing data to the memory capacitor MC and the operation of reading data stored in the memory capacitor MC. In this example, the lower electrode 160 is not connected to any of the bit line BL and the word line WL.
[0022]
The ferroelectric layer 170 is formed between the lower electrode 160 and the upper electrode 180 using, for example, a mixed crystal material (PZT) of lead titanate (PbTiO3) and lead zirconate (ZrTiO3). In this example, the ferroelectric layer 170 is provided over the plurality of memory capacitors MC and the auxiliary capacitors AC, but may be provided separately on each of the plurality of memory capacitors MC and the auxiliary capacitors AC. In this case, the ferroelectric layer 170 is preferably formed by etching using the upper electrode 180 as a mask. Further, the ferroelectric layer 170 may be etched using a mask for etching the upper electrode 180. Further, the ferroelectric layer 170 may be provided individually for each memory cell 140 instead of for each memory capacitor MC and auxiliary capacitor AC.
[0023]
The upper electrode 180 is provided to face a predetermined region of the lower electrode 160 with the ferroelectric layer 170 interposed therebetween. The lower electrode 160, the ferroelectric layer 170, and the upper electrode 180 provided in the predetermined region form a memory capacitor MC, and the lower electrode 160, the ferroelectric layer 170, and a memory capacitor MC different from the predetermined region. Auxiliary capacitor AC is constituted by upper electrode 180 provided in the region. Here, the predetermined region and the other region are non-overlapping regions on the surface of the lower electrode 160 where the ferroelectric layer 170 is provided.
[0024]
The upper electrode 180 includes a first metal layer 182 and a second metal layer 184. The second metal layer 184 is provided so as to configure the upper electrode of the memory capacitor MC and also configure the bit line BL in the memory capacitor MC. In the auxiliary capacitor AC, the second metal layer 184 is electrically connected to the word line WL.
[0025]
The operation of the memory device 100 will be described with reference to FIGS. Hereinafter, an operation of writing data to the memory capacitor MC11 using the auxiliary capacitor AC11 and an operation of reading data written to the memory capacitor MC11 will be described as examples.
[0026]
When writing data “1” to the memory capacitor MC11, the potential of the bit line BL1 is set to V, and the potential of the word line WL1 is set to zero. At this time, the non-selected memory cell 140 is set to a predetermined potential so that data written to the non-selected memory capacitor MC is not erased. For example, the potentials of the word lines WL2 and WL3 are set to V × １ ／, and the potentials of the bit lines BL2 and BL3 are set to V × ２. Thereby, the potential difference between the upper electrode 180 of the memory capacitor MC11 and the upper electrode 180 of the auxiliary capacitor AC11 becomes V, while the potential difference between the upper electrode 180 of the non-selected memory capacitor MC and the upper electrode of the non-selected auxiliary capacitor AC becomes V. Since it is × １ ／ or V × ２, data “1” can be written only to the memory capacitor MC11.
[0027]
When writing data “0” to the memory capacitor MC11, the potential of the bit line BL1 is set to zero and the potential of the word line WL11 is set to V, contrary to the above. Then, for example, by setting the potential of the word lines WL2 and WL3 to V × ２ and the potential of the bit lines BL2 and BL3 to V × １ ／, data “0” can be written only to the memory capacitor MC11. it can.
[0028]
When reading the data written in the memory capacitor MC11, the potential of the word line WL1 is set to V and the sense amplifier (shown in FIG. The data written in the memory capacitor MC11 is read out by reading the potential of the bit line BL1 in FIG. At the same time, the potentials of the word lines WL2 and WL3 are set to V × ２, and the potentials of the bit lines BL2 and BL3 are set to V × １ ／ so that the data written in the non-selected memory capacitor MC is not erased.
[0029]
According to the present embodiment, the auxiliary capacitor AC sharing the lower electrode 160 kept electrically floating with the memory capacitor MC is provided, and the upper electrode 180 of the memory capacitor MC and the upper electrode 180 of the auxiliary capacitor AC are connected. By providing a potential difference therebetween, the internal electric field of the ferroelectric layer 170 can be reduced. Accordingly, the imprint phenomenon of the memory device 100 can be reduced, so that the highly reliable memory device 100 can be provided.
[0030]
Further, according to the present embodiment, the memory cell 140 having the memory capacitor MC and the auxiliary capacitor AC described above is applied to the cross-point type memory device 100, whereby the structure and the manufacturing process are simplified, and the memory cell array 110 is A small memory device 100 can be provided.
[0031]
FIG. 3 is a diagram illustrating an example of a circuit configuration of the memory device 100 according to the second embodiment of the present invention. In the present embodiment, the auxiliary capacitor AC is used for data write and data read operations of the plurality of memory capacitors MC. Hereinafter, a ferroelectric memory having a cross-point type memory cell structure will be described as an example of a memory device. Note that the components denoted by the same reference numerals as those described in the first embodiment may have the same structures and functions as those described in the first embodiment.
[0032]
In the present embodiment, the memory device 100 includes a memory cell array 110 having a plurality of auxiliary capacitors AC and a memory capacitor MC, and a data control unit that writes data to the memory capacitor MC and / or reads data written to the memory capacitor MC. The configuration includes a word line control unit 120 and a bit line control unit 130, which are examples. The memory cell array 110 is configured such that a plurality of memory capacitors MC correspond to a predetermined auxiliary capacitor AC among the plurality of auxiliary capacitors AC.
[0033]
The word line control unit 120 is electrically connected to the upper electrode 180 of the auxiliary capacitor ACn via the word line WLn. Further, the bit line control unit 130 is electrically connected to the upper electrode 180 of the memory capacitor MCnm via the bit line BLm. That is, in this example, the word line WL is electrically connected to one auxiliary capacitor AC, and the bit line BL is electrically connected to a plurality of memory capacitors MC. Then, data is written to the memory capacitor MCnm by providing a potential difference between the word line WLn selected by the word line control unit 120 and the bit line BLm selected by the bit line control unit 130.
[0034]
That is, by providing a potential difference between the upper electrode of the auxiliary capacitor AC and the upper electrode 180 of the memory capacitor MC selected from the plurality of memory capacitors MC sharing the lower electrode 160 with the auxiliary capacitor AC. Write data to the memory capacitor MC. At this time, data may be simultaneously written to the plurality of memory capacitors MC by selecting a plurality of memory capacitors MC provided corresponding to the auxiliary capacitor AC.
[0035]
FIG. 4 is a diagram illustrating an example of the structure of the memory cell array 110 in the memory device 100 according to the second embodiment. FIG. 4A is a diagram illustrating an upper surface of the memory cell array 110. FIG. FIG. 4B is a diagram illustrating a cross section taken along the line AA ′ in FIG. 4A, and FIG. 4C is a diagram illustrating another example of the structure of the memory cell array 110.
[0036]
The memory cell array 110 includes a base 150, a lower electrode 160, a ferroelectric layer 170, an upper electrode 180 having a first metal layer 182 and a second metal layer 184, and an insulating layer 190. You. Further, the memory cell array 110 includes a plurality of word lines WL and a plurality of bit lines BL substantially orthogonal to the lower electrode 160 of the memory capacitor MC corresponding to each word line WL and formed of the second metal layer 184. Have. In this example, the auxiliary capacitor AC is provided on the outer periphery of the memory capacitor MC in the memory cell array 110. Further, in the example described in the first embodiment, the auxiliary capacitors AC and the memory capacitors MC are provided alternately corresponding to the predetermined word lines WL, but in the present example, the auxiliary capacitors AC and the memory capacitors MC correspond to the predetermined word lines WL. Thus, a plurality of memory capacitors MC are continuously provided for one auxiliary capacitor AC.
[0037]
The auxiliary capacitor AC may have a capacity different from that of the memory capacitor MC. For example, as shown in FIG. 4C, the upper electrode 180 in the auxiliary capacitor AC may have a different area from the upper electrode 180 in the memory capacitor MC. In this case, it is desirable that the area of the upper electrode 180 in the auxiliary capacitor AC is larger than the area of the upper electrode 180 in the memory capacitor MC. That is, it is desirable that the capacity of the auxiliary capacitor AC is configured to be larger than the capacity of the memory capacitor MC.
[0038]
The operation of the memory device 100 will be described with reference to FIGS. Hereinafter, an operation of writing data to the memory capacitor MC11 using the auxiliary capacitor AC1 and an operation of reading data written to the memory capacitor MC11 will be described as examples.
[0039]
When writing data “1” to the memory capacitor MC11, the potential of the bit line BL1 is set to V, and the potential of the word line WL1 is set to zero. At this time, the non-selected memory cell 140 is set to a predetermined potential so that data written to the non-selected memory capacitor MC is not erased. For example, the potentials of the word lines WL2 and WL3 are set to V × １ ／, and the potentials of the bit lines BL2 and BL3 are set to V × ２. As a result, the potential difference between the upper electrode 180 of the memory capacitor MC11 and the upper electrode 180 of the auxiliary capacitor AC1 becomes V, while the potential difference between the upper electrode 180 of the unselected memory capacitor MC and the upper electrode of the auxiliary capacitor AC1 becomes V × 1. / 3 or V × 2/3, so that data “1” can be written only to the memory capacitor MC11.
[0040]
When writing data “0” to the memory capacitor MC11, the potential of the bit line BL1 is set to zero and the potential of the word line WL11 is set to V, contrary to the above. Then, for example, by setting the potential of the word lines WL2 and WL3 to V × ２ and the potential of the bit lines BL2 and BL3 to V × １ ／, data “0” can be written only to the memory capacitor MC11. it can.
[0041]
When reading the data written in the memory capacitor MC11, the potential of the word line WL1 is set to V and the sense amplifier (shown in FIG. The data written in the memory capacitor MC11 is read out by reading the potential of the bit line BL1 in FIG. At the same time, the potentials of the word lines WL2 and WL3 are set to V × ２, and the potentials of the bit lines BL2 and BL3 are set to V × １ ／ so that the data written in the non-selected memory capacitor MC is not erased.
[0042]
FIG. 5 is a diagram comparing the shift amounts of the hysteresis curves of the conventional capacitor and the capacitors according to the first and second embodiments. Specifically, a conventional capacitor is a capacitor in which one upper electrode and one lower electrode are provided to face each other. The capacitor according to the present embodiment includes, as an example, a capacitor having the same capacitor area as a conventional capacitor and configured so that the area ratio between the memory capacitor and the auxiliary capacitor is 1: 1. And an auxiliary capacitor having an area ratio of 1:14. Further, in the conventional capacitor and the capacitor according to the present embodiment, the ferroelectric layers have the same material and the same thickness.
[0043]
The conventional capacitor has a plus-side coercive electric field (applied voltage when the amount of polarization becomes zero) of +1.45 V (volt) and a minus-side coercive electric field of -1.15 V. The shift amount of the hysteresis curve is as follows. It is as large as 0.125V. On the other hand, in the capacitor according to the present embodiment in which the area ratio is 1: 1, the coercive electric field on the positive side is +1.29 V, the coercive electric field on the negative side is −1.20 V, and the shift amount of the hysteresis curve is 0.045 V. It has become. This is an extremely low value as compared with the conventional capacitor. According to the capacitor of the present embodiment, the influence of the internal electric field is extremely small, and the influence of the imprint phenomenon can be greatly reduced. As a result, malfunction of the memory device due to deterioration of the hysteresis characteristic can be prevented.
[0044]
In the capacitor according to the present embodiment in which the area ratio is 1:14, the coercive electric field on the positive side is +1.28 V, the coercive electric field on the negative side is −1.15 V, and the shift amount is 0.065 V. Even when the area ratio is set to 1:14, the influence of the internal electric field can be greatly reduced as compared with the conventional capacitor, although most of the applied voltage is applied to the memory capacitor having a small area. .
[0045]
FIG. 6 is a perspective view showing a configuration of a personal computer 1000 which is an example of an electronic apparatus including the memory device of the present invention. 6, a personal computer 1000 includes a display panel 1002 and a main body 1006 having a keyboard 1004. The memory device of the present invention is used in a built-in board or the like of the main body 1006 of the personal computer 1000.
[0046]
The examples and application examples described through the above embodiments of the present invention can be used in appropriate combination or with modifications or improvements depending on applications. The present invention is limited to the description of the above embodiments. Not something. It is apparent from the description of the appended claims that embodiments in which such combinations or changes or improvements are made can be included in the technical scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of a circuit configuration of a memory device 100 according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a structure of a memory cell array 110 in the memory device 100 according to the first embodiment.
FIG. 3 is a diagram illustrating an example of a circuit configuration of a memory device 100 according to a second embodiment of the present invention.
FIG. 4 is a diagram illustrating an example of a structure of a memory cell array 110 in a memory device 100 according to a second embodiment.
FIG. 5 is a diagram comparing shift amounts of hysteresis curves between a conventional capacitor and the capacitors according to the first and second embodiments.
FIG. 6 is a perspective view illustrating a configuration of a personal computer 1000 which is an example of an electronic apparatus including the memory device of the present invention.
[Explanation of symbols]
100 memory device, 110 memory cell array, 120 word line control unit, 130 bit line control unit, 140 memory cell, 150 base, 160 bottom Electrodes, 170: ferroelectric layer, 180: upper electrode, 182: first metal layer, 184: second metal layer, 190: insulating layer, 1000: personal Computer, 1002: display panel, 1004: keyboard, 1006: main unit, AC: auxiliary capacitor, BL: bit line, MC: memory capacitor, WL: word line

Claims (8)

A lower electrode having a first surface and maintained electrically floating;
A first ferroelectric layer provided on the lower electrode in a first region on the first surface;
A second ferroelectric layer provided on the lower electrode in a second region on the first surface;
A first upper electrode that is provided to face the first region with the first ferroelectric layer interposed therebetween, and that forms a first capacitor with the lower electrode and the first ferroelectric layer;
The lower electrode, the second ferroelectric layer, and a second upper electrode constituting a second capacitor are provided so as to face the second region with the second ferroelectric layer interposed therebetween. A capacitor comprising: a capacitor; The capacitor according to claim 1, wherein the first ferroelectric layer and the second ferroelectric layer are provided integrally. A memory device comprising the capacitor according to claim 1. 4. The data control unit according to claim 3, further comprising a data control unit that writes data to the second capacitor by providing a potential difference between the first upper electrode and the second upper electrode. Memory device. A third ferroelectric layer provided on the lower electrode in a third region on the first surface;
The lower electrode, the third ferroelectric layer, and a third upper electrode forming a third capacitor are provided so as to face the third region with the third ferroelectric layer interposed therebetween. In addition,
The memory according to claim 4, wherein the data control unit writes data to the third capacitor by providing a potential difference between the first upper electrode and the third upper electrode. apparatus. The memory device according to claim 5, wherein the first capacitor has a different capacity from the second capacitor and the third capacitor. A lower electrode having a first surface;
A first ferroelectric layer provided on the lower electrode in a first region on the first surface;
A second ferroelectric layer provided on the lower electrode in a second region on the first surface;
A first upper electrode that is provided to face the first region with the first ferroelectric layer interposed therebetween, and that forms a first capacitor with the lower electrode and the first ferroelectric layer;
A second upper electrode that is provided to face the second region with the second ferroelectric layer interposed therebetween, and that forms a second capacitor with the lower electrode and the first ferroelectric layer;
A memory device comprising: a data control unit that writes data to the second capacitor by providing a potential difference between the first upper electrode and the second upper electrode. An electronic apparatus comprising the memory device according to claim 3.

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