CN100466296C - Variable capacitor - Google Patents
Variable capacitor Download PDFInfo
- Publication number
- CN100466296C CN100466296C CNB2006100715226A CN200610071522A CN100466296C CN 100466296 C CN100466296 C CN 100466296C CN B2006100715226 A CNB2006100715226 A CN B2006100715226A CN 200610071522 A CN200610071522 A CN 200610071522A CN 100466296 C CN100466296 C CN 100466296C
- Authority
- CN
- China
- Prior art keywords
- those
- variable capacitor
- electrode
- top electrode
- doped regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
A variable capacitor is prepared as setting multiple doped region being arranged as an array at substrate on bottom electrode, setting top electrode above substrate and arranging multiple electrode position and multiple opening on said top electrode, setting the first dielectric layer between top electrode and said substrate, setting conductor layer above said top electrode and electric-connecting said conductor layer to said doped regions through said opening but electric-isolating said conductor layer to said top electrode.
Description
Technical field
The present invention relates to a kind of semiconductor structure, relate in particular to a kind of variable capacitor structure.
Background technology
In typical communication system, the information signal (for example: TV programme) can be by modulation (Tune), and be placed on the carrier wave of high frequency to make things convenient for the transmission of signal.Have the characteristic of different carrier signal through different frequency, simultaneously many information signals are blazed abroad.Therefore, and the receiver need working voltage control generator in the communication system (Voltage Controlled Oscillator, VCO), so that the information signal is separated from carrier wave.In VCO, include LC (inductance capacitance) circuit of forming by variable capacitor and inductance.By the characteristic that its electric capacity of variable capacitor changes along with voltage modulation, can be so that the frequency of oscillation of VCO changes thereupon.
Common variable capacitor comprises with metal oxide semiconductor transistor (Metal-OxideSemiconductor Transistor, MOS) structure is main MOS variable capacitor, and with p type doped region and the interconnected eliminant that forms of n type doped region (Junction) variable capacitor.Wherein, though its electric capacity of MOS variable capacitor has the characteristics of big modulation scope ((maximum capacitor-minimum capacity)/minimum capacity), yet, its capacitance is the gross area ratio that depends on the bottom electrode (being the source/drain regions of MOS variable capacitor) in the substrate of top electrode (being the grid of MOS variable capacitor) and top electrode both sides, and just the specific capacitance amount is to be proportional to the ratio of top electrode area than the bottom electrode area of both sides.Therefore how can increase the top electrode area than the ratio of the upper/lower electrode gross area to improve the specific capacitance amount, become the important topic of current variable capacitor development.
Summary of the invention
The purpose of this invention is to provide a kind of variable capacitor, can increase specific capacitance amount and the quality factor that improves variable capacitor.
The present invention proposes a kind of variable capacitor and is positioned on the substrate, and this variable capacitor comprises a bottom electrode, a top electrode, one first dielectric layer and a conductor layer.Wherein, bottom electrode has and is arranged in a plurality of doped regions that this substrate is arranged in an array, and this array has multirow and multiple row, and the doped regions of adjacent two row are alternately arranged.Top electrode then is positioned at substrate top, and top electrode is made of a plurality of electrode position, and top electrode has a plurality of openings, and each opening exposes corresponding doped region, and wherein each electrode position is directly by three doped regions encirclements.First dielectric layer is between substrate and top electrode.Conductor layer is positioned at this top electrode top, and wherein conductor layer and top electrode electrical isolation and conductor layer and doped region are via opening and doped region electrically connect.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein each electrode position is a polygonal body, and three doped regions that surround electrode position then are positioned at the corner position of this polygonal body.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein polygonal body is a regular polygon body.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein each opening is shaped as a quadrangle.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein each opening is shaped as a circle.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein the material of top electrode comprises doped polycrystalline silicon.
According to the described variable capacitor of the preferred embodiments of the present invention, one second dielectric layer is wherein arranged between top electrode and the conductor layer, second dielectric layer is inserted in the opening, and second dielectric layer has one of exposed doped region of a contact window in each opening.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein the area of each electrode position than the ratio of the gross area of the doped region of last this electrode position of encirclement more than or equal to 1/3.
The present invention provides a kind of variable capacitor to be positioned on the substrate again, and this variable capacitor comprises a bottom electrode, a top electrode, one first dielectric layer, a conductor layer.Wherein, bottom electrode has a plurality of doped regions that are arranged in this substrate.Top electrode then is positioned at substrate top, and top electrode is made of a plurality of electrode position, and wherein the shape of each electrode position is defined by at least five openings, and each opening exposes corresponding doped region.First dielectric layer is between substrate and top electrode.Conductor layer is positioned at the top electrode top, and wherein conductor layer and top electrode electrical isolation and conductor layer and doped region are via opening and doped region electrically connect.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein each electrode position is a polygonal body, and the doped region that surrounds electrode position then is positioned at the corner position of polygonal body.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein polygonal body is a regular polygon body.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein each opening is shaped as a quadrangle.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein each opening is shaped as a circle.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein each opening is shaped as a hexagon.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein the material of top electrode comprises doped polycrystalline silicon.
According to the described variable capacitor of the preferred embodiments of the present invention, one second dielectric layer is wherein arranged between top electrode and the conductor layer, and second dielectric layer inserts in the opening, and second dielectric layer has one of exposed doped region of a contact window in each opening.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein the area of each electrode position than the ratio of the gross area of the doped region of last encirclement electrode position more than or equal to 1/3.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein each electrode position is surrounded by six doped regions.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein doped region is arranged in an array with multirow and multiple row in substrate, and the doped region of adjacent two row is alternately arranged.
According to the described variable capacitor of the preferred embodiments of the present invention, wherein electrode position is arranged with a tight complimentary fashion.
The top electrode of variable capacitor of the present invention is constituted with several electrode positions, and each electrode position surrounded by several openings, and these openings expose the doped region that is arranged in substrate respectively.Just each electrode position in the top electrode can be surrounded by the doped region of majority, each electrode position approximately more than or equal to 1/3, can improve the capacitance of each electrode position and the quality factor of variable capacitor (Q factor) than its ratio of the gross area of doped region of last encirclement thus.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A illustrates to looking sketch on according to one preferred embodiment of the present invention a kind of variable capacitor;
Figure 1B illustrates and is the diagrammatic sectional view of the variable capacitor among Figure 1A along I-I;
Fig. 2 illustrates to looking sketch on a kind of variable capacitor of another preferred embodiment according to the present invention;
Fig. 3 illustrates to looking sketch on a kind of variable capacitor of the another preferred embodiment according to the present invention;
Fig. 4 illustrate for according to the present invention more a kind of variable capacitor of a preferred embodiment on look sketch.
The main element symbol description
100: variable capacitor
102: substrate
104: bottom electrode
104a, 204a, 304a, 404a: doped region
106: the first dielectric layers
108,208,308,408: top electrode
108a, 208a, 308a, 408a: electrode position
110,210,310,410: opening
112: the second dielectric layers
114: conductive layer
Embodiment
Figure 1A illustrates to looking sketch on according to one preferred embodiment of the present invention a kind of variable capacitor.Figure 1B illustrates and is the diagrammatic sectional view of the variable capacitor among Figure 1A along I-I.Please refer to Figure 1A and Figure 1B, a variable capacitor 100 is positioned on the substrate 102, and this variable capacitor 100 comprises a bottom electrode 104, and this bottom electrode 104 has a plurality of doped region 104a that are arranged in substrate 102.This substrate 102 can be a Semiconductor substrate, and its material comprises silicon, germanium, germanium silicide, GaAs and indium arsenide, and substrate 102 also can be a sandwich construction again, and for example being has silicon (silicon on insulator) or silicon/germanium silicide on the insulant.Alloy in doped region 104a can be P conduction type ion or N conduction type ion.In addition, doped region 104a is arranged in an array with multirow and multiple row, and the doped region of adjacent two row is alternately arranged.
This variable capacitor comprises that also a top electrode 108 is positioned at substrate 102 tops, and top electrode 108 is made of a plurality of electrode position 108a.The material of this top electrode 108 comprises doped polycrystalline silicon or other conductive material.In addition, top electrode 108 comprises several openings 110, each opening 110 exposed corresponding doped region 104a.Shown in Figure 1A and as mentioned above, because the doped region 104a in the substrate 102 is arranged in an array, and the doped region 104a of adjacent two row alternately arranges, so the arrayed of 110 corresponding doped region 104a of the opening in top electrode 108 in substrate 102, and present the array that adjacent two openings of going are alternately arranged.Again, the shape of each electrode position 108a is defined by several openings, and for example each electrode position is a polygonal body, preferably a regular polygon body.The doped region that surrounds electrode position then is positioned at the corner position of polygonal body.Preferably, the electrode position of top electrode 108 is that tight complimentary fashion is arranged.Shown in Figure 1A, each electrode position 108a is defined by three doped region 104a, and electrode position 108a be shaped as a triangle, and each electrode position 108a each other closely complimentary fashion arrange.Preferably, electrode position 108a's is shaped as an equilateral triangle.Again, each electrode position 108a than its ratio of the gross area of three doped region 104a of last encirclement approximately more than or equal to 1/3.
It should be noted that also to comprise one first dielectric layer 106 between substrate 102 and top electrode 108, the material of this first dielectric layer 106 for example is silica, silicon nitride or silicon oxynitride, and its formation method comprises chemical vapour deposition technique.
In addition, in top electrode 108 and substrate 102 tops one second dielectric layer 112 is arranged, this second dielectric layer 112 is inserted in the opening 110, and this second dielectric layer 112 has a contact window to expose the surface of doped region 104a in each opening 110.The material of this second dielectric layer can be silica, silicon nitride or silicon oxynitride.And the method that forms second dielectric layer comprises sedimentation, preferably chemical vapour deposition technique.
In addition, a conductor layer 114 is positioned at top electrode 108 tops, and with doped region 104a via opening 110 and doped region 104a electrically connect.And conductor layer 114 utilizes second dielectric layer 112 with top electrode 108 and electrical isolation each other.
In the foregoing description, each opening shape in the top electrode 108 is circular, and each electrode position 108a is all surrounded by three doped regions.Yet in practical application, the present invention is not limited to the foregoing description.Below will other Application Examples of the present invention be described respectively with Fig. 2, Fig. 3 and Fig. 4.
Fig. 2 illustrates to looking sketch on a kind of variable capacitor of another preferred embodiment according to the present invention.Please refer to Fig. 2, the difference of Figure 1A and Fig. 2 is, the opening 210 of the top electrode 208 among Fig. 2 be shaped as the quadrangle body.
Fig. 3 illustrates to looking sketch on a kind of variable capacitor of the another preferred embodiment according to the present invention.Please refer to Fig. 3, the opening 310 of top electrode 308 is a hexagonal configuration, and electrode position 308a then is similarly hexagonal configuration, and electrode position 308a and opening 310 formation honeycombs arrangements.In this embodiment, doped region 304a arranges with array way as the doped region 104a among Figure 1A, and the doped region 304a of adjacent two row is staggered, the area of each electrode position 308a and surround one of them rough equating of area of this electrode position doped region 304a, so the area of each electrode position 308a in addition equals 1/3 than the ratio of the gross area of the doped region 304a of last encirclement electrode position 308a.
Fig. 4 illustrate for according to the present invention more a kind of variable capacitor of a preferred embodiment on look sketch.As shown in Figure 4, doped region 404a is arranged in array.Wherein, the electrode position that regional A indicated is positioned at the peripheral position of variable capacitor 400, and the electrode position that regional A indicated is surrounded by five doped region 404a.Moreover the electrode position that area B indicated is positioned at the interior location of variable capacitor 400, and the electrode position that area B indicated is surrounded by six doped region 404a.Again, the electrode position that zone C indicated is positioned at the peripheral position of variable capacitor 400, and the electrode position that zone C indicated is surrounded by seven doped region 404a.In addition, the electrode position that region D indicated is surrounded by eight doped region 404a.And the electrode position that area E indicated is positioned at the peripheral position of variable capacitor 400, and the electrode position that area E indicated is surrounded by nine doped region 404a.As described earlier, the electrode position among Fig. 4 is closely complementary each other to be arranged, and each electrode position can be surrounded by several doped regions.Just, each electrode position than its ratio of the gross area of doped region of last encirclement approximately more than or equal to 1/3.
In sum, the top electrode of variable capacitor of the present invention is constituted with several electrode positions, and each electrode position surrounded by several openings, and these openings expose the doped region that is arranged in substrate respectively.Just each electrode position in the top electrode can be surrounded by the doped region of majority, can improve the capacitance and the quality factor of each electrode position thus.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; under the premise without departing from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention is as the criterion when looking the claims person of defining.
Claims (20)
1. a variable capacitor is positioned on the substrate, and it comprises:
One bottom electrode has and is arranged in a plurality of doped regions that this substrate is arranged in an array, and wherein this array has multirow and multiple row, and those doped regions of adjacent two row are alternately arranged;
One top electrode is positioned at this substrate top, and this top electrode is made of a plurality of electrode position, and this top electrode has a plurality of openings, and each those opening exposes corresponding this doped region, and wherein each those electrode position is directly by three doped regions encirclements;
One first dielectric layer is between this substrate and this top electrode; And
One conductor layer is positioned at this top electrode top, and wherein this conductor layer and this top electrode electrical isolation and this conductor layer and those doped regions are via those openings and those doped region electrically connects.
2. variable capacitor as claimed in claim 1, wherein each those electrode position is a triangle or hexagon, three doped regions that surround this electrode position then are positioned at this triangle or hexagonal corner position.
3. variable capacitor as claimed in claim 2, wherein this triangle or hexagon are an equilateral triangle or regular hexagon.
4. variable capacitor as claimed in claim 1, wherein each those opening is shaped as a quadrangle.
5. variable capacitor as claimed in claim 1, wherein each those opening is shaped as a circle.
6. variable capacitor as claimed in claim 1, wherein the material of this top electrode comprises doped polycrystalline silicon.
7. variable capacitor as claimed in claim 1, one second dielectric layer is wherein arranged between this top electrode and this conductor layer, this second dielectric layer is inserted in those openings, and this second dielectric layer has one of exposed those doped regions of a contact window in each those opening.
8. variable capacitor as claimed in claim 1, wherein the area of each those electrode position than the ratio of the gross area of those doped regions of last this electrode position of encirclement more than or equal to 1/3.
9. a variable capacitor is positioned on the substrate, and it comprises:
One bottom electrode has a plurality of doped regions that are arranged in this substrate;
One top electrode is positioned at this substrate top, and this top electrode is made of a plurality of electrode position, and wherein each electrode position is surrounded by at least five openings, and each those opening exposes corresponding this doped region;
One first dielectric layer is between this substrate and this top electrode; And
One conductor layer is positioned at this top electrode top, and wherein this conductor layer and this top electrode electrical isolation and this conductor layer and those doped regions are via those openings and those doped region electrically connects.
10. variable capacitor as claimed in claim 9, wherein each those electrode position is polygonal bodies, those doped regions that surround this electrode position then are positioned at the corner position of this polygonal body.
11. variable capacitor as claimed in claim 10, wherein this polygonal body is a regular polygon body.
12. variable capacitor as claimed in claim 9, wherein each those opening is shaped as a quadrangle.
13. variable capacitor as claimed in claim 9, wherein each those opening is shaped as a circle.
14. variable capacitor as claimed in claim 9, wherein each those opening is shaped as a hexagon.
15. variable capacitor as claimed in claim 9, wherein the material of this top electrode comprises doped polycrystalline silicon.
16. variable capacitor as claimed in claim 9, one second dielectric layer is wherein arranged between this top electrode and this conductor layer, this second dielectric layer is inserted in those openings, and this second dielectric layer has one of exposed those doped regions of a contact window in each those opening.
17. variable capacitor as claimed in claim 9, wherein the area of each those electrode position than the ratio of the gross area of those doped regions of last this electrode position of encirclement more than or equal to 1/3.
18. variable capacitor as claimed in claim 9, wherein each those electrode position is surrounded by six doped regions.
19. variable capacitor as claimed in claim 9, wherein those doped regions are arranged in an array with multirow and multiple row in this substrate, and those doped regions of adjacent two row are alternately arranged.
20. variable capacitor as claimed in claim 9, wherein those electrode positions are arranged with a tight complimentary fashion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100715226A CN100466296C (en) | 2006-03-29 | 2006-03-29 | Variable capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100715226A CN100466296C (en) | 2006-03-29 | 2006-03-29 | Variable capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101047210A CN101047210A (en) | 2007-10-03 |
| CN100466296C true CN100466296C (en) | 2009-03-04 |
Family
ID=38771591
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100715226A Active CN100466296C (en) | 2006-03-29 | 2006-03-29 | Variable capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100466296C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109708785B (en) * | 2018-12-26 | 2020-10-23 | 中国科学院半导体研究所 | Flexible capacitive touch sensor, electronic skin, wearable device and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1043389C (en) * | 1993-11-19 | 1999-05-12 | 株式会社日立制作所 | Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance and method of man |
| US6362501B1 (en) * | 1999-05-18 | 2002-03-26 | Hyundai Electronics Industries Co., Ltd. | DRAM cell array not requiring a device isolation layer between cells |
| JP2004303809A (en) * | 2003-03-28 | 2004-10-28 | Seiko Epson Corp | Capacitor, storage device, and electronic apparatus |
| US20050285153A1 (en) * | 2004-06-29 | 2005-12-29 | Rolf Weis | Transistor, memory cell array and method of manufacturing a transistor |
-
2006
- 2006-03-29 CN CNB2006100715226A patent/CN100466296C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1043389C (en) * | 1993-11-19 | 1999-05-12 | 株式会社日立制作所 | Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance and method of man |
| US6362501B1 (en) * | 1999-05-18 | 2002-03-26 | Hyundai Electronics Industries Co., Ltd. | DRAM cell array not requiring a device isolation layer between cells |
| JP2004303809A (en) * | 2003-03-28 | 2004-10-28 | Seiko Epson Corp | Capacitor, storage device, and electronic apparatus |
| US20050285153A1 (en) * | 2004-06-29 | 2005-12-29 | Rolf Weis | Transistor, memory cell array and method of manufacturing a transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101047210A (en) | 2007-10-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7705428B2 (en) | Varactor | |
| KR900001225B1 (en) | Semiconductor memory device | |
| US5006481A (en) | Method of making a stacked capacitor DRAM cell | |
| DE4417150C2 (en) | Method for producing an arrangement with self-reinforcing dynamic MOS transistor memory cells | |
| US5798544A (en) | Semiconductor memory device having trench isolation regions and bit lines formed thereover | |
| KR950009890B1 (en) | Semiconductor memory device | |
| US6611059B1 (en) | Integrated circuitry conductive lines | |
| JP2000150816A (en) | Fabrication of both sides of memory array | |
| US4193125A (en) | Read only memory | |
| CN101102100A (en) | Integrated filter structure having improved interchannel isolation and method of manufacture | |
| CN109979939A (en) | Semiconductor memory device structure and manufacturing method thereof | |
| CN102122654B (en) | Varactor and manufacturing method thereof | |
| CN100466296C (en) | Variable capacitor | |
| CN103021956A (en) | PIP (poly-insulator-poly) capacitor of split gate type flash memory and manufacturing method of PIP capacitor | |
| KR20040048350A (en) | Method for fabricating a trench capacitor with an insulation collar, which is electrically connected to a substrate on one side via a buried contact, in particular for a semiconductor memory cell | |
| US4529994A (en) | Variable capacitor with single depletion layer | |
| US5313090A (en) | Bipolar memory cell having capacitors | |
| JPS62177963A (en) | Semiconductor memory device | |
| US4173819A (en) | Method of manufacturing a dynamic random access memory using MOS FETS | |
| JPH0473964A (en) | Semiconductor memory | |
| US20020039834A1 (en) | Gate device with raised channel and method | |
| CN112420661B (en) | Isolation capacitor and preparation method thereof | |
| KR19990052173A (en) | Method of Manufacturing High Performance Inductor Device by Substrate Conversion Technology | |
| KR0155854B1 (en) | Capacitor fabrication method by hsg mask | |
| CN111164755B (en) | Method of forming transistor and method of forming memory cell array |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |