JP2004303118A - Memory control device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control device and a memory control method using an efficient access control in the input and output control of data to a memory shared by a plurality of processing circuits. <P>SOLUTION: This memory control device is provided with a means for detecting the continuity of access permitting situations with respect to a memory access request to control access permission in an independent priority order in continuous access time and under discontinuous access conditions. Thus, access rights to memory access are easily and equally distributed in a lower priority order, thereby realizing the efficient memory access control. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory control device and method for controlling access to a memory used for data processing.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, data processing such as error correction has been performed using a memory in recording and reproduction processing of a medium such as an optical disk. 2. Description of the Related Art In recent years, with the trend of high-speed signal processing and high integration of circuits, a plurality of processing circuits may share one memory. At this time, arbitration of memory access is required because a plurality of processing circuits may simultaneously request access to one memory.
[0003]
As a conventional memory control method, there is a method of prioritizing each request signal in advance and granting access permission based on the priority (for example, see Patent Document 1).
[0004]
FIG. 4 shows a conventional memory control device disclosed in Patent Document 1. 401 is a memory control circuit, 102 is a memory for storing data, 103 and 104 are processing circuits A and B for accessing the memory, and 405 is the priority of a request (REQ) which is a memory access request from the processing circuit. , A permission signal generation circuit that generates a permission signal (ACK) in accordance with the selected request signal, and a command generation circuit that generates an access command to the memory 102. Here, it is assumed that the processing circuits A and B have the request priority in order.
[0005]
The operation of the conventional circuit of FIG. 4 will be described with reference to FIG. 3, which is a timing chart of a request from the processing circuit and a permission signal from the memory control circuit. REQ-A is a request signal (“Hi” Active) which is a memory access request from the processing circuit A, and ACK-A is an access permission signal (“Hi” Active) to the processing circuit A. REQ-B is a request signal (“Hi” Active) which is a memory access request from the processing circuit B, and ACK-B is an access permission signal (“Hi” Active) to the processing circuit B.
[0006]
The memory access in FIG. 3 indicates a processing circuit accessing the memory, and the REQ selection indicates a timing for detecting the REQ (indicated by a triangle in FIG. 3). The priority determination circuit 405 detects REQ-A or REQ-B at a certain period of capture timing, and when both REQ signals are detected, selects and outputs REQ-A having a higher priority and permits The signal generation circuit 106 permits the memory access to the processing circuit A. When only one of the REQ signals is detected, the permission signal generation circuit 406 permits memory access to the processing circuit corresponding to the detected REQ signal. In addition, the memory control circuit 401 that has received the request generates a predetermined command and address, outputs the command and address to the memory 102, and inputs and outputs data from each processing circuit to the memory 102.
[0007]
[Patent Document 1]
Japanese Patent Application Laid-Open No. H11-65919
[Problems to be solved by the invention]
With an increase in the speed of signal processing, the number of times access requests issued from a plurality of processing circuits are duplicated also increases. Therefore, efficient memory access arbitration with few empty cycles of memory access is required.
[0009]
A problem occurring in the conventional circuit will be described with reference to FIG. As shown in the latter half of FIG. 3, when the request REQ-A is continuously output from the processing circuit A having the higher priority, the request REQ-B is output from the processing circuit B having the lower priority at the same time. Even if the request REQ-A stops, the lower-order request REQ-B cannot be accepted, and a wait state occurs in the processing circuit B.
[0010]
Therefore, in order to permit access to the lower processing circuit, the processing circuit having the higher priority temporarily stops the output of the request REQ-A for each access permission and accepts the access of the lower processing circuit. Thereafter, the output of the request REQ-A may be restarted. That is, REQ-A is output intermittently, and ACK-B based on REQ-B can be obtained during the period when REQ-A is not output.
[0011]
However, if the lower request REQ-B is not output when the output of the request REQ-A is temporarily stopped, neither of the processing circuits A and B can access the memory. Will be. Further, even if the timing of resuming the output of the request REQ-A is delayed after the end of the memory access of the processing circuit B, an empty cycle of the memory access occurs.
[0012]
[Means for Solving the Problems]
The above object has a means for detecting continuity of an access permission state for a memory access request, and changing a priority order under a continuous access condition and a non-consecutive access condition to thereby obtain a memory of a processing circuit having a lower priority order. This can be improved by distributing the access right evenly to the access request and efficiently accessing the memory without generating useless idle time.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0014]
FIG. 1 is a block diagram showing a configuration of a memory control device according to a first embodiment of the present invention. The description of those equivalent to those in FIG. 4 is omitted. 101 is a memory control circuit, 105 is a priority determination circuit that determines a request from a processing circuit based on priority, 108 is a continuity detection circuit that detects continuity based on a selected request, and 109 to 112 are input of request signals. AND gates 113 and 114 are inverters for inverting the values.
[0015]
FIG. 5 shows a detailed diagram of the request continuity detection circuit 108 in FIG. Reference numerals 501 and 502 in FIG. 5 denote increments each time a request of a corresponding processing circuit is selected and a permission signal is output, and is reset when the request is not selected. Reference numeral 503 denotes a predetermined number setting circuit for setting the number of consecutive times to a predetermined number (N: natural number). Reference numerals 504 and 505 compare the respective counter values with the predetermined number, and decrement the counter value by one from the predetermined number N. This is a comparator that outputs a continuity detection signal when it reaches (N-1).
[0016]
When the value set in the predetermined number setting circuit 503 is "2", the continuity detection returns to "Hi" when one of the requests is selected and the permission signal is output, and returns to "Low" at the next request fetch timing. Generate and output signals.
[0017]
Hereinafter, the operation of the memory control device according to the first embodiment will be described with reference to the timing chart of FIG. In FIG. 6, continuity-A and continuity-B are request continuity detection signals (“Hi” Active) in the processing circuits A and B, respectively. Others are equivalent to FIG.
[0018]
Here, in this embodiment, using the continuity detection signal, the priority of the request is determined by REQ-A (continuity detection signal “Low”), REQ-B (continuity detection signal “Low”), REQ- A (continuity detection signal “Hi”) and REQ-B (continuity detection signal “Hi”).
[0019]
Since the request REQ-A that is repeated a predetermined number of times has a lower priority than the request REQ-B, the request REQ-A has a lower priority at a predetermined ratio using the request continuity detection signal without waiting for the end of the request REQ-A. It is possible to permit an access request for the request (REQ-B) of the processing circuit B having
[0020]
More specifically, when two requests (REQ-A, REQ-B) are output at the same time as shown in FIG. 6, at the first fetch timing, the priority determination circuit 105 performs the processing with the higher priority. The request of the circuit A is selected, and the permission signal generation means 106 outputs a permission signal ACK-A to the processing circuit A. However, at the next fetch timing, although the REQ-A is still output, the request from the processing circuit A is sent to the processing circuit B because the continuity detection signal generated by the continuity detection circuit 108 is output. , The priority determination circuit 105 selects a request from the processing circuit B, and the permission signal generation means 106 outputs a permission signal ACK-B to the processing circuit B. Note that even when REQ-A is continuously output, when REQ-B is not output, REQ-A is continuously enabled, so that the processing circuit A continuously performs memory access. it can.
[0021]
FIG. 2 is a block diagram showing a configuration in which the memory control device according to the first embodiment of the present invention is applied to an optical disk recording / reproducing device. 201 is a disk, 202 is a pickup for recording / reproducing data on the disk 201, 203 is a spindle motor for rotating the disk 201, and 204 is an analog processing such as a waveform equalization processing of an analog reproduction signal obtained from the disk 201. AFE (Analog Front End), 205 is an RD-CH (Read Channel) for binarizing data and generating a synchronous clock, 206 is a servo for performing servo control processing in a drive mechanism, and 207 is for digital data read from a disk. A decoding circuit 208 performs demodulation processing, error correction processing, and output scrambling processing. An encoding circuit 208 performs scramble processing, error correction code addition, and modulation processing on input data to generate recording data. river), 210 is an external host (e.g. a personal computer), 211 deals with input and output data from the host 210 I / F (Interface), 212 is a microcomputer which controls the system.
[0022]
In the recording / reproducing apparatus as shown in FIG. 2, the memory 102 is used when data decoding / encoding processing during recording / reproducing and when input / output data is stored in the host, and the memory control circuit 101 performs arbitration of memory access for each processing. At the time of high-speed processing, memory access by a plurality of arithmetic processing in data decoding / encoding processing and memory access in input / output to the host increase. However, by using the memory control circuit 101 described in the first embodiment, it is possible to efficiently perform the processing. Memory access becomes possible and high-speed processing can be realized.
[0023]
As described above, in the first embodiment, by changing the priority by the priority change signal (in this embodiment, the continuity detection signal), efficient memory control capable of coping with high-speed processing can be easily realized. Further, since it is not necessary for the processing circuit to consider the access of the lower priority, it is easy to generate the request signal to be output.
[0024]
Here, the configuration of the device corresponding to the present embodiment is a configuration in which a priority change signal generation circuit, an AND gate, and an inverter are added to the conventional memory control device. This can be realized without increasing the number of circuits. In addition, although the request fetch timing is performed at a fixed cycle, the same configuration can be made in a variable cycle in which the fetch timing is continuously generated when no request is selected.
[0025]
In the present embodiment, the number of consecutive requests for changing the priority of requests is set to “2”. However, the present invention is not limited to this, and an appropriate natural number other than 1 can be set. Also, the invention has been described with an example in which there are two processing circuits, but the number of processing circuits is not limited to this, and an appropriate number can be selected.
[0026]
Priority (continuity detection signal “Low”) of the first processing circuit, ‥, REQ (continuity detection signal “Low”) of the Nth processing circuit, REQ (continuity detection signal “Hi”) of the Nth processing circuit, ‥, and REQ (continuity detection signal “Hi”) of the Nth processing circuit. In this embodiment, the continuity detection signals corresponding to all the processing circuits have been described. However, the continuity detection signals corresponding to the lowest priority processing circuits are used for an appropriate number of processing circuits. A similar configuration is possible without this. Priority (continuity detection signal “Low”) of the first processing circuit, ‥, REQ (continuity detection signal “Low”) of the (N−1) th processing circuit as priority in the N (natural number) processing circuits. ), REQ of Nth processing circuit, REQ of first processing circuit (continuity detection signal “Hi”), Δ, REQ of (N−1) th processing circuit (continuity detection signal “Hi”) It consists of.
[0027]
FIG. 7 is a block diagram showing a configuration of a memory control device according to a second embodiment of the present invention. Reference numeral 701 denotes a memory control circuit, and reference numerals 702 and 703 denote flip-flops (FF) for latching each request permission signal (ACK) once by a clock. The description of the same components as those in FIG. 1 is omitted.
[0028]
Hereinafter, the operation of the memory control device according to the second embodiment will be described with reference to the timing chart of FIG. 8 is a signal obtained by latching the ACK-A and ACK-B access permission signals once by a clock. Others are equivalent to FIG.
[0029]
The request permission signal for each processing signal is latched by a flip-flop and the timing is adjusted to use it as a substitute for the continuity detection signal twice. By combining this signal with the request signal, the priority of one processing circuit request can be changed. Can be easily realized.
[0030]
In this embodiment, the priority order of the requests is the order of the first request of the processing circuit A, the first request of the processing circuit B, the second consecutive request of the processing circuit A, and the second consecutive request of the processing circuit B.
[0031]
Therefore, in the case of accessing a plurality of times by the request (REQ-A) of the processing circuit A having the higher priority, even if the request output is not completed until the predetermined number of times (two times in the figure), the request is output once every two times. , The access request permission can be easily allocated to the request (REQ-B) of the processing circuit B having the priority of (1).
[0032]
As described above, in the second embodiment, by changing the priority using the priority change signal (in this embodiment, the permission signal), efficient memory control capable of coping with high-speed processing can be easily realized. Further, since it is not necessary for the processing circuit to consider the access of the lower priority, it is easy to generate the request signal to be output. Furthermore, in the present embodiment, if the memory control device is limited to a memory control device having a continuity detection circuit for two consecutive times, it is possible to cope with it only by adjusting the timing of the permission signal without adding a new circuit for generating a switching signal. , Can be realized with a simpler configuration than in the first embodiment.
[0033]
FIG. 9 is a block diagram showing the configuration of the memory control device according to the third embodiment of the present invention. Reference numeral 901 denotes a memory control circuit; 902, an external microcomputer; and 903, a circuit for generating a priority switching signal based on settings by the external microcomputer 902. The description of the same components as those in FIG. 1 is omitted.
[0034]
Hereinafter, the operation of the memory control device according to the third embodiment will be described with reference to the timing chart of FIG. The switching signal-A and the switching signal-B in FIG. 10 are switching signals corresponding to the processing circuits A and B, respectively, and can be arbitrarily set by the microcomputer 902. By combining the request signal with a switching signal that can be set from the microcomputer, it is possible to easily change the priority of a request from one processing circuit. As a result, the change of the priority can be controlled by the external microcomputer, and the priority of the processing circuit having the higher priority can be temporarily reduced to the lower.
[0035]
In this embodiment, as shown in FIG. 10, if the normal switching signal is set to “Low” for all the processing circuits, the first and second priorities become valid, and the processing circuits A, The priority order of the processing circuit B is controlled. Therefore, if only the switching signal for the processing circuit A having the higher priority is set to “Hi”, the second and third priorities are effective, and thus the processing circuit B and the processing circuit A are arranged in a priority system. Can be changed.
[0036]
As described above, in the third embodiment, a memory control circuit capable of changing the priority order to some extent can be realized without a large circuit change and a large-scale circuit increase.
[0037]
【The invention's effect】
As described above, in the memory control device of the present invention, the right to access the memory access request of the lower priority processing circuit can be appropriately allocated, and efficient memory access can be performed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the configuration of a memory control device according to a first embodiment of the present invention; FIG. 2 is a block diagram showing the configuration of an optical disk recording / reproducing device using the memory control device according to the first embodiment of the present invention; FIG. 3 is a timing chart of a request from a processing circuit and a permission signal from a memory control circuit. FIG. 4 is a block diagram showing a configuration of a conventional memory control device. FIG. 5 is a first embodiment of the present invention. FIG. 6 is a detailed diagram of a request continuity detection circuit in a memory control device as an example. FIG. 6 is a timing chart of a request from a processing circuit and a permission signal from the memory control circuit during a continuous access process according to the first embodiment of the present invention. FIG. 7 is a block diagram illustrating a configuration of a memory control device according to a second embodiment of the present invention. FIG. 8 is a diagram illustrating a request and a memory from a processing circuit during a continuous access process according to the second embodiment of the present invention. control FIG. 9 is a block diagram showing a configuration of a memory control device according to a third embodiment of the present invention. FIG. 10 is a diagram showing a continuous access process in the third embodiment of the present invention. Diagram of the request from the processing circuit of FIG. 1 and the permission signal from the memory control circuit
101: memory control circuit, 102: memory, 103: processing circuit A, 104: processing circuit B, 105: priority determination circuit, 106: permission signal generation circuit, 107: command generation circuit, 108: request continuity detection circuit, 109 AND gate, 110 AND gate, 111 AND gate, 112 AND gate, 113 inverter, 114 inverter, 201 optical disk, 202 pickup, 203 spindle motor, 204 AFE, 205 RD-CH , 206 servo, 207 decode circuit, 208 encode circuit, 209 LDD, 210 host, 211 I / F, 212 microcomputer, 401 memory control circuit, 405 priority determination circuit, 501 counter A , 502... Counter B, 503... Predetermined number of times setting Road, 504 ... comparator A, 505 ... comparator B, 701 ... memory controller, 702 ... flip-flop, 703 ... flip-flop, 901 ... memory controller, 902 ... microcomputer, 903 ... switching signal generating circuit

Claims (7)

A plurality of processing means for performing processing in a predetermined data unit,
A memory for temporarily storing processing data targeted by the processing means,
Control means for performing data input / output control between the memory and the plurality of processing means based on priority;
Continuous access detection means for detecting the number of continuous accesses to the memory by the processing means,
A memory control device comprising: The memory control device according to claim 1,
The continuous access detection means independently generates a continuous access detection signal for each processing means, and increments the number of accesses each time the corresponding processing means accesses the memory in predetermined data units for each predetermined unit. A memory control device comprising counting means. The memory control device according to claim 1 or 2,
The memory control device according to claim 1, wherein said continuous access detection means outputs a continuous access detection signal when the number of continuous accesses to said memory by any of said processing means reaches a predetermined number. The memory control device according to claim 1,
The control means determines a processing means that can access the memory access request from each processing means by changing a priority of the access request between a continuous access detection time and a non-detection time. A memory control device comprising means. A memory for temporarily storing data to be processed,
First processing means for performing first signal processing on data obtained from the memory;
Second processing means for performing a second signal processing on the data obtained from the memory;
Selecting means for selecting any one of the access request signals to the memory output from the first processing means or the memory output from the second processing means based on the priority order;
Memory access permitting means for permitting the processing means that has output the access request signal selected by the selecting means to access the memory;
A counter that counts the number of consecutive times of the first memory access request signal,
When the counter counts the first memory access request signal continuously for a predetermined number of times, the priority of the first memory access request signal and the priority of the second memory access request signal are changed. Memory management device. A memory control method in an apparatus having a memory for temporarily storing data to be processed and a plurality of processing means for performing signal processing on data obtained from the memory,
A priority order for each access request output when each of the plurality of processing units accesses the memory is changed when any processing unit continuously accesses the memory a predetermined number of times (an integer number of 2 or more). A memory control method. A memory control method in an apparatus having a memory for temporarily storing data to be processed and a plurality of processing means for performing signal processing on data obtained from the memory,
A memory control method, wherein priority of each access request output when each of the plurality of processing units accesses the memory is changed based on a priority change signal from outside.

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