JP2006309530A - Bus arbitration circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus arbitration circuit capable of accepting a request with a lower priority without placing a disproportionate emphasis on requests from a specified bus master. <P>SOLUTION: The bus arbitration circuit 10 comprises a priority control part 101 and a bus adjustment part 102. The priority control part 101 sets and changes the priority of each request from a plurality of bus masters at predetermined time intervals. The bus arbitration part 102 arbitrates respective requests based on the priority set and changed by the priority control part 101. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a bus arbitration circuit that performs arbitration based on priority order for requests from a plurality of bus masters.

  When a plurality of bus masters request to use a bus to access a storage device such as a DRAM (Dynamic Random Access Memory) at the same time, these requests are arbitrated by a bus arbitration circuit.

  FIG. 5 shows a configuration of a conventional bus arbitration circuit in the optical disc apparatus. When a plurality of bus masters request a bus for accessing a storage device, the bus arbitration circuit 100 selects one request based on the priority order of requests from each bus master, and the bus master of the request source receives a bus request. Allow use. The priority order is set so that the host transfer request is the highest priority, and is fixed in the following order: demodulation processing request, ECC (Error Correcting Code) processing request, syndrome calculation request.

In addition, there is a technique that counts the number of times a request is received, and accepts a request with a lower priority when a predetermined number of times is reached, thereby ensuring that these requests are accepted evenly (see, for example, Patent Documents 1 and 2). .
Japanese Patent Laid-Open No. 08-235107 (2nd page, FIG. 2) No. 2887476 (2nd page, FIG. 1)

  However, if a fixed priority is assigned to each request, if the bus is requested at the same time, the bus master of the request source having a high priority is permitted to use the bus. However, it is difficult to use the bus. As a result, there is a risk that the processing of the lower-level bus master will systematically fail. In particular, this risk increases as the optical disk apparatus performs high-speed reproduction and recording processing.

  By the way, in the optical disk apparatus, the host transfer speed is improved in accordance with the improvement in performance of the host apparatus. In recent host apparatuses, interfaces of 100 MBps ATA 100 and 133 MBps ATA 133 are standardized, and therefore host transfer requests are generated more frequently than before. For this reason, it is essential for the optical disk apparatus having a high-speed interface to make the host transfer request the highest.

  FIG. 6 shows an example of bus arbitration when the host transfer request has the highest priority. A block shown for each request indicates a bus request period, and a portion drawn with diagonal lines indicates that the bus request is accepted by the bus arbitration circuit 100. All host transfer requests are accepted because they are located at the highest priority. On the other hand, since there are fewer opportunities to receive requests with lower priority, there is a possibility that the system will fail in order from the processing of the bus master with the lower priority.

  On the other hand, FIG. 7 shows an example of bus arbitration when the host transfer request has the lowest priority. When the host transfer request is at the lowest level, the number of times that the host transfer request is accepted for the demodulation processing request, the ECC processing request, and the syndrome calculation request is relatively large, and thus the above-described danger can be avoided. However, since the host transfer request located at the lowest order can be accepted fewer times, data transfer at a stable speed to the host device cannot be realized.

  In view of the above problems, an object of the present invention is to realize a bus arbitration circuit that can accept a request with a lower priority without biasing to a request from a specific bus master.

  Means taken by the present invention to solve the above problems is a bus arbitration circuit, a priority control unit for changing the priority of each request from a plurality of bus masters at predetermined time intervals, and priority control And a bus arbitration unit that arbitrates the above requests based on the priority order changed by the unit.

  According to the present invention, the priority order of the requests from the plurality of bus masters is set and changed at predetermined time intervals by the priority order control unit, and the bus arbitration unit sets the priority levels of the requests based on the changed priority order. Request is arbitrated. As a result, a bus arbitration circuit that can accept lower priority requests without being biased to requests from a specific bus master is realized.

  Specifically, when the given clock is at the first logic level, the priority control unit sets the priority of each request to a predetermined order, while the clock is at the second logic level. In this case, the priority order of a predetermined request is set to the lower order.

  More specifically, the priority control unit sets the priority of the predetermined request to the highest level when the clock is at the first logic level, while the clock is set at the second logic level. When it is level, the priority order of the predetermined request is set to the lowest.

  Specifically, the bus arbitration unit outputs a signal when a predetermined request is received, and the priority order control unit outputs a given clock from the first logic level to the second logic level. It is assumed that the priority order of each of the above requests is set to a predetermined order when the change is made, while the priority order of the above predetermined request is set to a lower order when the above signal is received.

  More specifically, the priority control unit sets the priority order of the predetermined request to the highest level when the clock changes from the first logic level to the second logic level. When the above signal is received, the priority order of the predetermined request is set to the lowest.

  More specifically, the clock period is changed according to the interval at which a predetermined bus master makes the predetermined request.

  Specifically, it is assumed that the bus arbitration circuit includes an order change permission / rejection unit for selecting whether or not priority setting change is possible.

  More specifically, the bus arbitration circuit permits the bus master making the predetermined request to access one bank of the storage device once every cycle of the clock. .

  The means taken by the present invention in order to solve the above-mentioned problem is a bus arbitration method, wherein a first step of setting and changing the priority of each request from a plurality of bus masters at predetermined time intervals, And a second step of arbitrating each of the requests based on the priority order changed in one step.

  According to the present invention, the priority of each request from a plurality of bus masters is set and changed every predetermined time interval, and the above requests are arbitrated based on the changed priority. As a result, it is possible to accept a request with a lower priority without biasing to a request from a specific bus master.

  Specifically, the first step sets the priority of each request to a predetermined order when the given clock is at the first logic level, while the clock is at the second logic level. In this case, the priority order of a predetermined request is set to the lower order.

  More specifically, the first step sets the priority of the predetermined request to the highest level when the clock is at the first logic level, while the clock is set at the second logic level. When it is level, the priority order of the predetermined request is set to the lowest.

  More specifically, a third step of detecting that a predetermined request has been accepted is provided, and the first step has a given clock changed from the first logic level to the second logic level. When the priority order of each of the above requests is set to a predetermined order, while the third step detects that the above predetermined request has been accepted, the priority order of the above predetermined request is set. It shall be set to the lower order.

  More specifically, the first step sets the priority of the predetermined request to the highest level when the clock changes from the first logic level to the second logic level, When acceptance is detected in step 3, the priority order of the predetermined request is set to the lowest.

  According to the present invention, a request having a lower priority can be accepted without being biased toward a request from a specific bus master. Then, the processing of the bus master of the lower request source is stably executed systematically while maintaining the high speed of data transfer with the host device.

  The best mode for carrying out the present invention will be described below with reference to the drawings. The bus arbitration system according to each embodiment of the present invention will be described as relating to signal processing in an optical disc apparatus.

(First embodiment)
FIG. 1 shows a configuration of a bus arbitration circuit according to the first embodiment of the present invention. The bus arbitration circuit 10 includes a priority order control unit 101, a bus arbitration unit 102, and an order change permission / inhibition unit 103.

  The priority control unit 101 sets the priority in synchronization with the given clock clk. When the clock clk is at the Hi level, the priority control unit 101 sets the priority in the order of host transfer request, demodulation processing request, ECC processing request, and syndrome calculation request (hereinafter referred to as order 1). When the level is Lo, the demodulation processing request, ECC processing request, syndrome calculation request, and host transfer request are set in this order (hereinafter referred to as order 2). The correspondence relationship between the clock clk and the above order may be reversed. The clock clk may be generated inside the priority control unit 101. The priority control unit 101 can be realized by a simple circuit such as a timer.

  The bus arbitration unit 102 performs bus arbitration according to the priority order set by the priority order control unit 101.

  FIG. 2 shows an example of bus arbitration by the bus arbitration circuit 10 according to the present embodiment. Immediately before the “first period”, a demodulation processing request is accepted. When the clock clk becomes Hi level and the “first period” is started, the priority order is set to the above order 1. When the received demodulation processing request processing is completed, a host transfer request is received next. When the processing of the accepted host transfer request is completed, the ECC processing request and the syndrome calculation request are subsequently accepted in order. Similarly, in the “second cycle”, when the clock clk is at the Hi level, the host transfer request is first preferentially accepted.

  In general, storage devices are shared by using separate banks for each bus master. In the “first period” and “second period” in FIG. 2, the host transfer request is accepted only once in each period. Therefore, the bus master requesting the host transfer can access one bank in the storage device at a frequency of once per cycle.

  The order change permission / inhibition unit 103 selects whether or not priority order can be changed. For example, the order change enable / disable unit 103 fixes the priority order as in the conventional case when the host transfer rate is low, and allows the priority order to be changed as described above when the host transfer rate is high. As a result, an optimum bus arbitration method can be selected according to the reproduction and recording speed.

  As described above, according to the present embodiment, even when host transfer requests are frequently generated, it is possible to accept lower priority requests without biasing to host transfer requests. This increases the chances of accepting a syndrome calculation request or the like having a low priority order, so that the processing of the requesting bus master is executed systematically.

  Note that it is preferable to change the cycle of the clock clk in accordance with the cycle of the host transfer request. As a result, the priority order can be set as order 1 for each host transfer request, and the high-speed transfer to and from the optical disc apparatus is maintained. For example, in a system operating with a 33 MHz master clock and a bandwidth of 8 bytes per cycle, if the priority control unit 101 controls the host transfer request to have the highest priority once every four cycles, 66 bps Stable host transfer is realized. If the system is configured in this manner, the host transfer request frequency is low for a low-speed host device such as the ATA 33, and therefore the host transfer request priority is always the highest priority and the performance of the system so far. Compatibility is maintained. Conversely, for a high-speed host device such as the ATA 100, a system in which the host transfer rate is suppressed and high-speed playback and recording do not fail is realized with a simple circuit.

  Further, the rank change enable / disable unit 103 may select statically instead of selecting dynamically. Further, the rank change permission / inhibition unit 103 may be omitted.

(Second Embodiment)
In FIG. 2, when the processing period of the ECC processing request received immediately before the end of the “second period” is longer than the Hi level period of the clock clk immediately after the start of the “third period”, the ECC processing request is being processed. In addition, the period in which the priority order is order 1 ends. For this reason, after the processing of the ECC processing request is completed, the priority of the host transfer request has already been changed to the lowest order, and therefore other requests are given priority over the host transfer request. When the Hi level period in one cycle of the clock clk is fixed, the above problem may occur. In order to solve the above problem, in the bus arbitration circuit according to the second embodiment of the present invention, when a host transfer request is accepted, the priority order is changed from order 1 to order 2.

  The bus arbitration circuit according to the second embodiment of the present invention will be described below.

  FIG. 3 shows a configuration of the bus arbitration circuit according to the present embodiment. The bus arbitration circuit 10A includes a priority order control unit 101A and a bus arbitration unit 102A.

  The priority order control unit 101A sets the priority order to 1 every time the clock clk rises. When the signal Sig1 indicating acceptance of the host transfer request is received, the priority order is changed to order 2.

  The bus arbitration unit 102A performs bus arbitration according to the priority set by the priority control unit 101A. When the host transfer request is received, the signal Sig1 is output.

  FIG. 4 shows an example of bus arbitration by the bus arbitration circuit 10A according to the present embodiment. Immediately before the “first period”, a demodulation processing request is accepted, and the priority is set to order 1 when the clock “clk” becomes Hi level and the “first period” starts. This order is maintained by the priority control unit 101A until the signal Sig1 is received, that is, until a host transfer request is accepted. When a host transfer request is accepted, the priority is changed to order 2, and thereafter an ECC processing request and a syndrome calculation request are accepted in order.

  Even after the “second period”, the order is set by the same process as the “first period”.

  As described above, according to the present embodiment, even when a host transfer request frequently occurs, the host transfer request is accepted more reliably than in the first embodiment. On the other hand, when the host transfer rate is low and host transfer requests are not frequently generated, according to the present embodiment, the priority order is set to order 1 in each cycle. This means that it is equivalent to the conventional case where the priority order is fixed. Therefore, according to this embodiment, a host transfer request is accepted more reliably and stably than in the first embodiment, regardless of the host transfer speed.

  Note that the rank change possibility / non-permission unit 103 provided in the first embodiment is not required in the present embodiment for the reason described above. For this reason, the bus arbitration circuit 10A in the present embodiment can realize a function with a smaller area than the bus arbitration circuit 10 in the first embodiment.

  In each of the above embodiments, the priority order of the host transfer request is one of the highest order and the lowest order, but it is not necessary to limit to this. For example, the priority of the host transfer request may be set to the second place in the order 1, and if the other requests are not affected in the order 2, the priority of the host transfer request is set to the third place. It may be set.

  In the above embodiments, the priority order is changed only for the host transfer request, but the priority order may be changed for other requests. For example, even for a syndrome calculation request whose priority is always in the lower order, the number of times this request is accepted can be increased by changing the priority. As a result, high-speed reproduction and recording processing in the optical disc apparatus becomes more stable.

  The bus arbitration circuit according to the present invention increases the chances of accepting lower-order requests while maintaining the high speed of data transfer with the host device. Therefore, in the optical disc apparatus that requires high-speed reproduction and recording processing. Useful.

1 is a configuration diagram of a bus arbitration circuit according to a first embodiment of the present invention. It is the figure which showed the example of bus arbitration by the bus arbitration circuit which concerns on the 1st Embodiment of this invention. It is a block diagram of the bus arbitration circuit which concerns on the 2nd Embodiment of this invention. It is the figure which showed the example of bus arbitration by the bus arbitration circuit which concerns on the 2nd Embodiment of this invention. It is a block diagram of the conventional bus arbitration circuit in an optical disk apparatus. It is the figure which showed the example of bus arbitration in case the priority of a host transfer request is the highest. It is the figure which showed the example of bus arbitration when the priority of a host transfer request is the lowest.

Explanation of symbols

10, 10A Bus arbitration circuit 101, 101A Priority control unit 102, 102A Bus arbitration unit 103 Order change enable / disable unit

Claims (13)

A priority controller that changes the priority of each request from a plurality of bus masters at predetermined time intervals;
A bus arbitration circuit comprising: a bus arbitration unit that arbitrates the requests based on the priority changed by the priority control unit. The bus arbitration circuit according to claim 1,
The priority control unit
When the given clock is at the first logic level, the priority of each request is set to a predetermined order, while when the clock is at the second logic level, the priority of the predetermined request is set to the lower order. A bus arbitration circuit characterized by setting. The bus arbitration circuit according to claim 2,
The priority control unit
When the clock is at the first logic level, the priority of the predetermined request is set to the highest level, while when the clock is at the second logic level, the priority of the predetermined request is set to the lowest. A bus arbitration circuit characterized by setting. The bus arbitration circuit according to claim 1,
The bus arbitration unit
When a predetermined request is received, a signal is output.
The priority control unit
When a given clock changes from a first logic level to a second logic level, the priority of each request is set to a predetermined order, while when the signal is received, the priority of the predetermined request is set. The bus adjustment circuit is characterized in that is set to the lower order. In the bus arbitration circuit according to claim 4,
The priority control unit
When the clock changes from the first logic level to the second logic level, the priority level of the predetermined request is set to the highest level, and when the signal is received, the priority level of the predetermined request is set to the highest level. A bus adjustment circuit characterized by being set at a lower level. The bus arbitration circuit according to any one of claims 2 and 4,
The bus arbitration circuit is characterized in that the cycle of the clock is changed according to an interval at which a predetermined bus master makes the predetermined request. The bus arbitration circuit according to claim 1,
A bus arbitration circuit comprising an order change enable / disable unit for selecting whether or not to change a priority order setting. The bus arbitration circuit according to any one of claims 2 and 4,
A bus arbitration circuit, wherein a bus master that makes the predetermined request is allowed to access one bank of the storage device once every cycle of the clock. A first step of changing the priority of each request from a plurality of bus masters at predetermined time intervals;
A bus arbitration method comprising: a second step of arbitrating each request based on the priority level changed in the first step. In the bus arbitration method according to claim 9,
The first step includes
When the given clock is at the first logic level, the priority of each request is set to a predetermined order, while when the clock is at the second logic level, the priority of the predetermined request is set to the lower order. A bus arbitration circuit characterized by setting. The bus arbitration method according to claim 10,
The first step includes
When the clock is at the first logic level, the priority of the predetermined request is set to the highest level, while when the clock is at the second logic level, the priority of the predetermined request is set to the lowest. A bus arbitration method characterized by setting. In the bus arbitration method according to claim 9,
Comprising a third step of detecting that a predetermined request has been accepted;
The first step includes
When the given clock changes from the first logic level to the second logic level, the priority of each request is set to a predetermined priority, while the predetermined request is accepted by the third step. When this is detected, the priority order of the predetermined request is set to the lower order. The bus arbitration method according to claim 12,
The first step includes
When the clock changes from the first logic level to the second logic level, the priority of the predetermined request is set to the highest level, while the predetermined request is accepted by the third step. A bus arbitration method, wherein when detected, the priority order of the predetermined request is set to the lowest order.

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