JP2004303116A - Data processor and data processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor capable of saving electric power by automatically supplying a clock only during the execution of data processing and stopping the supply of the clock except during the execution. <P>SOLUTION: This data processor comprises a data processing circuit performing prescribed data processing when the start of data processing is instructed, and outputting a termination signal when processing is finished. The clock supplied to the data processing circuit is controlled by a data processing start signal, and the data processing start signal is delayed by a delay circuit and inputted to the data processor. Data processing can thereby be started after starting the supply of the clock. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to power saving of a data processing device.
[0002]
[Prior art]
In a data processing device composed of a synchronous circuit, various functional circuit blocks for taking in a data input signal supplied to itself in synchronization with a clock signal are included, and these functional circuit blocks are usually included in these functional circuit blocks. It is configured such that a clock signal is always supplied.
[0003]
However, as the circuit scale increases and the operating speed increases, a large amount of power is consumed only by constantly inputting a clock signal.
[0004]
Therefore, in Patent Document 1, means for determining whether a predetermined functional block is operating and means for supplying a clock only when the predetermined functional block is operating are provided. The supply has been stopped.
[0005]
In Patent Document 2, as means for determining whether or not a predetermined functional block is operating, the state of two or more signals input from input pins is monitored, and all of these two or more signals are monitored. Is stopped for a predetermined time or more, and the operation or stop of the internal clock signal supplied to the internal circuit is controlled accordingly.
[0006]
[Patent Document 1]
JP-A-7-99434 [Patent Document 2]
JP-A-11-143570
[0007]
[Problems to be solved by the invention]
Some functional circuit blocks perform predetermined data processing when externally instructing the start of data processing, and output an end signal when the processing is completed and stop. In this case, there is no need to monitor the internal state and determine whether to supply or stop the clock externally. The clock may be supplied simultaneously with an external processing start instruction, and the clock may be stopped simultaneously with the processing end signal.
[0008]
However, since the clock supply is started by the processing start instruction signal, this functional circuit block receives the clock supply after receiving the processing start instruction signal.
[0009]
Therefore, the rising edge of the processing start instruction signal cannot be detected, and the data processing operation may not be started even when the clock is supplied. Further, even when the processing start instruction signal is a short pulse, the rising edge cannot be detected, and the data processing operation may not be started even when the clock is supplied.
[0010]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a data processing device capable of reliably starting a data processing operation by allowing a functional circuit block to receive a processing start instruction signal after a clock is supplied.
[0011]
[Means for Solving the Problems]
In the data processing apparatus including a data processing circuit that performs a predetermined data processing when a data processing start is instructed and outputs an end signal when the processing is completed, a clock supplied to the data processing circuit is a data processing start signal. By inputting the data processing start signal to the data processing device after being delayed by the delay circuit, the data processing device can be improved by starting the data processing after the clock supply is started.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment in which the present invention is applied to a data processing device in an optical disk reproducing device will be described with reference to the drawings.
[0013]
FIG. 14 is a block diagram showing an optical disk reproducing apparatus including the data processing apparatus according to the first embodiment of the present invention. The data read from the optical disk 14 by the optical pickup 15 is amplified by the preamplifier 16, demodulated by the demodulation circuit 17, and then written to the DRAM 3 via the RAM controller 2. The data written in the DRAM 3 is subjected to error correction by the error correction circuit 1 via the RAM controller 2, descrambled by the descrambling circuit 18, and then sent to the host PC via the host interface 19.
[0014]
FIG. 1 is a block diagram showing a data processing device according to a first embodiment of the present invention. Reference numeral 1 denotes an error correction circuit which inputs / outputs data ecc_data from / to the DRAM 3 via the RAM controller 2 and performs error correction of data on the DRAM 3. The error correction circuit 1 starts the error correction start signal ecc_start from the RAM controller 2 by delayed_ecc_start delayed by the delay circuit 4, executes a predetermined error correction, and then outputs the error correction end signal ecc_end to the RAM controller 2 and the RS flip-flop. Output to 5 and stop. The operation clock of the error correction circuit 1 is ecc_clk.
[0015]
A RAM controller 2 adjusts a DRAM access request from the error correction circuit 1 or another circuit not shown in the figure, and controls data read / write of the DRAM 3. Reference numeral 3 denotes a DRAM, which performs data read / write under the control of the RAM controller 2. Reference numeral 4 denotes a delay circuit that outputs to the error correction circuit 1 a delayed_ecc_start obtained by delaying the error correction activation signal ecc_start from the RAM controller 2. Reference numeral 5 denotes an RS flip-flop, which sets a clock on / off control signal ecc_clken to "H" by ecc_start and to "L" by ecc_end. Reference numeral 6 denotes a clock gate, which gates a constantly operating clock by ecc_clken to supply and stop the operation clock ecc_clk of the error correction circuit 1. The supply of ecc_clk is started by ecc_start and is stopped by ecc_end. The error correction circuit 1 receives the activation signal delayed_ecc_start after the supply of the ecc_clk, outputs the end signal ecc_end, and stops the supply of the ecc_clk.
[0016]
Next, the operation of the data processing circuit according to the first embodiment of the present invention will be described with reference to a timing chart. FIG. 2 is a timing chart showing the supply and stop of the operation clock ecc_clk of the error correction circuit 1.
[0017]
When the error correction start signal ecc_start is output from the RAM controller 2, the clock on / off control signal ecc_clken output from the RS flip-flop becomes “H”, and ecc_clk is supplied to the error correction circuit 1. After ecc_clk is supplied, delayed_ecc_start is input to the error correction circuit 1 to start error correction.
[0018]
When the error correction is completed, an end signal ecc_end is output and the operation is stopped. When ecc_end is output, ecc_clken output from the RS flip-flop becomes “L”, and supply of ecc_clk to the error correction circuit 1 is stopped.
[0019]
As described above, in the first embodiment of the present invention, the clock is supplied to the error correction circuit 1 only during the data processing, and the power supply is stopped by stopping the clock supply except during the processing. Further, since the start signal is received after the clock is supplied, the data processing operation can be reliably started.
[0020]
FIG. 3 is a block diagram showing a data processing device according to a second embodiment of the present invention. The description of the same parts as in the first embodiment is omitted. Reference numeral 7 denotes a delay circuit which outputs delayed_ecc_end obtained by delaying the end signal ecc_end from the error correction circuit 1 to the RS flip-flop 5.
[0021]
In this embodiment, the supply of ecc_clk is started by ecc_start and is stopped by ecc_end. The error correction circuit 1 receives the start signal delayed_ecc_start after the supply of the ecc_clk, outputs the end signal ecc_end, and stops the supply of the ecc_clk with a delay of the delay of the delay circuit 7.
[0022]
Next, the operation of the data processing circuit according to the second embodiment of the present invention will be described with reference to a timing chart. FIG. 4 is a timing chart showing the supply and stop of the operation clock ecc_clk of the error correction circuit 1. When the error correction start signal ecc_start is output from the RAM controller 2, the clock on / off control signal ecc_clken 2 becomes “H” and the error correction circuit 1 is supplied with ecc_clk. After ecc_clk is supplied, delayed_ecc_start is input to the error correction circuit 1 to start error correction.
[0023]
When the error correction is completed, an end signal ecc_end is output and the operation is stopped. After the ecc_end is output, the delayed_ecc_end is output, the ecc_clken2 becomes “L”, and the supply of the ecc_clk to the error correction circuit 1 is stopped.
[0024]
As described above, in the second embodiment of the present invention, the clock is automatically supplied only during the execution of the data processing as in the first embodiment, and the supply of the clock is stopped except during the execution of the data processing, thereby saving power. It becomes. Further, since the start signal can be received after the clock is supplied, the data processing operation can be reliably started. Further, in the second embodiment, since the clock is supplied for the delay of the delay circuit even after the end signal is output, even if a shift register or the like is provided and several clocks are required for the end processing, the operation can be reliably stopped. it can.
[0025]
FIG. 5 is a block diagram showing a data processing device according to a third embodiment of the present invention. The description of the same parts as in the first embodiment is omitted. Reference numeral 8 denotes a delay circuit that outputs an ecc_reset obtained by delaying the error correction start signal ecc_start from the RAM controller 2 to the error correction circuit 1 as a circuit reset. Reference numeral 9 denotes a delay circuit which outputs delayed_ecc_start obtained by further delaying ecc_reset to the error correction circuit 1.
[0026]
In this embodiment, the error correction circuit 1 receives the circuit reset ecc_reset after the supply of the ecc_clk, then receives the start signal delayed_ecc_start, outputs the end signal ecc_end, and then stops the supply of the ecc_clk.
[0027]
Next, the operation of the data processing circuit according to the third embodiment of the present invention will be described with reference to a timing chart. FIG. 6 is a timing chart showing the supply and stop of the operation clock ecc_clk of the error correction circuit 1. When the error correction start signal ecc_start is output from the RAM controller 2, the clock on / off control signal ecc_clken 3 becomes “H” and the error correction circuit 1 is supplied with ecc_clk. After the ecc_clk is supplied, the ecc_reset is input to the error correction circuit 1 to reset the circuit, and then the activation signal delayed_ecc_start is input to the error correction circuit 1 to start error correction.
[0028]
When the error correction is completed, an end signal ecc_end is output and the operation is stopped. When ecc_end is output, ecc_clken3 becomes “L”, and supply of ecc_clk to the error correction circuit 1 is stopped.
[0029]
As described above, in the third embodiment of the present invention, as in the first embodiment, the clock is automatically supplied only during the execution of the data processing, and the power supply is stopped by stopping the clock supply except during the execution of the data processing. It becomes. Furthermore, in the third embodiment, a reset is input after the clock is supplied, and a start signal is received after that, so that the data processing operation can be reliably started from the initial state after the reset.
[0030]
FIG. 7 is a block diagram showing a data processing device according to a fourth embodiment of the present invention. The description of the same parts as in the first embodiment is omitted. The RS flip-flop 5 sets the clock switching signal ecc_clksel to “H” by ecc_start and “L” by ecc_end. Reference numeral 10 denotes a frequency dividing circuit, which divides the frequency of the clock ecc_clk output to the error correction circuit 1 by 1 / n (n: natural number). Reference numeral 11 denotes a multiplexer, which switches the clock supplied to the error correction circuit 1 between clock and clock / n by using ecc_clksel.
[0031]
In the present embodiment, the frequency of ecc_clk is released by ecc_start, and the frequency is set by ecc_end. The error correction circuit 1 receives the activation signal delayed_ecc_start after the frequency division of the ecc_clk is released, outputs the end signal ecc_end, and sets the frequency division of the ecc_clk.
[0032]
Next, the operation of the data processing circuit according to the fourth embodiment of the present invention will be described with reference to a timing chart. FIG. 8 is a timing chart showing frequency division and release of the operation clock ecc_clk of the error correction circuit 1. When the error correction start signal ecc_start is output from the RAM controller 2, the clock switching signal ecc_clksel becomes “H”, and the clock whose frequency has been released is supplied to the error correction circuit 1. After the clock whose frequency has been released is supplied, the activation signal delayed_ecc_start is input to the error correction circuit 1 to start error correction.
[0033]
When the error correction is completed, an end signal ecc_end is output and the operation is stopped. When ecc_end is output, ecc_clksel becomes “L”, and the frequency-divided clock is supplied to the error correction circuit 1.
[0034]
As described above, in the fourth embodiment of the present invention, the clock is automatically de-divided and supplied only during the execution of the data processing, and the power is saved by supplying the divided clock except during the execution of the data processing. Become. Further, since the start signal can be received after the clock is released from the frequency division, the data processing operation can be reliably started.
[0035]
FIG. 9 is a block diagram showing a data processing device according to a fifth embodiment of the present invention. The description of the same parts as in the fourth embodiment is omitted. Reference numeral 7 denotes a delay circuit which outputs delayed_ecc_end obtained by delaying the end signal ecc_end from the error correction circuit 1 to the RS flip-flop 5.
[0036]
In this embodiment, the RS flip-flop 5 sets the clock switching signal ecc_clksel2 to "H" by ecc_start and to "L" by delayed_ecc_end. The multiplexer 11 switches the clock ecc_clk to be supplied to the error correction circuit 1 to clock and clock / n by ecc_clksel2. The frequency of ecc_clk is released by ecc_start, and the frequency is set by delayed_ecc_end. The error correction circuit 1 receives the activation signal delayed_ecc_start after the frequency division of the ecc_clk is released, and outputs the end signal ecc_end.
[0037]
Next, the operation of the data processing circuit according to the fifth embodiment of the present invention will be described with reference to a timing chart. FIG. 10 is a timing chart showing frequency division and cancellation of the operation clock ecc_clk of the error correction circuit 1. When the error correction start signal ecc_start is output from the RAM controller 2, the clock switching signal ecc_clksel2 becomes “H”, and the clock whose frequency has been released is supplied to the error correction circuit 1. After the clock whose frequency has been released is supplied, the activation signal delayed_ecc_start is input to the error correction circuit 1 to start error correction. When the error correction is completed, an end signal ecc_end is output and the operation is stopped. When ecc_end is output, ecc_clksel2 becomes “L” due to delayed_ecc_end delayed by the delay of the delay circuit 7, and the frequency-divided clock is supplied to the error correction circuit 1.
[0038]
As described above, in the fifth embodiment of the present invention, similarly to the fourth embodiment, the clock is automatically de-divided and supplied only during the execution of the data processing, and the divided clock is supplied except during the execution of the data processing. By doing so, power can be saved. Further, since the start signal can be received after the clock is released from the frequency division, the data processing operation can be reliably started. Furthermore, in the fifth embodiment, even after the end signal is output, the clock is frequency-divided by the delay of the delay circuit, so that even if a shift register or the like is provided and several clocks are required for the end processing, it is ensured. Can be stopped.
[0039]
FIG. 11 is a block diagram showing a data processing device according to a sixth embodiment of the present invention. The description of the same parts as in the fourth embodiment is omitted.
[0040]
In this embodiment, when activated, the error correction circuit 1 outputs a data transfer request ecc_dreq to the RAM controller 2. When receiving the ecc_dreq, the RAM controller 2 adjusts the DRAM access request, outputs a data transfer acknowledge ecc_dack, and performs data transfer by ecc_data. The RS flip-flop 5 sets the clock switching signal ecc_clksel3 to “H” by ecc_dreq and to “L” by ecc_end. The multiplexer 11 switches the clock ecc_clk to be supplied to the error correction circuit 1 to clock and clock / n using ecc_clksel3. Note that it takes several clocks from the input of the ecc_dreq to the output of the ecc_dack of the normal RAM controller 2, so that the clock can be switched in the meantime. And good. The error correction circuit 1 receives the data transfer acknowledgment ecc_dack after the frequency division of the ecc_clk is released, outputs the end signal ecc_end, and sets the frequency division of the ecc_clk.
[0041]
Next, clock division and release of the clock of the data processing device according to the sixth embodiment of the present invention will be described with reference to a timing chart. FIG. 12 is a timing chart showing frequency division and cancellation of the operation clock ecc_clk of the error correction circuit 1. The clock switching signal ecc_clksel3 becomes “H” by the data transfer request ecc_dreq output from the error correction circuit 1, and the frequency-divided released ecc_clk is supplied to the error correction circuit 1. When the error correction is completed, an end signal ecc_end is output and the operation is stopped. When ecc_end is output, ecc_clksel3 becomes “L”, and the error-corrected circuit 1 is supplied with the frequency-divided ecc_clk.
[0042]
As described above, in the sixth embodiment of the present invention, similarly to the fourth embodiment, the clock is automatically de-divided and supplied only during the execution of the data processing, and the divided clock is supplied except during the execution of the data processing. By doing so, power can be saved. Further, in the sixth embodiment, it is not particularly necessary to use the data processing activation signal for releasing the clock frequency division as in the fourth embodiment, and the clock frequency division can be released if there is a data transfer request.
[0043]
FIG. 13 is a block diagram showing a data processing device according to a seventh embodiment of the present invention. The description of the same parts as in the second embodiment is omitted. Reference numeral 12 denotes an error correction code adding circuit which inputs / outputs data ecc_data from / to the DRAM 3 via the RAM controller 13 and adds an error correction code to data on the DRAM 3. The error correction code addition circuit 12 is activated by the delayed_ecc_start delayed by the delay circuit 4 from the error correction code addition activation signal ecc_start from the RAM controller 13, and is stopped by the end signal ecc_end2. The operation clock of the error correction code adding circuit 12 is ecc_clk. A RAM controller 13 adjusts a DRAM access request from the error correction code adding circuit 12 and other circuits not shown in the figure, and controls data read / write of the DRAM 3. Further, the RAM controller 13 outputs an end signal ecc_end2 to the error correction code addition circuit 12 and the delay circuit 7 when the error correction code addition is completed. The delay circuit 7 outputs to the RS flip-flop 5 delayed_ecc_end2 obtained by delaying the error correction code addition end signal ecc_end2 from the RAM controller 13. The RS flip-flop 5 sets the clock on / off control signal ecc_clken4 to “H” by ecc_start and to “L” by delayed_ecc_end2.
[0044]
As described above, in the seventh embodiment of the present invention, the clock is automatically supplied only during the execution of the data processing as in the second embodiment, and the supply of the clock is stopped except during the execution of the data processing, thereby saving power. It becomes. In addition, since the start signal can be received after the clock is supplied, the data processing operation can be reliably started, and the clock is supplied for the delay of the delay circuit even after the end signal is output. Therefore, even when several clocks are required for the end processing, the operation can be reliably stopped. Further, in the seventh embodiment, the block does not need to output the data processing end signal by itself in order to stop the clock supply as in the second embodiment. Can be stopped.
[0045]
In each of the above embodiments, the case where the present invention is applied to a data processing device including an error correction circuit or an error correction code adding circuit has been described as an example, but the present invention is not limited to the above embodiments. However, various modifications can be made without departing from the spirit of the invention. That is, the supply of the clock to the signal processing circuit is started based on the data processing start signal corresponding to the error correction start signal in the present invention, and the signal processing circuit performs the processing based on the delayed data processing start signal. The same effect as that of the above embodiment can be obtained even when the configuration for starting the process is started.
[0046]
In each of the above embodiments, a D flip-flop or a shift register combining the same is generally used as the delay circuit, but an analog delay may be used. In addition, a JK flip-flop may be used as the RS flip-flop 5, and any circuit can be used as long as ecc_clken can be set to “H” by ecc_start and set to “L” by ecc_end.
[0047]
【The invention's effect】
According to the configuration described above, the clock is automatically supplied only during the execution of the data processing, and the supply of the clock is stopped except during the execution of the data processing, thereby saving power. Further, since the start signal can be received after the clock is supplied, the data processing operation can be reliably started. Furthermore, since the clock is stopped after outputting the end signal, the data processing operation can be surely ended.
[0048]
In other words, the clock is automatically supplied only during the execution of data processing in each circuit, and the supply of the clock to the circuit is stopped except during the execution of the data processing, whereby power saving of the entire device can be achieved, and At times, the time during which the user can use the device can be extended.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a data processing device according to a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of the data processing device according to the first embodiment of the present invention.
FIG. 3 is a block diagram showing a data processing device according to a second embodiment of the present invention.
FIG. 4 is a timing chart for explaining the operation of the data processing device according to the second embodiment of the present invention.
FIG. 5 is a block diagram showing a data processing device according to a third embodiment of the present invention.
FIG. 6 is a timing chart for explaining the operation of the data processing device according to the third embodiment of the present invention.
FIG. 7 is a block diagram showing a data processing device according to a fourth embodiment of the present invention.
FIG. 8 is a timing chart for explaining the operation of the data processing device according to the fourth embodiment of the present invention.
FIG. 9 is a block diagram showing a data processing device according to a fifth embodiment of the present invention.
FIG. 10 is a timing chart for explaining the operation of the data processing device according to the fifth embodiment of the present invention.
FIG. 11 is a block diagram showing a data processing device according to a sixth embodiment of the present invention.
FIG. 12 is a timing chart illustrating the operation of the data processing device according to the sixth embodiment of the present invention.
FIG. 13 is a block diagram showing a data processing device according to a seventh embodiment of the present invention.
FIG. 14 is a block diagram showing an optical disc reproducing apparatus including the data processing apparatus according to the first embodiment of the present invention.
REFERENCE SIGNS LIST 1 error correction circuit 2 RAM controller 3 DRAM 4 delay circuit 5 RS flip-flop 6 clock gate 7 delay circuit 8 delay circuit 9 delay circuit 10 frequency division Circuit, 11 multiplexer, 12 error correction code adding circuit, 13 RAM controller, 14 optical disk, 15 optical pickup, 16 preamplifier, 17 demodulation circuit, 18 descramble circuit, 19 host interface

Claims (11)

A data processing circuit that starts data processing based on the data processing start signal, and outputs a data processing end signal when certain data processing is completed;
A clock control circuit that starts supplying a clock to the data processing circuit by the data processing start signal;
A control circuit for controlling the data processing circuit and the clock control circuit,
A delay circuit for delaying the data processing start signal output to the data processing circuit,
A data processing device, wherein a data processing start signal is supplied after supplying a clock to the data processing circuit. A data processing circuit that starts data processing based on the data processing start signal, and outputs a data processing end signal when certain data processing is completed;
A clock control circuit that starts clock supply to the data processing circuit by the data processing start signal, and stops clock supply to the data processing circuit by the data processing end signal;
A control circuit for controlling the data processing circuit and the clock control circuit,
A delay circuit for delaying a data processing end signal output to the clock control circuit,
A data processing apparatus, wherein a clock supply is stopped after a data processing end signal is supplied to the control circuit. A data processing circuit that starts data processing based on the data processing start signal, and outputs a data processing end signal when certain data processing is completed;
A clock control circuit that starts clock supply to the data processing circuit by the data processing start signal, and stops clock supply to the data processing circuit by the data processing end signal;
A control circuit for controlling the data processing circuit and the clock control circuit,
A first delay circuit that delays the data processing start signal output to the data processing circuit;
A second delay circuit that delays a data processing end signal output to the clock control circuit;
A data processing circuit that supplies a data processing start signal after supplying a clock to the data processing circuit, and stops the clock after supplying a data processing end signal. A data processing circuit that starts data processing based on the data processing start signal, and outputs a data processing end signal when certain data processing is completed;
A clock control circuit that starts supplying a clock to the data processing circuit by the data processing start signal;
A first delay circuit that delays the data processing start signal and outputs the data processing start signal as a reset signal to the data processing circuit;
A second delay circuit for further delaying the data processing start signal delayed by the first delay circuit and outputting the data processing start signal to the data processing circuit,
A data processing apparatus, comprising: supplying a reset signal after supplying a clock to the data processing circuit, and then supplying a data processing start signal. A data processing circuit that starts data processing based on the data processing start signal, and outputs a data processing end signal when certain data processing is completed;
A clock division control circuit that starts frequency division of a clock supplied to the data processing circuit by the data processing end signal and cancels frequency division of a clock supplied to the data processing circuit by the data processing start signal;
A delay circuit for delaying the data processing start signal output to the data processing circuit,
A data processing apparatus, wherein a data processing start signal is supplied to the data processing circuit after supplying a non-divided clock to the data processing circuit. A data processing circuit that starts data processing based on the data processing start signal, and outputs a data processing end signal when certain data processing is completed;
A clock division control circuit that starts frequency division of a clock supplied to the data processing circuit by the data processing end signal and cancels frequency division of a clock supplied to the data processing circuit by the data processing start signal;
A first delay circuit that delays the data processing start signal output to the data processing circuit;
A second delay circuit for delaying a data processing end signal output to the clock frequency division control circuit,
A data processing apparatus comprising: supplying a data processing start signal after supplying a clock that does not divide to the data processing circuit; and supplying a data processing end signal to divide the clock. A data processing circuit that starts data processing by outputting a data transfer request signal, and outputs a data processing end signal when certain data processing is completed;
A clock frequency division control circuit that starts frequency division of a clock supplied to the data processing circuit by the data processing end signal and cancels frequency division of a clock supplied to the data processing circuit by the data transfer request signal. And
A data processing apparatus characterized in that when data transfer is started, a clock is supplied to the data processing circuit without division, and when data transfer is completed, the clock is divided and supplied. A data processing circuit that starts data processing based on the data processing start signal and performs processing until a data processing end signal is input;
A clock control circuit that starts clock supply to the data processing circuit by the data processing start signal, and stops clock supply to the data processing circuit by the data processing end signal;
A first delay circuit that delays the data processing start signal output to the data processing circuit;
A second delay circuit for delaying the data processing end signal,
A data processing apparatus comprising: supplying a data processing start signal after supplying a clock to the data processing circuit; and stopping the clock after supplying a data processing end signal. Data processing means for performing data processing based on a data processing start signal and a clock,
Control means for supplying the data processing start signal;
Clock supply means for supplying the clock based on the data processing start signal;
Delay means for performing a delay process on the data processing start signal;
A data processing device comprising:
The data processing apparatus according to claim 1, wherein said data processing means starts data processing based on a data processing start signal delayed by said delay means. A data processing unit that performs data processing based on the data processing start signal and the clock, and outputs a data processing end signal when the data processing ends.
Control means for supplying the data processing start signal;
A clock supply unit that starts supplying the clock based on the data processing start signal and stops supplying the clock based on the data processing end signal;
Delay means for performing delay processing on the data processing end signal;
A data processing device comprising:
The data processing apparatus according to claim 1, wherein the clock supply unit stops the clock based on a data processing end signal delayed by the delay unit. A data processing method of a data processing unit that performs data processing based on a data processing start signal and a clock,
A data processing method comprising: supplying a clock to the data processing means based on the data processing start signal; and starting data processing based on the data processing start signal.

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