JP2004234269A - Data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To divide an interface for managing interconnection between a PCI bus and peripheral devices into a plurality of blocks, and limit supply of operating clocks to unused blocks. <P>SOLUTION: OR circuits 16 each produce the logical sum of a STOP_CLK signal 15 and a clock from a clock oscillator to control a start/stop of clock transmission. Specifically, when the STOP_CLK signal 15 is High, the logical sum output is High to stop the clock. An initiator control part itself can determine whether or not to start its own access, and thus determines the timing to set the STOP_CLK signal 15 to Low. After a completion signal of data transfer on the PCI bus is detected, the STOP_CLK signal 15 is set to High again to stop the clock. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data transfer device that transfers data between various devices used by a computer via a bus line, and in particular, directly transfers data between devices without a CPU (Central Processing Unit). The present invention relates to a data transfer device equipped with a plurality of DMA controllers for controlling DMA (Direct Memory Access) transfer on a mother board.
[0002]
[Prior art]
2. Description of the Related Art In recent years, when transferring data with a large amount of information, for example, image data, a DMA (Direct Memory Access) transfer method for directly transferring data between devices without going through a CPU (Central Processing Unit). The number of devices adopting is increasing.
Further, when performing such a DMA transfer, it is possible to cope with a wide band from a low speed to a high speed, so that a PCI (Peripheral Component Interconnect) bus is used in various systems.
This PCI bus enables continuous data transfer at high speed by performing burst access.
[0003]
Generally, a data transfer device that performs such data transfer requires a buffer for efficiently processing data. The capacity of this buffer depends on the data transfer speed when using the PCI bus. Therefore, in a data transfer device requiring high speed, the capacity of the buffer tends to be large.
As the capacity of the buffer provided in the data transfer device increases, the power consumption of the data transfer device necessarily increases.
Conventionally, various techniques for reducing power consumption in a data transfer device have been disclosed, including the following patent documents.
[Patent Document 1]
JP-A-11-053049
[Patent Document 2]
JP-A-2002-007316
[0004]
Patent Literature 1 discloses a technique of dynamically controlling a PCI clock during system operation to reduce the power consumption of the system.
Patent Literature 2 discloses a technique that monitors transactions on a PCI bus and stops the PCI clock when the PCI bus is in an idle state to reduce the power consumption of the system.
[0005]
[Problems to be solved by the invention]
However, in the techniques for reducing the power consumption of the systems described in Patent Documents 1 and 2, since the clock generation circuit for generating the PCI clock is directly controlled, the connected peripheral devices are controlled. It was not possible to control the PCI clock for each circuit.
Therefore, the present invention divides an interface for managing the interconnection between the PCI bus and peripheral devices into a plurality of blocks without requiring a complicated configuration, and restricts the supply of an operation clock to unused blocks. Accordingly, it is an object to provide a data transfer device capable of reducing power consumption.
[0006]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a data transfer device for transmitting and receiving data between devices connected by using a PCI (Peripheral Component Interconnect) bus, wherein a plurality of devices for managing interconnection between the PCI bus and the device are provided. An interface divided into blocks, and a clock supply device for supplying an operation clock for controlling the interface, wherein the clock supply device has the same phase, frequency, and is synchronized with the operation clock. Is supplied to each of the interfaces divided into the plurality of blocks to achieve the above object.
[0007]
According to a second aspect of the present invention, in the first aspect of the present invention, a clock switching unit that switches between supply and stop of the operation clock is provided between the clock supply device and the interface divided into the plurality of blocks. The purpose is achieved by providing.
According to a third aspect of the present invention, in the second aspect of the invention, the clock switching unit stops supplying the operation clock to an idle interface among the plurality of interfaces divided into the plurality of blocks. Thereby, the above-mentioned object is achieved.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to FIGS.
FIG. 1 is a diagram showing a schematic configuration of a data transfer device according to the present embodiment.
As shown in FIG. 1, the data transfer device includes a PCI (Peripheral Component Interconnect) bus 1, a clock oscillator 2, a basic block 3, an initiator user control unit 4, a CPU (central processing unit) 5, a memory 6, an IO It comprises an (input / output) device 7, a CPU I / F (interface) 8, a memory I / F 9, an IO I / F 10, and targets 11 to 14.
[0009]
Here, the function of each unit constituting the data transfer device will be described.
The PCI bus 1 is a 32-bit bus used as a standard for an expansion bus of a personal computer compatible machine, for which a standard has been established in PCI / SIG (Special / Interest / Group).
The clock oscillator 2 oscillates a clock (operating frequency) which is a frequency of a reference signal for controlling the operation of the computer.
The basic block 3 is a control unit for controlling the PCI bus 1, and includes an initiator control unit 3a, a target control unit 3b, and a PCI bus I / F 3c.
[0010]
The initiator user control unit 4 receives a command from the CPU 5 and performs an interface for accessing the PCI bus 1.
The CPU 5 is a central processing unit that controls input / output devices to receive data, performs calculations using the data, and stores and outputs results.
The memory 6 is a storage device that can temporarily store data and programs used in the computer and can retrieve the data and programs when necessary. The memory 6 includes a main storage device and an auxiliary storage device such as a hard disk device. The main storage device includes a readable / writable RAM (random access memory) and a read-only ROM (read only memory).
The IO device 7 is an input / output device that can be used in a computer. The input device includes a keyboard, a mouse, a scanner, and a digital camera. The output device includes a display, a printer, and a speaker.
The CPU I / F 8 is an interface for mutually connecting the initiator user control unit 4 and the CPU 5.
[0011]
The memory I / F 9 is an interface for interconnecting the memory 6 and the targets 11 to 12.
The IO I / F 10 is an interface for mutually connecting the IO device 7 and the targets 13 and 14.
The targets 11 to 14 are control circuits provided for each base address set by the PCI bus 1. The PCI bus 1 can set eleven base addresses. Further, the target control unit 3b outputs a BARx_HIT signal indicating which base address of each base address has been accessed.
In the present embodiment, as shown in FIG. 1, a memory 6 is connected to base addresses 0 and 1 via a memory I / F 9, and base addresses 2 and 3 are connected via an IO I / F 10. The IO device 7 is connected.
[0012]
Next, the operation of the data transfer device configured as described above will be described. In the present embodiment, the clock oscillator 2 supplies a synchronized clock having the same phase and frequency to each of the initiator control unit 3a, the target control unit 3b, the PCI bus I / F 3c, and the targets 11 to 14.
Even in the configuration in which the control block is finely divided in this way, by distributing the synchronized clocks, control can be performed in the same manner as when the control block is not divided.
[0013]
FIG. 2 is a diagram showing a schematic configuration of a data transfer device provided with a logic circuit according to the present embodiment. In addition, the symbol of the part which overlaps with FIG. 1 is abbreviate | omitted.
In the data transfer device according to the present embodiment, as shown in FIG. 2, a STOP_CLK signal 15 for stopping a clock is provided, and an initiator control unit 3a, a target control unit 3b, and a PCI bus to which a clock of a clock oscillator 2 is sent. An OR circuit 16 for performing a logical sum operation is provided at a stage preceding the I / F 3c and the targets 11 to 14. The OR circuit 16 and the STOP_CLK signal 15 are used to configure a clock on / off switching circuit.
[0014]
Next, using the STOP_CLK signal 15 and the OR circuit 16, the start / stop of clock transmission to each block of the initiator control unit 3a, the target control unit 3b, the PCI bus I / F 3c, and the targets 11 to 14 is controlled. The method will be described.
The OR of the STOP_CLK signal 15 and the clock of the clock oscillator 2 in the OR circuit 16 controls start / stop of clock transmission.
Specifically, when the STOP_CLK signal 15 is high (or 1), the output of the logical sum becomes high, and the clock stops. The timing at which the STOP_CLK signal 15 is made high differs between the initiator control unit 3a and the targets 11 to 14.
Since the initiator control unit 3a can determine whether or not to start the access by itself, it determines the timing and sets the STOP_CLK signal 15 to low (or 0). Then, after detecting the data transfer completion signal of the PCI bus 1, the STOP_CLK signal 15 is set to high again to stop the clock.
[0015]
On the other hand, the targets 11 to 14 first decode which base address the target control unit 3b has accessed, and outputs a high signal to one of the BARx_HIT signals.
Then, the targets 11 to 14, which have received the high signal of the BARx_HIT signal, change the STOP_CLK signal 15 to low and operate (start) the clock. As a result, the targets 11 to 14 can operate the clock only when they are accessed and their base addresses are accessed.
[0016]
FIG. 3 is a diagram showing a clock operation state of each block when PCI access is performed using the data transfer device according to the present embodiment.
Here, a clock output to the PCI bus 1 is always supplied as an Output CLK signal in consideration of access between other PCI devices.
First, a case of performing an initiator operation (start operation) will be described.
As shown in FIG. 3, the clock (Initiator CLK) supplied to the initiator control unit 3a operates by setting the STOP_CLK signal 15 to the release setting, that is, to the low level.
Then, upon detecting that the initiator operation has been completed, the initiator control unit 3a sets the STOP_CLK signal 15 to high, and stops the Initiator CLK.
[0017]
When the target control unit 3b detects a target access to the base address 0, the clock (Target0 CLK) supplied to the target 11 operates.
Then, upon detecting that this access has been completed, the target 11 sets the STOP_CLK signal 15 to high and stops the clock.
In the case of accessing the base address 1 and the base address 2, the clock supplied to the target 12 (Target1 CLK) and the clock supplied to the target 13 (Target2 CLK) operate in the same manner. ing.
[0018]
As shown in FIG. 3, while the clock to the location where the access is detected is operating, the clock to the location where the access is not detected is stopped.
As shown in the bus idle state 17, all internal clocks other than the output clock are stopped while the PCI bus 1 is idle when data transfer is not being performed. When the target controller 3b detects a target access to the base address 3 during the bus idle state 17, only the clock (Target3 CLK) supplied to the target 14 operates.
In this embodiment, not only the clock is received from the clock oscillator 2 and this clock is output to the PCI bus 1 but also this clock is used as an internal operation clock. 1, a PCI clock may be received, and the received PCI clock may be used as an internal clock.
[0019]
According to the present embodiment, by dividing the internal circuit and supplying clocks having the same phase, it is possible to systematically classify the circuit into a circuit capable of stopping the clock and other circuits, thereby further reducing consumption. Power can be easily reduced.
Further, according to the present embodiment, since the divided circuits can individually stop the clock, the effect of reducing power consumption can be obtained.
Further, according to the present embodiment, the clock can be stopped even when the PCI bus 1 is not in the idle state, so that the power consumption can be further reduced.
[0020]
【The invention's effect】
According to the first aspect of the present invention, it is possible to control the operation clock for each block by supplying the synchronized operation clock having the same phase and frequency to each of the interfaces divided into a plurality of blocks. it can.
According to the second aspect of the present invention, the operation clock can be stopped for each block by including the clock switching means for switching between supply and stop of the supply of the operation clock.
According to the third aspect of the present invention, the power consumption of the data transfer device is reduced by stopping the supply of the operation clock to the idle interface among the interfaces divided into the plurality of blocks. be able to.
[Brief description of the drawings]
FIG. 1 is a diagram showing a schematic configuration of a data transfer device according to the present embodiment.
FIG. 2 is a diagram showing a schematic configuration of a data transfer device provided with a logic circuit according to the present embodiment.
FIG. 3 is a diagram showing a clock operation state of each block when a PCI access is performed using the data transfer device according to the present embodiment.
[Explanation of symbols]
1 PCI bus 2 Clock oscillator 3 Basic block 3a Initiator control unit 3b Target control unit 3c PCI bus I / F
4 Initiator user control unit 5 CPU
6 Memory 7 IO device 8 CPU I / F
9 Memory I / F
10 IOI / F
11 to 14 target 15 STOP_CLK signal 16 OR circuit 17 bus idle state

Claims (3)

In a data transfer device for transmitting and receiving data between devices connected using a PCI (Peripheral Component Interconnect) bus,
An interface divided into a plurality of blocks for managing interconnection between the PCI bus and the device;
A clock supply device that supplies an operation clock for controlling the interface,
The data transfer device, wherein the clock supply device supplies the operation clocks having the same phase and frequency and being synchronized to each of the interfaces divided into the plurality of blocks. 2. The data transfer device according to claim 1, further comprising clock switching means for switching between supply and stop of the supply of the operation clock between the clock supply device and the interface divided into the plurality of blocks. 3. The data transfer device according to claim 2, wherein the clock switching unit stops supplying the operation clock to an idle interface among the interfaces divided into the plurality of blocks.

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