JP6635696B2 - Information processing apparatus and control method - Google Patents

Description

  The present invention relates to an information processing apparatus having a multi-chip and a start-up method, and in particular, in a configuration in which at least three or more integrated circuit chips are connected, distribution of a program from one integrated circuit chip to another integrated circuit chip , And initialization of the integrated circuit chip.

  2. Description of the Related Art In recent years, as devices become more sophisticated, the number of cases where a device is configured by a plurality of integrated circuit chips (hereinafter, also referred to as “chips”) (multi-chip configuration) has increased. These chips required a ROM for storing programs and a RAM for temporarily storing data being processed. On the other hand, in order to reduce the number of components constituting the apparatus and reduce costs, a method has been proposed in which a ROM is provided only on a specific chip and a program is transferred from that chip to another chip.

  However, if the transfer and initialization of the program are performed sequentially from one chip, it takes time to start the initialization of the entire system. Therefore, after transferring and initializing a program from one chip to two or more appropriate chips, the initialized chips initialize the remaining chips in parallel, so that the system startup time is reduced. A multiprocessor system has been proposed to speed up the process (Patent Document 1).

JP 2000-339284 A

  However, there is a difference in the initialization time of the chip depending on the use purpose and the function. For this reason, depending on the order of initialization of a plurality of chips, the system startup time may not be reduced.

  An object of the present invention is to reduce the time required for initialization by starting initialization with priority from a specific chip.

An information processing apparatus according to the present invention for solving the above problems is an information processing apparatus in which three or more chips including at least a first chip, a second chip, and a third chip are connected in series,
At least a first chip of the attached chip to the series includes specifying means for specifying a priority chip initialization, and a control means for the initialization of the chip specified by the specifying means, the When the specifying means specifies the third chip as a chip that has a higher priority for the initialization, the control means controls the second chip before transferring the initialization program for the second chip to the second chip. Transferring a program for initializing the third chip to the three chips,
The third chip is initialized by a program for initializing the third chip .

  According to the present invention, it is possible to perform initialization from a chip where initialization should be performed with priority. As a result, the required initialization time can be reduced.

1 is a block diagram illustrating a configuration of a multi-chip system according to a first embodiment. 4 is a flowchart illustrating a control method of the multi-chip system according to the first embodiment. FIG. 9 is a block diagram illustrating a configuration of a multichip system according to a second embodiment. 9 is a control method flowchart of the multichip system according to the second embodiment. FIG. 11 is a block diagram illustrating a configuration of a multichip system according to a third embodiment. FIG. 11 is an explanatory diagram showing a pattern of a chip initialization order according to a third embodiment. FIG. 14 is a block diagram illustrating a configuration of a multichip system according to a fourth embodiment. 15 is a flowchart for determining a chip initialization order of the multi-chip system according to the fourth embodiment. FIG. 14 is a block diagram illustrating a configuration of a multichip system according to a fifth embodiment. 15 is a flowchart for determining the order of chip initialization of the multi-chip system according to the fifth embodiment.

  An embodiment for carrying out the invention will be described with reference to the drawings. In addition, the relative arrangement of each component of the apparatus used in the following embodiment, the apparatus shape, and the like are examples, and are not limited to the following.

(Embodiment 1)
FIG. 1 is a block diagram illustrating an image processing apparatus as an example of the information processing apparatus according to the present embodiment. In the present embodiment, a method for initializing a multi-chip system in an image processing apparatus based on initialization order information stored in a ROM connected to a master chip among three chips connected in series will be described. . In the present embodiment, the information processing apparatus is an image processing apparatus having a printing function. However, the present invention is not limited to this, and may be any apparatus in which three or more chips are connected in series.

  As shown in FIG. 1, the image processing apparatus 100 has three chips (chip 110, chip 120, and chip 130) connected in series. That is, in the image processing apparatus 100, the chip 110, the chip 120, and the chip 130 are connected in a peer-to-peer connection. Hereinafter, in the image processing apparatus 100, a chip configuration including the chip 110, the chip 120, and the chip 130 is also referred to as a “multi-chip system”.

  The image processing apparatus 100 is connected to a host PC 190 operated by a user. Note that the host PC 190 and the image processing apparatus 100 are connected by a host interface 191.

  The image processing apparatus 100 can receive print data from the host PC 190 and generate a printed matter. Note that the image processing apparatus may be a composite printer having an image reading function, a facsimile function, or the like, or may be a copying machine or a plotter.

  The image processing apparatus 100 includes a master chip 110 used as a controller chip, a slave chip 120 used as a print control chip, and a slave chip 130 used as a mechanical drive chip. Here, the master chip is a chip that becomes a master of the multi-chip (three chips in the present embodiment) and starts the initialization of the slave chip. Specifically, the CPU of each chip is activated. Thereby, the CPU reads the program and initializes the chip. Further, in the present embodiment, “initialization of a chip” refers to processing from the start of the chip until the chip becomes operable.

  The chip 110 and the chip 120 are connected by an interface 250 that performs communication. The chip 120 and the chip 130 are connected by an interface 260 that performs communication. The interfaces 250 and 260 are not particularly limited, and include, for example, a PCI Express interface.

In the chip 110, a RAM 210 and a ROM 202 are connected. The ROM 202 stores chip initialization order information.
The chip 120 is connected to the RAM 211 and the printing unit.
In the chip 130, the RAM 221 and the mechanical unit 222 are connected.
The chip 110 has a CPU 111, a RAM controller unit 112, a ROM controller unit 113, an interface unit 115, and a host communication unit 1101, and is connected to each other by an internal bus 118. The host communication unit 1101 is connected to the PC 190 via the host interface 191.

  The CPU 111 controls the image processing apparatus 100 according to a program. The RAM controller 112 is a RAM control unit for reading and writing data from and to the RAM 201. The ROM controller unit 113 is a ROM control unit for reading data from the ROM 202. The interface unit 115 is a communication unit for communicating with the chip 120 via the interface 250. The RAM 201 is a storage unit that stores temporary data such as image data being processed and a transferred program. The ROM 202 is a recording unit that stores a program executed by the CPU 111 and the like. In the present embodiment, the ROM 202 includes chip initialization order information 202a that is information on the order of chips to be initialized.

  Here, the chip initialization order information 202a will be described. In the present embodiment, the chip initialization order information 202a is determined in advance based on the initialization time of each chip, and is stored in the ROM 202. The chip 130, which is a mechanical driving chip, requires time to determine the initial position of the mechanical unit and the like, and thus takes time to initialize. However, in the present embodiment, the chip 130 is arranged as a downstream chip distant from the chip 110 which is the master chip in order to match the mechanical configuration. Therefore, in the present embodiment, first, the initialization order information 202a is set so that the chip 130 performs initialization. That is, the initialization order information 202a is set so that the chip 130 is activated before the chip 120.

  The chip 120 has a CPU 121, a RAM controller 122, a print controller 123, a CPU reset controller 124, and interfaces 125 and 126, and is connected to each other by an internal bus 128.

  The CPU 121 controls the image processing apparatus 101 according to a program. The RAM controller 122 is a RAM control unit for reading and writing data from and to the RAM 211. The print control unit 123 controls the print unit 212. The CPU reset control unit 124 controls the CPU 121 by controlling a CPU reset signal 253 to the CPU 121. The interface unit 125 is a communication unit for communicating with the chip 130 via the interface 260. The interface unit 126 is a communication unit for performing communication with the chip 110 via the interface 250.

  The chip 130 has a CPU 131, a RAM controller 132, a mechanical drive controller 133, a CPU reset controller 134, and an interface 136, and is connected to each other by an internal bus 138.

  The CPU 131 controls the image processing apparatus 101 according to a program. The RAM controller 132 is a RAM control unit for reading and writing data from and to the RAM 221. The mechanical drive control unit 133 controls the mechanical unit 222. The CPU reset control unit 134 controls a CPU reset signal 263 to the CPU 131 to perform reset control of the CPU 131. The interface unit 136 is a communication unit for communicating with the chip 120 via the interface 260.

  Further, the image processing apparatus 100 has a reset IC 300. The reset IC 300 outputs a reset signal 301 output to all components in the chip 110, components other than the CPU in the chip 120, and components other than the CPU in the chip 130, and resets each component. Can be.

  FIG. 2 is a flowchart illustrating a procedure of a control method of the multichip system according to the first embodiment.

  When the power is turned on to the multichip system, the reset IC 300 outputs a reset signal 301 to each chip of the multichip system. More specifically, the reset IC 300 outputs a reset signal 301 to the CPU 111, the RAM controller 112, the ROM controller 113, and the interface 115. Further, the reset IC 300 outputs a reset signal 301 to the reset control unit 124, the RAM controller unit 122, the print control unit 123, the interface unit 125, and the interface unit 126. Further, the reset IC 300 outputs a reset control unit 134, a RAM controller unit 132, a mechanical drive control unit 133, an interface unit 136, and a reset signal 301. As a result, the chip reset of the chip 110, the reset of the chip 120 other than the CPU 121, and the reset of the chip 130 other than the CPU 131 are released.

  In step S501, the CPU 111 reads a program for initializing the chip 110 itself from the ROM 202, writes the program in the RAM 201, and starts initialization of the chip 110. In step S502, the CPU 111 acquires the chip initialization order information 202a from the ROM 202, and specifies the next chip to be initialized. In the present embodiment, the initialization time of the mechanical unit 222 connected to the chip 130 is longer than the initialization time of the printing unit 212 connected to the chip 120. Therefore, the chip initialization order information 202a is stored so that the initialization of the chip 130 is started before the execution of the chip 120. Therefore, the CPU 111 specifies that the chip to be initialized next is the chip 130 based on the chip initialization order information 202a.

  In step S504, the CPU 111 sets predetermined parameters in the interface unit 115 and activates the interface unit 115. This enables connection communication between the interface unit 115 and the interface unit 126. When the interface unit 115 and the interface unit 126 are connected, communication between the chip 110 and the chip 120 is established. That is, it is possible to freely access the memory space of both chips.

  In S506, the CPU 111 sets predetermined parameters in the interface unit 125, and activates the interface unit 125. This enables connection communication between the interface unit 125 and the interface unit 136. When the interface unit 125 and the interface unit 136 are connected, communication between the chip 110 and the chip 130 is established via the chip 120. That is, the chip 110 can freely access the memory space of the chip 130 via the chip 120.

  In step S <b> 507, the CPU 111 reads the program for initializing the chip 130 from the ROM 202 and transfers the program for initializing the chip 130 to the RAM 221 of the chip 130 via the interface 250 and the interface 260. Thereby, the program is stored in the RAM 221 (S532). That is, the CPU 111 causes the RAM 221 of the chip 130 to store a program for initializing the chip 130.

  In step S508, the CPU 111 accesses the CPU reset control unit 134 to release the reset of the CPU 131. Specifically, the CPU 131 is activated by the CPU reset control unit 134 outputting the reset signal 263 in response to the access of the CPU 111 (S533). Thus, the chip 110 and the chip 130 can operate in parallel thereafter.

  After S533, in the chip 130, the program stored in S532 is read from the RAM 221 by the CPU 131 in S534, and the initialization of the chip 130 is started in S535. When the initialization is completed in the chip 120 in S536, the chip 130 transmits an initialization completion notification to the chip 110 (S537).

  After S508, in the chip 110, in S509, the CPU 111 reads the program from the ROM 202, transfers the program for initializing the chip 120 to the RAM 211 of the chip 120, and stores the program in the RAM 211 (S522). That is, the CPU 111 causes the RAM 211 of the chip 120 to store a program for initializing the chip 120. In step S510, the CPU 121 accesses the CPU reset control unit 124 to release the reset of the CPU 121. Specifically, the CPU 121 is activated by the CPU reset control unit 124 outputting the reset signal 253 in response to the access of the CPU 111 (S523). Thus, the chip 110, the chip 120, and the chip 130 can operate in parallel thereafter.

  After S523, in the chip 120, the program is read from the RAM 211 by the CPU 121 in S524, and initialization of the chip 120 is started in S525. When the initialization is completed in the chip 120 in S526, the chip 120 transmits an initialization completion notification to the chip 110 (S527).

  After S510, the chip 110 confirms the completion of the initialization of the chips 120 and 130 in S511. The initialization completion confirmation is performed by determining whether or not an initialization completion notification has been received for each chip (chips 120 and 130). Upon receiving the initialization completion notification from each chip, it is determined that the initialization has been completed in each chip (S512). Upon receiving the initialization completion notification from the chips 120 and 130, it is determined that all the chips have been initialized (S513).

As described above, in the present embodiment, a slave chip to be preferentially initialized is specified based on chip initialization order information, and a slave chip that takes a long time to initialize is preferentially initialized. . As a result, the startup time of the entire system can be reduced.
The initialization time of the chip differs depending on the chip, depending on the use purpose and the function. When starting in the order of chip connection, initialization is performed in order of proximity to the master chip. When a slave chip with a long initialization time is arranged near the master chip, the slave chip with a long initialization time can be preferentially initialized. However, depending on the influence of wiring congestion and the configuration of terminals to be connected, a slave chip having a long initialization time may need to be arranged as a downstream chip over a plurality of chips from the master chip. If a slave chip with a long initialization time is arranged at a position far from the master chip, initialization of the slave chip with a long initialization time is delayed, and the startup time of the entire system is delayed. On the other hand, in the present embodiment, before the chip 120 between the chip 110 and the chip 130 is initialized, communication between the chip 110 and the chip 130 is established, and the program is stored in the RAM 221 for the chip 130 having a long initialization time. Is stored. Therefore, compared with the case where the chip 120 is initialized and the program for initializing the chip 130 is temporarily stored in the RAM 211 for initializing the chip 120 and then stored in the RAM 221 for the chip 130, the program is transferred. The time required to do so can be reduced. When the program for initializing the chip 130 is stored in the RAM 221 for the chip 130, the initialization of the chip 130 is started. As a result, the startup time of the entire system can be shortened.

(Embodiment 2)
In the present embodiment, the chip initialization order is specified by the external terminal. FIG. 3 is a block diagram illustrating a configuration example of the image processing apparatus according to the present embodiment. The same parts as those in FIG. 1 are represented by the same symbols, and the description will be omitted.

  As shown in FIG. 3, the image processing apparatus 100A has three chips (chip 110A, chip 120A, and chip 130A) connected in series. Hereinafter, different parts of FIG. 3 and FIG. 1 will be described.

  The chip 110A is similar to FIG. 1, but the ROM 202 connected to the chip 110A does not include the chip initialization order information 202a.

  The chip 120A has a port control unit 127. The port control unit 127 has an internal register 127a that controls an input from the initialization order setting terminal 401 by controlling a port, and stores input information from the initialization order setting terminal 401. In the present embodiment, the initialization order setting terminal 401 is set to “Low”.

  The chip 130A further has a port control unit 137. The port control unit 137 has an internal register 137a that controls an input from the initialization order setting terminal 402 by controlling a port and stores input information from the initialization order setting terminal 402. In the present embodiment, the initialization order setting terminal 402 is set to “High”.

  FIG. 4 is a flowchart illustrating a procedure of a control method of the multichip system according to the present embodiment.

  When the power is turned on to the multichip system, the reset IC 300 outputs a reset signal 301 to each chip of the multichip system. As a result, the chip reset of the chip 110, the reset of the chip 120 other than the CPU 121, and the reset of the chip 130 other than the CPU 131 are released.

  After the reset by the reset IC 300, the signal of the initialization order setting terminal 401 is input to the chip 120 because the reset of the port control unit 127 has been released in the chip 120 (S611). Then, the signal of the initialization order setting terminal 401 is stored in the internal register 127a of the port control unit 127 as initialization order information of the second chip 120 (S612). Since the initialization order setting terminal 401 is set to "Low", "0" is stored in the internal register 127a.

  After the reset by the reset IC 300, the chip 130 receives the signal of the initialization order setting terminal 402 because the reset of the port control unit 137 has been released (S621). Then, the signal of the initialization order setting terminal 402 is stored in the internal register 137a of the port control unit 137 as the initialization order information of the chip 130 (S622). Since the initialization order setting terminal 402 is set to "High", "1" is stored in the internal register 137a.

  After reset release by the reset IC 300, the chip 110 starts initialization of the chip 110 in S601.

  In step S <b> 602, by setting the interface unit 115 by the CPU 111, connection communication between the interface unit 115 and the interface unit 126 becomes possible. When the interface section 115 and the interface section 126 are connected, the memory space of both chips can be freely accessed. That is, communication between the chip 110 and the chip 120 is established.

  In S603, the CPU 111 reads the internal register 127a and acquires the initialization order information of the chip 120. In step S604, the initialization order information of the read chip 120 is stored in the RAM 201.

  In step S605, the CPU 111 sets the interface unit 125, thereby enabling connection communication between the interface unit 125 and the interface unit 136. When the interface unit 125 and the interface unit 136 are connected to each other, the chip 110 can freely access the memory space of the chip 130 via the chip 120. That is, communication between the chip 110 and the chip 130 is established via the chip 120.

  In S606, the CPU 111 reads the internal register 137a and acquires the initialization order information of the chip 130. In step S607, the initialization order information of the read chip 130 is stored in the RAM 201.

  As a result, the initialization order information of all the chips has been obtained. In step S608, the initialization order of each chip is controlled. The initialization order of each chip is determined based on the initialization order information obtained from each chip, and initialization is performed with priority on the chip having the initialization order information “1”. In the present embodiment, the second initialization order information is “0” and the third initialization order information is “1”, and it is determined that the chip 130 is to be preferentially initialized.

  Steps S507 to S513, S522 to S527, and S532 to S537 are the same as those in FIG.

  In this embodiment, one initialization order setting terminal is provided for each chip. However, the present invention is not limited to this. For example, the number of terminals for setting the initialization order input to one chip may be increased, and the initialization order of a plurality of chips may be set for one chip.

  In the present embodiment, the external terminals for specifying the chip initialization order are provided on the chips 120 and 130. However, the present invention is not limited to this, and the chips to which the external terminals for specifying the chip initialization order are connected are: However, the present invention is not limited to a specific chip. For example, the external terminals may be connected to the chip 110, the external terminals may be connected only to the chip 120, or the external terminals may be connected only to the chip 130. .

  As described above, in the present embodiment, by providing the chip with the external terminal for specifying the initialization order information, the slave which should execute the initialization preferentially based on the initialization order information input from the external terminal is provided. Identify the chip. Then, the initialization of the slave chip which takes a long time for initialization is preferentially performed. As a result, the startup time of the entire system can be reduced.

(Embodiment 3)
In the image processing apparatus according to the present embodiment, four chips are connected in series.

  FIG. 5 is a block diagram illustrating a configuration example of the image processing apparatus according to the present embodiment.

  The same parts as those in FIG.

  As shown in FIG. 5, the image processing apparatus 100B has four chips (chip 110, chip 120, chip 130, and chip 140) connected in series. Hereinafter, different parts of FIG. 5 and FIG. 1 will be described.

  The image processing apparatus 100B is an apparatus that can receive print data from a user and generate a printed material, and can read image data from a medium.

  The interface 270 performs communication between the chip 120 and the chip 140. The interface 280 performs communication between the chip 140 and the chip 130. The chip 140 is connected to the RAM 231 and the scanner unit 232.

  The configurations of the chip 110, the chip 120, and the chip 130 are the same as those in FIG. 1 (Embodiment 1).

  The chip 140 has a CPU 141, a RAM controller 142, a scanner controller 143, a CPU reset controller 144, and interfaces 145 and 146, which are connected to each other by an internal bus 148. The chip 140 is used as a scanner control chip.

  The CPU 141 is a processing execution unit that controls the image processing apparatus 100B according to a program. The RAM controller 142 is a RAM control unit for reading and writing data from and to the RAM 231. The scanner control unit 143 controls the scanner unit 232. The CPU reset control unit 144 controls a CPU reset signal 273 to the CPU 141 to perform reset control of the CPU 141. The interface unit 145 is a communication unit for communicating with the chip 130 via the interface 280. The interface unit 146 is a communication unit for communicating with the chip 120 via the interface 270.

  The reset IC 300 outputs a reset signal to all components in the chip 110, components other than the CPU in the chip 120, components other than the CPU in the chip 140, and components other than the CPU in the chip 130.

  The present embodiment includes four chips, and the chip initialization order is arbitrarily determined by the chip initialization order information 202a stored in the ROM 202, and is not specified in one initialization order. In the present embodiment, the initialization order of the three chips excluding the chip 110 is (4-1)! = 6 types can be arbitrarily selected. FIG. 6 is an explanatory diagram showing a pattern of a chip initialization order according to the present embodiment.

  In the present embodiment, a configuration in which four chips are connected has been described. However, the number of connected chips may be any number.

  As described above, even when n (n: natural number) chips are a multichip system, an arbitrary chip initialization order can be realized. That is, the start-up time of the entire system can be reduced for various multi-chip systems.

(Embodiment 4)
In the present embodiment, an image processing apparatus capable of dynamically changing the initialization order of chips will be described. Here, a detachable unit to which the image processing apparatus can be connected can be connected, and the chip initialization order can be selectively started when the detachable unit is connected and when it is not connected.

  FIG. 7 is a block diagram illustrating a configuration of the multichip system according to the present embodiment. The same parts as those in FIG. As shown in FIG. 7, the image processing apparatus 100C has four chips (chip 110, chip 150, chip 120, and chip 130) connected in series. Hereinafter, different parts of FIG. 7 and FIG. 1 will be described.

  An optional unit can be connected to the image processing apparatus 100C. The option unit unit 290 is, for example, an accelerator unit that speeds up data processing of the image processing apparatus 100C, and is attached to and detached from the image processing apparatus 100C according to the usage of the image processing apparatus 100C.

  The chip 150 is a slave chip used as a data control chip. The interface 251 performs communication between the chip 110 and the chip 150. The interface 261 performs communication between the chip 150 and the chip 120. The chip 150 is connected to the RAM 241. Further, the chip 150 performs communication between the option unit 290 and the chip 150 by an option interface. In this embodiment, when the option unit unit 290 is not connected, it takes time to initialize the chip 130, the chip 120, and the chip 150 in this order. When the option unit 290 is connected, it takes time to initialize the chip 150, the chip 130, and the chip 120 in this order.

  The chip 110C includes an option unit detection unit 293. Further, the option unit detection unit 293 includes an internal register 294. When the option unit unit 290 is connected to the image processing apparatus 100C, the option unit notification signal 292 notifies the chip 110 that the option unit unit 290 has been connected. When the option unit unit 290 is not connected, the option unit detection unit 293 writes “0” into the internal register 294. When the option unit 290 is connected and the option unit notification signal 292 is input to the chip 110 </ b> C, ‘1’ is written to the internal register 294. The ROM 202 connected to the chip 110 does not include the chip initialization order information 202a. As described above, in the present embodiment, the connection information indicating the connection state of the option unit unit 290 is stored in the internal register 294 of the option unit detection unit 293. Then, although details will be described later, the CPU 111 determines the order of initialization based on the connection information indicating the connection state of the option unit unit 290. When the option unit 290 is not connected, the order of initialization is determined in the order of the chip 130, the chip 120, and the chip 150. When the option unit 290 is connected, the order of initialization is determined in the order of the chip 150, the chip 130, and the chip 120.

  The configurations of the chips 120 and 130 are the same as those in FIG.

  The chip 150 includes a CPU 151, a RAM controller 152, a data processor 153, a CPU reset controller 154, interfaces 155, 156, and an optional interface 295, which are connected to each other by an internal bus 158. The CPU 151 controls the image processing device 100C according to a program. The RAM controller 152 is a RAM control unit for reading and writing data from and to the RAM 241. The data processing unit 153 processes image data. The CPU reset control unit 154 controls the CPU reset signal 283 to the CPU 151 to perform reset control of the CPU 151. The interface unit 155 is communication means for communicating with the chip 120 via the interface 261. The interface unit 156 is communication means for communicating with the chip 110 via the interface 251. The option interface unit 295 is a communication unit for communicating with the option unit.

  FIG. 8 is a flowchart for determining the chip initialization order of the multichip system according to the present embodiment.

  When the power is turned on to the multichip system, the reset IC 300 outputs a reset signal 301 to each chip of the multichip system. Thereby, the chip reset of the chip 110, the reset of the chip 120 other than the CPU 121, the reset of the chip 130 other than the CPU 131, and the reset of the chip 150 other than the CPU are released.

  After the reset is released by the reset IC 300, the chip 110 starts to initialize the chip 110 in S701.

  In S702, the CPU 111 reads the value stored in the internal register 294. As a result, in S703, when the value is “0”, the process transits to S704a, and when the value is not “0”, the process transits to S704a.

  In S704a, since the option unit unit 290 is not connected, initialization is started in the order of the chip 130, the chip 120, and the chip 150. In S704b, since the option unit unit 290 is connected, initialization is started in the order of the chip 150, the chip 130, and the chip 120. That is, the order of initialization is determined according to the determination result of S703. In other words, the CPU 111 switches the chip initialization order according to the connection state of the option unit unit 290. The method of initializing each chip is the same as the method described with reference to FIG. 2 and the like, except that the order of initialization is different, and a description thereof will be omitted. As described above, in the present embodiment, there is provided a unit for notifying that a detachable unit is connected, and by switching the initialization order of the chip based on the notified information, the chip can be switched according to the state of the device. Change the initialization priority. Thereby, initialization can be performed in a more appropriate order, and the initialization time of the entire system can be reduced.

(Embodiment 5)
In this embodiment, chip initialization can be started in a variable order based on information input from the outside.

  FIG. 9 is a block diagram illustrating a configuration example of the image processing apparatus according to the present embodiment. As shown in FIG. 9, the image processing apparatus 100D has four chips (chip 110, chip 120, chip 140, and chip 130) connected in series. Hereinafter, the same parts as those in FIG. 5 are represented by the same symbols, and the description will be omitted. Here, different portions between FIG. 9 and FIG. 5 will be described.

  The user interface unit 411 outputs a user interface signal 412 to the chip 110.

  The user interface unit 411 has a plurality of externally operable keys, and outputs a signal corresponding to the pressed key as a user interface signal 412. In the present embodiment, the plurality of keys include a print operation start button, a scanner operation start button, and a stop button.

  The chip 110 has a user interface control unit 119. Then, the user interface control unit 119 has an initialization table 119a. In the initialization table 119a, the order of initialization is set for each key selected in the user interface unit 411.

  The user interface control unit 119 is a control unit that controls the user interface signal 412. In the initialization table 119a, information for specifying the order of chips to start initialization is stored as a table. The initialization order table of the initialization table 119a is selected according to the type of the input user interface signal 412, and the initialization order of the chips is variably determined. Further, the ROM 202 connected to the chip 110 does not include the chip initialization order information 202a. Note that the user interface signal 412 changes according to the type of key selected by the user interface unit 411.

  For example, when the start button of the scanner operation is pressed, initialization of the chip 140 connected to the scanner unit 232 is preferentially performed in order to perform the scanner operation. When the print operation start button is pressed, the chip 130 connected to the mechanical unit 222 is preferentially initialized. As described above, in the present embodiment, it is possible to variably change the chip initialization order according to the operation mode. In other words, the order of initializing the chips is determined according to the function selected by the user. More specifically, the initialization order is determined so that the initialization of the chip required to execute the operation specified by the user is prioritized.

  The configurations of the chip 120, the chip 130, and the chip 140 are the same as those in FIG.

  FIG. 10 is a flowchart for determining a chip initialization order of the multichip system according to the fifth embodiment.

  When the power is turned on to the multichip system, a reset signal 301 is output to each chip of the multichip system. As a result, the reset IC 300 releases the chip reset of the chip 110, the reset of the chip 120 other than the CPU 121, the reset of the chip 140 other than the CPU 141, and the reset of the chip 130 other than the CPU 131.

  After the reset of the reset IC 300 is released, in step S801, the chip 110 starts initialization. In step S802, when the user interface signal 412 is input from the user interface unit 411, in step S803, the initialization chip table 109a is selected according to the type of the pressed key. As a result, in step S804, the CPU 111 determines the chip initialization order by reading the selected initialization chip table 109a. In step S805, an initialization flow is started in the determined order of initialization. The method of initializing each chip is the same as the method described with reference to FIG. 2 and the like, except that the order of initialization is different, and a description thereof will be omitted.

  As described above, in the present embodiment, the initialization order table is variably determined based on information input from the outside based on the initialization chip table in which the initialization order of the chips is recorded. Thus, the initialization of the chips can be started in a variable order, and the required start-up time of the subsystem can be shortened. That is, in the present embodiment, the initialization of the chip required to execute the designated operation can be hastened. For example, depending on the operation mode, the operation can be executed without initializing the downstream chip. Therefore, in the present embodiment, it is possible to preferentially initialize the operation of the chip connected to the functional units (printing unit, scanner unit, etc.) used in the operation mode. Therefore, depending on the operation mode, the operation can be started earlier.

(Other embodiments)
The present invention is not limited to the embodiments described above. For example, in the above-described embodiment, the master chip and the slave chip have different configurations. However, the present invention is not limited to this, and the master chip and the slave chip may have the same configuration. In this case, each chip can be a master chip or a slave chip.

  In the above-described embodiment, the communication between all the chips is established before the initialization of the slave chip is started, but the chip to be preferentially initialized is not a terminal chip but a relay chip. In some cases, not all communications need to be established up to the terminal chip. Therefore, although the communication between the master chip and the chip to be preferentially initialized has been established, the initialization of the chip to be preferentially initialized may be started before the communication with all the chips is established. .

  In the above-described embodiment, the CPU 111 of the chip 110, which is the master chip, sets each interface unit and establishes communication between the chips. However, the present invention is not limited to this. For example, the reset IC 300 may output a reset signal and release the chip reset, so that communication between the chips can be automatically established first while the CPU of the slave chip is reset.

  In the above-described embodiment, the case where the number of chips is three or four is described as an example. However, the number of chips is not limited to three or more as long as the number is three or more.

  In the embodiment described above, the chips are connected in series, and the program is distributed from one chip to another chip. However, the present invention is not limited to this. For example, a part of the chips may be connected in parallel, or a plurality of chips for distributing the program may be provided.

  Further, in the above-described embodiment, the CPU 111 stores the program for initializing the chip 130 in the RAM 221 for the chip 130, but is not limited thereto. For example, a program including a program for initializing the chip 130 and a program for initializing another chip may be stored.

  In the third embodiment, the order for initializing all the connected chips is determined. However, when the system can be started only by initializing some of the chips, only the chips necessary for starting the system are determined. The initialization order may be determined. Then, instead of initializing all the chips, only the chips for which the initialization order is determined may be initialized.

  In the fourth embodiment, the CPU 111 acquires the connection information indicating the connection state of the option unit unit 290 and determines the order of initialization, but the present invention is not limited to this. For example, the ROM 202 may include the chip initialization order information 202a, and update the chip initialization order information 202a according to the connection information of the internal register 294 of the option unit detection unit 293. In this case, the CPU 111 can execute the initialization according to the flow shown in FIG. 2 based on the initialization order information 202a. Further, for example, the ROM 202 includes an initialization table in which the order of initialization is set for each connection state, and acquires the initialization table according to the connection information of the internal register 294 of the option unit detection unit 293. You may.

  In the fifth embodiment, the user interface signal is input to the initialization table. However, the signal input to the initialization table is not limited to the user interface signal. For example, it may be information input from a PC via a host interface or input information from another external device.

  Further, by combining the above-described embodiments, the initialization method may be appropriately changed. For example, in the normal start-up, the order of each chip is determined based on information in the ROM as in the first embodiment. As described above, the activation may be performed using the initialization chip table.

In addition, it is not necessary to execute all of the processes of the above-described embodiments using hardware, and some of them may be configured using software.

100, 100A, 100B, 100C Image processing device 110 Master chip 120, 130, 140, 150 Slave chip 111, 121, 131, 141, 151 CPU
112, 122, 132, 142, 152 RAM controller unit 113 ROM controller unit 123 print control unit 133 mechanical drive control unit 143 scanner control unit 153 data processing unit 114, 124, 134, 144, 154 CPU reset control unit 115, 125, 126, 136, 145, 146, 155, 156 Interface section 118, 128, 138, 148, 158 Bus 250, 251, 260, 261, 270, 280 Interface 253, 263, 273, 283 CPU reset signal 190 Host PC
191 Host interface 201, 211, 221, 231 RAM
202 ROM
212 Printing unit 222 Mechanical unit

Claims (10)

An information processing apparatus in which three or more chips including at least a first chip, a second chip, and a third chip are connected in series,
At least a first chip among the chips connected in series,
Specifying means for specifying a chip whose initialization is prioritized;
Control means for initializing the chip specified by the specifying means,
Has,
In a case where the third chip is specified as a chip that prioritizes the initialization by the specifying unit, the control unit sets the third chip before transferring an initialization program for the second chip to the second chip. transferring the third program for chip initialization of the third chip,
The information processing apparatus according to claim 1, wherein the third chip is initialized by a program for initializing the third chip . The information processing apparatus according to claim 1, wherein the third chip is a chip that requires longer time to initialize than the second chip . 3. The device according to claim 1, wherein the specifying unit specifies a chip to which the initialization is prioritized by acquiring initialization order information stored in a memory corresponding to the first chip in advance. 4. Information processing device.   2. The device according to claim 1, wherein the identification unit identifies initialization-priority chips by acquiring initialization order information stored in an internal register of each chip of the serially connected chips. Or the information processing device according to 2.   The information processing apparatus according to claim 4, wherein the initialization order information stored in the internal register is input information input from an external terminal. Determining means for determining whether an optional unit is connected to the information processing apparatus;
Determining means for determining the order of initialization based on the determination result of the determining means,
The information processing apparatus according to claim 1 , further comprising:   The information processing apparatus according to claim 1, wherein the chip that gives priority to the initialization is a chip necessary to execute a specified operation.   The control unit establishes communication up to the chip specified by the specifying unit, transfers a program for initializing the chip to the chip specified by the specifying unit, and initializes the chip. The information processing apparatus according to claim 1. 9. The information processing apparatus according to claim 1, wherein the second chip establishes communication with the first chip before the third chip. 9. A method for controlling an information processing device in which three or more chips including at least a first chip, a second chip, and a third chip are connected in series,
In the first chip,
Identifying a chip for which initialization is prioritized;
Transfer the program for initialization of the chip to the particular chips, the method comprising the chip Ru is initialized,
Run,
In a case where the third chip is specified as a chip that has a higher priority for the initialization, before transferring the initialization program for the second chip to the second chip, the third chip is loaded with the third chip. Transfer the initialization program,
The control method according to claim 1, wherein the third chip is initialized by a program for initializing the third chip .

Images