JP7206693B2 - Information processing equipment - Google Patents

Description

The present invention relates to an information processing device.

Patent Document 1 discloses an interface circuit for a card-type memory that connects a plurality of card-type memories that are detachable and capable of at least one of reading and writing data and an electronic device main body, wherein the plurality of card-type memories are , a first card-type memory in which boot program data is recorded, and a second card-type memory for transferring and storing image data, etc., connected to each of the plurality of card-type memories; Card access control means for accessing any one of the card-type memories to read and write data, and the electronic device main body based on boot program data transferred from the first card-type memory a transfer control means for controlling data transfer between the second card-type memory and the memory of the electronic device main body; and the start control means and the transfer control means. Based on a selection means for making a selection based on a signal from the electronic device main body, a signal from the electronic device main body instructing the selection of the selection means, and a signal indicating the data transfer state of the card access control means, and switching control means for controlling switching of the selection means, wherein the switching control means switches a signal from the electronic device main body that instructs the selection of the selection means, and changes the data transfer state by the card access control means. Disclosed is an interface circuit for a card-type memory characterized by outputting a switching control signal for switching the selection means when in a stopped state.

Japanese Patent No. 4508687

A central processing unit (CPU) has a plurality of I/Fs including a dedicated interface section (dedicated I/F section) used at startup. Conventionally, the startup program is stored in a dedicated storage device connected to the dedicated I/F of the CPU, and the startup program is read from the dedicated storage device at startup.
SUMMARY OF THE INVENTION It is an object of the present invention to provide an information processing apparatus that does not require a dedicated storage device for boot programs.

Each aspect of the information processing apparatus of the present invention will be described.
In a first aspect, a storage device in which a startup program that is read and executed at startup is stored in advance, a first terminal that is used at startup, and the first terminal that are of different types are used after startup. a second terminal, a control section for outputting a control signal after expansion of the startup program; a third terminal connected to the first terminal of the control section via a first transmission line; a fourth terminal connected to the second terminal of the control unit via a second transmission line different in type from the transmission line; a fifth terminal connected to the storage device via a third transmission line; A switching unit including a sixth terminal to which a control signal is input, wherein the third terminal and the fifth terminal are connected at startup, and the fourth terminal and the fifth terminal are connected after startup. and a switching unit that is switched according to the control signal input from the sixth terminal so that the information processing apparatus is provided with.

In a second aspect, the storage device is a storage device from which data can be read and data is written, and the control unit, after startup, writes data to the storage device and stores data in the storage device. The information processing apparatus according to the first aspect, which performs at least one of reading out the data obtained from the information processing apparatus.

A third aspect is the information processing apparatus according to the second aspect, wherein the control unit prohibits writing to an area in which the boot program is stored.

In a fourth aspect, the third transmission line is of a type different from that of the first transmission line and is of the same type as that of the second transmission line, and the switching unit transmits converting the format of data into the format of data transmitted over the third transmission line, and converting the format of data transmitted over the third transmission line into the format of data transmitted over the first transmission line The information processing apparatus according to any one of the first to third aspects, further comprising a unit.

A fifth aspect is the information processing apparatus according to the fourth aspect, wherein the first transmission line transmits data faster than each of the second transmission line and the third transmission line.

A sixth aspect is any one aspect from the first aspect to the fifth aspect, wherein a control signal having a predetermined value is output by a pull-up resistor provided on a circuit board of the control unit at startup. is an information processing device.

According to the present invention, it is possible to provide an information processing apparatus that does not require a dedicated storage device for boot programs.

According to the second aspect, the storage devices can be combined into one.

According to the third aspect, the boot program cannot be rewritten.

According to the fourth aspect, data can be transmitted even if the types of transmission paths are different.

According to the fifth aspect, data transfer can be performed at a higher speed than reading of the boot program.

According to the sixth aspect, it is possible to output the control signal even at the time of activation.

1 is a block diagram showing an example of the configuration of an information processing device according to an embodiment of the present invention; FIG. 1 is a block diagram showing an example of the configuration of a conventional information processing device; FIG. FIG. 4 is a schematic diagram showing an example of a mechanism for outputting control signals; 4 is a chart showing an example of control signals according to states; 5 is a time chart showing an example of data transfer after power-on;

An example of an embodiment of the present invention will be described in detail below with reference to the drawings.

<Information processing device>
First, the information processing device will be described.
FIG. 1 is a block diagram showing an example configuration of an information processing apparatus according to an embodiment of the present invention. The information processing apparatus 10 includes a central processing unit (CPU) 20 , a storage device 40 storing a boot program 50 , and a switching section 30 . The CPU 20 is an example of the "controller".

The switching unit 30 switches an interface (I/F) that connects the CPU 20 and the storage device 40 . The boot program is a program that executes a process of deploying basic software such as an operating system (OS) when the power of the information processing apparatus is turned on. Booting is booting the OS. Activation is also referred to as boot.

The storage device 40 is a storage device from which data can be read and data can be written. Hereinafter, data reading and data writing are referred to as "data transfer". The storage device 40 has a ROM area in which writing of data is prohibited. A boot program 50 is stored in this ROM area. In addition to the boot program 50, the ROM area also stores an OS program and the like.

As the storage device 40, for example, an embedded Multi Media Card (eMMC) may be used. eMMC is a type of storage device that includes NAND flash memory and control circuitry. The eMMC is incorporated in the information processing device and functions as a built-in storage device. The eMMC has a simpler structure than a hard disk drive (HDD) and can read and write data faster than the HDD. Also, for example, an embedded SD card may be used as the storage device 40 .

The CPU 20 has a plurality of terminals. In the illustrated example, the CPU 20 has a first terminal 22 , a second terminal 24 , a seventh terminal 26 and an eighth terminal 28 . For example, an external storage device 42 is connected to the eighth terminal 28 of the CPU 20 . The switching unit 30 also has a plurality of terminals. In the illustrated example, the switching section 30 includes a third terminal 32 , a fourth terminal 34 , a fifth terminal 38 and a sixth terminal 36 .

The first terminal 22 of the CPU 20 and the third terminal 32 of the switching section 30 are connected by a first transmission line 52 . A connection via the first transmission line 52 is called a "first I/F". The first transmission line 52 is, for example, a serial bus that connects devices used inside the information processing apparatus. A serial bus transmits data bit by bit. The data transfer speed is slower than that of a parallel bus that transfers data in units of multiple bits. Specifically, the first transmission line 52 may be a serial peripheral interface (SPI) or the like.

The second terminal 24 of the CPU 20 and the fourth terminal 34 of the switching section 30 are connected via a second transmission path 54 . A connection via the second transmission line 54 is called a "second I/F". The fifth terminal 38 of the switching section 30 and the storage device 40 are connected by a third transmission line 58 . The seventh terminal 26 of the CPU 20 and the sixth terminal 36 of the switching section 30 are connected by a signal line 56 for transmitting control signals. The third transmission line 58 is shared by both the "first I/F" and the "second I/F".

The second transmission line 54 and the first transmission line 52 have different formats of data to be transmitted. The second transmission line 54 and the third transmission line 58 share the format of data to be transmitted. The second transmission line 54 and the third transmission line 58 are, for example, data buses used for data transfer. The data bus is a parallel bus. A parallel bus has a faster data transfer speed than a serial bus. Specifically, each of the second transmission line 54 and the third transmission line 58 may be an SD card interface or the like.

Each of the first transmission line 52, the second transmission line 54, and the third transmission line 58 cannot transmit data when the connection state is invalid, and transmits data when the connection state is valid.

The switching unit 30 includes a conversion unit 35 and a selection unit 37 in addition to the plurality of terminals. The selection unit 37 selects whether to connect the CPU 20 and the storage device 40 via the "first I/F" or via the "second I/F" according to the control signal. When reading the boot program 50 from the storage device 40 (at the time of booting), the CPU 20 and the storage device 40 are connected by the "first I/F". Also, when data transfer is to be performed with the storage device 40 (after activation), the CPU 20 and the storage device 40 are connected by the "second I/F". Note that data may be transferred between the CPU 20 and the external storage device 42 after startup.

The converter 35 is arranged between the third terminal 32 and the selector 37 . The data format transmitted by the first transmission line 52 is converted into a data format that can be transmitted by the third transmission line 58 . The conversion unit 35 also converts the format of the data transmitted through the third transmission line 58 into a format of data that can be transmitted through the first transmission line 52 . As data format conversion, for example, serial-parallel conversion, protocol conversion, and the like are performed.

(Difference from conventional configuration)
Here, differences from the configuration of the conventional information processing apparatus will be described.
FIG. 2 is a block diagram showing an example of the configuration of a conventional information processing apparatus. A conventional information processing apparatus 10A includes a CPU 20, a first storage device 44 storing a boot program 50, and a second storage device 46. FIG. The first storage device 44 is a dedicated storage device for the boot program 50, and data writing is prohibited. The second storage device 46 is a storage device from which data can be read and written.

The first terminal 22 of the CPU 20 and the first storage device 44 are connected by a first transmission line 52 . The second terminal 24 of the CPU 20 and the second storage device 46 are connected by a second transmission line 54 . At startup, the startup program 50 is read from the first storage device 44 via the first transmission line 52 . After startup, data transfer is performed with the second storage device 46 via the second transmission line 54 .

The first transmission line 52 is used for reading the boot program 50, and the second transmission line 54 is used for data transfer. Although this point is similar to the present embodiment, conventionally, the first storage device 44 dedicated to the boot program 50 was provided separately from the second storage device 46 . Therefore, in the conventional information processing apparatus 10A, connection to the first storage device 44 or connection to the second storage device 46 is selected. That is, conventionally, the storage device that is the connection destination is switched.

On the other hand, in this embodiment, as shown in FIG. 1, the storage devices are combined into one. The activation program 50 is stored in the storage device 40 used for data transfer. Then, it is selected whether the CPU 20 and the storage device 40 are connected by the "first I/F" or by the "second I/F". That is, the I/F that connects the CPU 20 and the storage device 40 is switched.

(Control signal)
Next, a mechanism for outputting the control signal will be described.
FIG. 3 is a schematic diagram showing an example of a mechanism for outputting control signals. At startup, that is, before the startup program is developed, the CPU 30 cannot control each part. Therefore, as shown in FIG. 3, the seventh terminal 26 of the CPU 20 and the sixth terminal 36 of the switching section 30 are connected with an open drain. The value of the control signal is high level (H) or low level (L). A high level (H) is a level whose voltage level is higher than the threshold. A low level (L) is a voltage level equal to or lower than a threshold.

The seventh terminal 26 includes a field effect transistor (FET). A pull-up resistor 60 having one end grounded is connected to the signal line 56 connected to the drain terminal of the FET. The pull-up resistor 60 fixes the initial value of the control signal to "H". The pull-up resistor 60 is provided on the same substrate as the CPU 30, for example.

FIG. 4 is a table showing an example of control signals according to states. It represents the value of the control signal according to the state of the CPU, the G signal, and the state of the FET. A G signal is a signal that is input to the gate terminal of the FET. The value of the G signal is H or L. When the CPU is in the initial state and the first I/F is selected, the G signal is "L" and the FET state is "OFF" before the startup program is developed. Therefore, the pull-up resistor 60 makes the control signal "H".

When the CPU state selects the second I/F, the CPU 30 can control each part after the boot program is deployed. The CPU 30 controls the FET to switch ON/OFF. When the G signal is "H" and the FET state is "ON", the control signal becomes "L". When the G signal is "L" and the FET state is "OFF", the control signal becomes "H".

<Action>
Next, the operation of the information processing device will be described.
FIG. 5 is a time chart showing an example of data transfer after power-on. Also referring to FIG. 1, the operation of the information processing apparatus 10 will be described.

First, when the power is turned on, the control signal "H" is output as described above. The output control signal “H” is input to the selection section 37 of the switching section 30 via the signal line 56 and the sixth terminal 36 . When the control signal "H" is input, the selection unit 37 selects to connect the CPU 20 and the storage device 40 by the "first I/F". The switching unit 30 switches connection so that the third terminal 32 and the fifth terminal 38 are connected. That is, the connection statuses of the first transmission line and the third transmission path are "valid", and the connection status of the second transmission path is "invalid".

The CPU 20 connects to the storage device 40 via the “first I/F” and reads the boot program 50 . The activation program 50 is transmitted to the fifth terminal 38 via the third transmission line 58 . The activation program 50 transmitted through the third transmission line 58 is converted by the conversion unit 35 into a data format that can be transmitted through the first transmission line 52 . The boot program 50 whose data format has been converted is transmitted from the third terminal 32 to the first terminal 22 via the first transmission path 52 . The CPU 20 develops the read boot program 50 on a RAM (not shown).

When the startup program 50 is finished developing, the CPU 30 outputs a control signal "L". The output control signal “H” is input to the selection section 37 of the switching section 30 via the signal line 56 and the sixth terminal 36 . The selection unit 37 selects to connect the CPU 20 and the storage device 40 by the "second I/F". The switching unit 30 switches connection so that the fourth terminal 34 and the fifth terminal 38 are connected. That is, the connection status of the second transmission line and the third transmission line becomes "valid", and the connection status of the first transmission line becomes "invalid".

The CPU 20 connects to the storage device 40 via the “second I/F” and reads out the OS program stored in the storage device 40 . The OS program is transmitted to the fifth terminal 38 via the third transmission line 58 . The OS program is transmitted from the fourth terminal 34 to the second terminal 24 by the second transmission line 54 . The CPU 20 develops the read OS program on a RAM (not shown). This starts the OS.

Even after startup, the CPU 20 and the storage device 40 are connected by the "second I/F". The CPU 20 reads data stored in the storage device 40 and writes data to the storage device 40 via the "second I/F".

<Modification>
The configuration of the information processing apparatus described in the above embodiment is an example, and it goes without saying that the configuration may be changed without departing from the gist of the present invention.

10 information processing device 10A information processing device 22 first terminal 24 second terminal 26 seventh terminal 28 eighth terminal 30 switching section 32 third terminal 34 fourth terminal 35 conversion section 36 sixth terminal 37 selection section 38 terminal 40 storage device 44 First storage device 46 Second storage device 50 Boot program 52 First transmission line 54 Second transmission line 56 Signal line 58 Third transmission line 60 Pull-up resistor

Claims (4)

a storage device pre-stored with a startup program that is read out and executed at startup;
a control unit that includes a first terminal that is used at startup and a second terminal that is different in type from the first terminal and is used after startup, and that outputs a control signal after the startup program is developed;
a third terminal connected to the first terminal of the control unit via a first transmission line; and the second terminal of the control unit via a second transmission line different in type from the first transmission line. A switching unit comprising a connected fourth terminal, a fifth terminal connected to the storage device via a third transmission line, and a sixth terminal to which a control signal is input,
Switching is performed according to the control signal input from the sixth terminal so that the third terminal and the fifth terminal are connected at startup, and the fourth terminal and the fifth terminal are connected after startup. a switching unit that is
wherein the third transmission line is of a type different from that of the first transmission line and of a type common to that of the second transmission line;
The switching unit converts the format of the data transmitted through the first transmission line into the format of the data transmitted through the third transmission line, and converts the format of the data transmitted through the third transmission line into the Further comprising a conversion unit that converts the format of the data to be transmitted on the first transmission line,
Information processing equipment. The storage device is a storage device capable of reading data and writing data,
After starting, the control unit performs at least one of writing data to the storage device and reading data stored in the storage device.
The information processing device according to claim 1 . The control unit prohibits writing to the area where the boot program is stored.
The information processing apparatus according to claim 2 . The first transmission line has a slower data transmission speed than each of the second transmission line and the third transmission line,
The information processing apparatus according to any one of claims 1 to 3.

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