JP2004297077A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having a shallow impurity region. <P>SOLUTION: In the method for manufacturing a semiconductor device, a gate electrode part having a gate oxide film, a floating gate on the gate oxide film, a control gate on the floating gate, and an oxide formed by oxidizing the floating gate and the control gate is formed on a semiconductor. Impurities are then added to the semiconductor using the gate electrode part as a mask to form an impurity region having a depth of 0.1 μm or less. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a technique of performing a doping process in a process of manufacturing a semiconductor device such as a semiconductor integrated circuit, and a semiconductor device (element) manufactured by the above technology.

  Conventionally, a thermal diffusion method and an ion implantation method have been known as techniques for performing doping. The thermal diffusion method is a method in which impurities are diffused into a semiconductor in a high temperature atmosphere of 500 to 1200 degrees. The ion implantation method is a method in which ionized impurities are accelerated by an electric field and implanted into a predetermined place. However, in the ion implantation method, the crystal structure is remarkably destroyed by the high-energy ions, the amorphous state or a state close to the amorphous state is obtained, and the electric characteristics are significantly deteriorated. Since the ion implantation method can control the impurity concentration more easily than the thermal diffusion method, it has become an indispensable technique for manufacturing VLSI and ULSI.

  However, ion implantation is not without its problems. The biggest problem has been the difficulty in controlling the diffusion of the implanted ions. This is a serious problem particularly in a so-called quarter micron device having a design rule of 0.5 μm or less. In recent years, it has been required to form a shallow region in which impurities are diffused (diffusion region). However, it is difficult to form a diffusion region having a depth of 0.1 μm or less with good reproducibility by ion implantation. there were. The above points will be described with reference to FIG.

  The first problem is due to the fact that the ions implanted into the semiconductor are diffused in the lateral direction by secondary scattering due to ion implantation, and are thermally expanded to the surroundings by the heat treatment process. is there. Such an effect was hardly a problem when the design rule (typically, the width of the gate electrode of the MOSFET) was 1.0 μm or more. As shown in FIG. 3A, the width becomes larger than the width of the gate electrode, and the gate electrode 205 and the diffusion regions (source and drain) 202 and 203 are geometrically overlapped. Such an overlap causes a parasitic capacitance between the gate electrode, the source and the drain, and lowers the operation speed.

  The second problem is roughly attributable to two effects. One is the effect of diffusion due to thermal factors as pointed out in the first problem. For this reason, it is difficult to make the thickness of the diffusion region 0.1 μm or less. Another effect is remarkable when the semiconductor is crystalline, but is an effect of channeling in ion implantation. This is an effect that, when the light is perpendicularly incident on the crystal plane, the ions reach a deep part of the substrate because the ions are not scattered at all.

  Conventionally, in order to avoid this channeling effect, ion implantation is performed with an inclination of several degrees with respect to the crystal plane. However, even with such a contrivance, the ions whose orbits are bent inside the semiconductor may meet the channeling conditions. Therefore, as shown in FIG. 2B, ions enter into a deep position. Further, when ions are implanted into a polycrystalline semiconductor, the crystal planes are random, so that the ion depths are completely different.

  There is another problem when using a polycrystalline semiconductor. That is, in a polycrystalline semiconductor, thermal diffusion of a doped impurity tends to proceed through a grain boundary of a crystal, and therefore, as shown in FIG. 2C, doping cannot be performed uniformly. These problems have been difficult to solve by the conventional methods of ion implantation and recrystallization by heat treatment. Of course, the thermal diffusion method could not solve the problem at all.

  The problems to be solved by the present invention are summarized as follows. That is, firstly, diffusion of impurities in the lateral direction is prevented, and secondly, the depth of the diffusion is controlled to be 0.1 μm or less, preferably 50 nm or less. An object of the present invention is to provide a method for solving at least one of these two problems in a part or all of a single crystal or a polycrystal or a semiconductor material equivalent thereto. By satisfying the above conditions, a MOS device having a channel length of 1.0 μm or less, typically 0.1 to 0.3 μm can be manufactured stably.

  In order to solve the above-described problems, the present invention provides a highly pure reactive gas (impurity gas) containing an impurity that imparts a conductivity type to a semiconductor and a relatively stable gas such as hydrogen, fluorine, helium, or argon. By irradiating the surface of the sample semiconductor with a pulsed laser beam in an atmosphere diluted with the above, impurities are doped into the sample semiconductor. In this method, the impurity gas in the vicinity of the semiconductor surface heated instantaneously by laser irradiation is decomposed or reacts with the semiconductor surface, and only a very thin portion of the semiconductor surface is doped with the impurity. The thickness depends on the temperature at which the surface of the semiconductor is held, but can be 0.1 μm or less.

  In such a reaction, thermal diffusion can be substantially eliminated by setting the pulse width of the laser beam to 1 μsec or less, preferably 100 nsec or less. Further, according to the present invention, there is no channeling or secondary scattering which is a problem in ion implantation. Therefore, as shown in FIG. 1A, a very ideal diffusion region is formed, and the impurity concentration in the depth direction is formed. As shown in FIG. 1B, the distribution is concentrated only at the required depth, and the distribution of impurities in the depth direction in the impurity region formed in the semiconductor is indicated by a distribution curve 106. Although there is strictly lateral diffusion, its size is typically less than 50 nm and is negligible in real devices.

  Further, even in a semiconductor material having a grain boundary, since there is no thermal influence, the diffusion region is not affected by the grain boundary as shown in FIG. In addition, in the present invention, since a non-thermal equilibrium state of heating by a pulsed laser is used, high-concentration impurity diffusion, which has been impossible in the past, is possible.

  In the present invention, the desired value of the impurity concentration can be obtained by adjusting the energy of the laser, the concentration of the impurity gas in the atmosphere, the semiconductor surface temperature, and the like. In the present invention, the semiconductor surface where the impurity is to be diffused may be exposed or covered with another film. When the film is covered with another film, impurities are blocked by the chemical and physical properties of the film, and as a result, the diffusion concentration and the diffusion depth in the semiconductor are controlled.

The impurity in the present invention can be a trivalent impurity, typically B (boron) or the like, when a silicon semiconductor (silicon) is used as the semiconductor and P-type is imparted. , N-type, pentavalent impurities, typically P (phosphorus), As (arsenic), or the like can be used. AsH ₃ , PH ₃ , BF ₃ , BCl ₃ , B (CH ₃ ) ₃ or the like can be used as a reactive gas containing these impurities.

  As a semiconductor, in addition to a conventional wafer-shaped single-crystal silicon semiconductor, an amorphous silicon semiconductor thin film formed by a vapor phase growth method, a sputtering method, or the like is generally used if a TFT is manufactured. Can be Further, the present invention can be applied to a polycrystalline or single-crystal silicon semiconductor formed over an insulating substrate by liquid phase growth. Furthermore, it is needless to say that the semiconductor is not limited to a silicon semiconductor, and may be another semiconductor.

  It is useful to use a pulse oscillation type excimer laser device as the laser light. This is because in the case of the pulsed laser, heating of the sample is instantaneous and is limited only to the surface, and does not affect the substrate. Heating with a continuous wave laser cannot achieve the above-mentioned non-thermal equilibrium state, and it is a local heating. May peel off. In this regard, in the pulse laser, the thermal relaxation time is overwhelmingly smaller than the reaction time of mechanical stress such as thermal expansion, and does not cause mechanical damage.

  In particular, excimer laser light is ultraviolet light, is efficiently absorbed by many semiconductors such as silicon, and has a short pulse duration of 10 nsec. Excimer lasers have already been used in experiments in which an amorphous silicon thin film is crystallized by laser irradiation to obtain a highly crystalline polycrystalline silicon thin film. As a specific type of laser, it is appropriate to use an ArF excimer laser (wavelength 193 nm), a XeCl excimer laser (wavelength 308 nm), a XeF excimer laser (wavelength 351 nm), a KrF excimer laser (248 nm), or the like.

  In the present invention, the semiconductor surface may be heated or cooled. By controlling the temperature of the semiconductor surface, the diffusion of impurities can be promoted or suppressed. Therefore, those who carry out the present invention perform temperature control in order to obtain desired impurity concentrations and diffusion depths. It is recommended.

  In the present invention, it is also effective to convert the impurity gas into plasma using DC or AC electric energy in order to promote the decomposition of the impurity gas. 13.56 MHz high frequency energy is generally used as the electromagnetic energy applied for this purpose. Due to the decomposition of the doping gas by the electromagnetic energy, doping can be efficiently performed even when a laser beam that cannot directly decompose the doping gas is used. The type of electromagnetic energy is not limited to the frequency of 13.56 MHz. For example, if a microwave of 2.45 GHz is used, a higher activation rate can be obtained. Further, an ECR condition generated by an interaction between a microwave of 2.45 GHz and a magnetic field of 875 Gauss may be used. It is also effective to use light energy capable of directly decomposing the doping gas.

  FIGS. 3 and 4 show conceptual diagrams of the apparatus of the present invention. FIG. 3 shows an apparatus provided with a substrate heating device, and FIG. 4 shows an apparatus provided with an electromagnetic device for generating plasma in addition thereto. Since these drawings are conceptual, it is needless to say that an actual device may include other components as necessary. Hereinafter, the method of use will be outlined.

In FIG. 3, the sample 304 is set on a sample holder 305. First, the chamber 301 is evacuated by an exhaust system 307 connected to an exhaust device. In this case, it is desirable to evacuate to as high a vacuum as possible. That is, carbon, nitrogen, and oxygen, which are atmospheric components, are generally not preferable for semiconductors. Such an element is taken into the semiconductor, but may reduce the activity of the impurity added at the same time. In addition, it impairs the crystallinity of the semiconductor and causes dangling bonds at grain boundaries. Therefore, it is desired to evacuate the chamber to 10 ^-6 torr or less, preferably 10 ^-8 torr or less.

  It is also desirable to operate the heater 306 before and after the exhaust to drive out the atmospheric components adsorbed inside the chamber. As used in current vacuum equipment, it is also desirable to provide a spare chamber in addition to the chamber so that the chamber does not directly contact the atmosphere. As a matter of course, it is desirable to use a turbo-molecular pump or a cryopump with less contamination of carbon or the like as compared with a rotary pump or an oil diffusion pump.

  Once fully evacuated, a reactive gas is introduced into the chamber by the gas system 308. The reactive gas may consist of a single gas, or may be diluted with hydrogen, argon, helium, neon, or the like. The pressure may be atmospheric pressure or lower. These are selected in consideration of the type of the target semiconductor, the impurity concentration, the depth of the impurity region, the substrate temperature, and the like.

  Next, the sample is irradiated with the laser beam 303 through the window 302. At this time, the sample is heated to a certain temperature by the heater. The laser light is usually applied to one place at about 1 to 50 pulses. In a state where the energy of the laser pulse has a very large variation and the number of pulses is small, the probability of occurrence of a defect is large. On the other hand, irradiating too many pulses to one location is not desirable in terms of mass productivity (throughput). According to the knowledge of the present inventor, the above-mentioned number of pulses was appropriate from the viewpoint of mass productivity and the yield.

  In this case, for example, when the laser pulse has a specific rectangular shape of 10 mm (x direction) × 30 mm (y direction), the same region is irradiated with 10 laser pulses, and after the end, the next The laser may be moved to a portion, but the laser may be moved in the x direction by 1 mm per pulse.

When the laser irradiation is completed, the inside of the chamber is evacuated, the sample is cooled to room temperature, and the sample is taken out. Thus, in the present invention, the doping process is extremely simple and fast. That is, if it is a conventional ion implantation process,
(1) Doping pattern formation (resist coating, exposure, development)
(2) Ion implantation (or ion doping)
(3) Three steps of recrystallization were required. However, in the present invention,
(1) Doping pattern formation (resist coating, exposure, development)
(2) It is completed in two steps of laser irradiation.

  4 is almost the same as that in FIG. First, the inside of the chamber 401 is evacuated by the exhaust system 407 and a reactive gas is introduced from the gas system 408. Then, the sample 404 on the sample holder 405 is irradiated with laser light 403 through the window 402. At that time, power is supplied to the electrode 409 from a high frequency or AC (or DC) power supply 410 to generate plasma or the like inside the chamber, thereby activating the reactive gas. Although the electrodes are shown as being capacitively coupled in the figure, they may be of the inductive (inductance) coupled type. Furthermore, the sample holder may be used as one electrode even if it is a capacitive coupling type. At the time of laser irradiation, the sample may be heated by the heater 406.

  FIG. 5 shows another doping apparatus according to the present invention. That is, a slit-like window 502 made of anhydrous quartz glass is provided in the chamber 501. The laser beam is shaped into an elongated shape to fit this window. The laser beam was, for example, a rectangle of 10 mm × 300 mm. The position of the laser beam is fixed. An exhaust system 507 and a gas system 508 for introducing a reactive gas are connected to the chamber. Further, a sample holder 505 is provided in the chamber, a sample 504 is placed thereon, and an infrared lamp (functioning as a heater) 506 is provided below the sample holder. The sample holder is movable and can move the sample in accordance with the laser shot.

  As described above, when the mechanism for moving the sample is incorporated in the chamber, the thermal expansion of the sample holder caused by the heater causes a disorder, so that extreme care is required for temperature control. Further, since dust is generated by the sample transfer mechanism, maintenance in the chamber is troublesome.

  FIG. 6A shows another doping apparatus according to the present invention. That is, a window 602 made of anhydrous quartz glass is provided in the chamber 601. Unlike the case of the third embodiment, this window is wide enough to cover the entire surface of the sample 604. An exhaust system 607 and a gas system 608 for introducing a reactive gas are connected to the chamber. A sample holder 605 is provided in the chamber, and a sample 604 is placed on the sample holder 605. The sample holder has a built-in heater. The sample holder is fixed to the chamber. A chamber base 601a is provided below the chamber, and laser irradiation is performed sequentially by moving the entire chamber in accordance with a laser pulse. The laser beam has an elongated shape as in the case of FIG. For example, it was a rectangle of 5 mm × 100 mm. As in FIG. 5, the position of the laser beam is fixed. In FIG. 6, unlike FIG. 5, a mechanism for moving the entire chamber is employed. Therefore, there is no mechanical part in the chamber and no dust or the like is generated, so that maintenance is easy. Further, the transfer mechanism is hardly affected by the heat of the heater.

  The example of FIG. 6 is superior to the example of FIG. 5 not only in the above points, but also in the following points. That is, in the method shown in FIG. 5, after the sample was put in the chamber, laser irradiation could not be performed until the sample was evacuated to a sufficient degree of vacuum. That is, there were many dead times. However, in the example of FIG. 6, a large number of chambers as shown in FIG. 6 (A) are prepared, and each of them is sequentially rotated in the order of sample loading, evacuation, laser irradiation, and sample removal, as described above. No dead time occurs. Such a system is shown in FIG.

  That is, the chambers 617 and 616 containing the unprocessed sample are directed by the continuous transfer mechanism 618 to the gantry 619 having a stage capable of precise movement during the evacuation process. The sample on the stage is irradiated with laser light emitted from the laser device 611 and processed by appropriate optical devices 612 and 613 to the chamber 615 on the stage through the window. By moving the stage, the chamber 614 to which the required laser irradiation has been performed is again sent to the next stage by the continuous transport mechanism 620, during which the heater in the chamber is turned off, exhausted, and sufficiently cooled. After lowering, the sample is removed.

  As described above, in the present embodiment, continuous processing can be performed, so that the evacuation waiting time can be reduced and the throughput can be improved. Of course, in the case of FIG. 6, although the throughput is improved, a larger number of chambers are required than in the case of FIG. 5, so that it should be carried out in consideration of the mass production scale and investment scale.

  As described above, in the examples of FIGS. 5 and 6, the shape of the laser beam is an elongated linear rectangle, but may be a rectangle or a square. In this case, as shown in FIG. 7, a method of dividing a substrate such as a semiconductor wafer into an appropriate number of regions (32 in FIG. 7) and sequentially irradiating a laser may be adopted. . For example, if the repetition frequency of the laser is 200 Hz, the time for processing one location on the wafer is 0.1 second, and the time required for the wafer to move up, down, left, and right (arrows in FIG. 7) is 1 The processing time for one wafer is less than 10 seconds. When wafers are automatically transferred, 200 or more wafers can be processed in one hour. This productivity is not less than that of the conventional method.

  Regarding the same laser doping apparatus, Japanese Patent Application Nos. 3-283981 (filed on Oct. 4, 1991), 3-290719 (filed on Oct. 8, 1991), and 4-100479 (filed on Oct. 8, 1991) (Filed on March 26, 2012). According to the present invention, for example, a device having a channel length of 0.5 μm or less can be manufactured with good reproducibility, and a diffusion region (impurity region) having a depth of 0.1 μm or less can be formed. Conversely, the present invention has features in forming a device under such conditions. Hereinafter, the present invention will be described in more detail with reference to Examples.

  According to the present invention, a MOS device having a channel length of 1.0 μm or less, typically 0.1 to 0.3 μm can be stably manufactured, and a shallow impurity region having a depth of 0.1 μm or less can be manufactured. In the above embodiment, the semiconductor device on single crystal silicon has been described. However, it goes without saying that the same may be applied to a device using polycrystalline silicon or the like. Thus, the present invention is industrially useful.

BEST MODE FOR CARRYING OUT THE INVENTION

Example 1 A CMOS circuit was formed on a single crystal silicon substrate by using the present invention. FIG. 8 shows the manufacturing procedure. First, a field insulator 702 is formed on the (100) plane of a single crystal silicon substrate 701 by a so-called LOCOS method, and boron is thermally diffused to a part of a region which is not covered with the field insulator. A mold well 703 was formed. In this state, a region other than the P-type well is covered with a mask material 704, and laser irradiation is performed in an atmosphere containing 2% by volume of diborane (B ₂ H ₆ ). Then, boron was diffused to form a P ⁺ region 705. (FIG. 8A)

  In this case, as the mask material 704, a material having good laser resistance is preferable, but it is not necessary to be opaque to laser light. For example, silicon nitride and silicon oxide satisfy the above conditions. Further, a carbon film may be used.

Laser doping was performed using the apparatus shown in FIG. In the apparatus shown in FIG. 5, boron (B) doping was performed by irradiating a laser beam in a B ₂ H ₆ / Ar atmosphere without heating the sample. The laser used was a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec), and irradiation was performed at an energy density of 150 to 350 mJ / cm ² for 2 to 20 shots per one place. At this time, when the temperature of the sample is lowered to room temperature or lower, preferably to −50 ° C., diffusion of impurities is suppressed, and the depth of the P ⁺ region 705 doped with impurities can be reduced. However, it is not preferred to lower the temperature below the freezing point or boiling point of diborane.

After that, the same operation was performed on the surface of the silicon substrate, and N ⁺ region 706 was formed by doping phosphorus with phosphine. Thereafter, a gate oxide film 707 and gate electrodes 708 and 709 were formed as in the conventional case. (FIG. 8 (B))

Thereafter, the region of the P-channel TFT (the right side in the figure) was covered with a mask material 710, and doping was performed again using the laser doping apparatus shown in FIG. At this time, phosphion was used as an impurity gas, and the substrate temperature was further increased to 200 to 450 ° C. The laser energy and the number of shots were within the range of the above conditions. At this time, since the sample is heated, the diffusion is larger than that in the previous doping, and the source and drain regions 711 are deeply doped with phosphorus to be N-type. On the other hand, the region below the gate electrode is not irradiated with the laser using the gate insulating film and the gate electrode as a mask, is not doped, and remains N ⁺ -type. Typical doping conditions are as follows. (FIG. 8 (C))
Atmosphere PH ₃ 5% concentration (H ₂ dilution)
Sample temperature 350 degrees Pressure 0.02 to 1.00 Torr
Laser KrF excimer laser (wavelength 248 nm)
Energy density 150 to 350 mJ / cm ²
Number of pulses 10 shots

  Similarly, the P-channel TFT (right side in the figure) was subjected to laser doping in a diborane atmosphere to form a P-type region, thereby forming a P-channel TFT.

  Thereafter, an interlayer insulator 712 was formed in the same manner as in the related art, contact holes were provided, and electrodes / wirings 713 were formed. It goes without saying that the material of the electrodes and wirings may be a single-layer metal or semiconductor film, or a multilayer film such as titanium nitride and aluminum.

  The transistor of this embodiment is a so-called buried channel type in which the surface of the channel formation region is not inverted even when a signal is applied to the gate, and a deeper region becomes a channel. Therefore, the gate insulating film is less likely to be broken by hot electrons or the like, and the reliability has been improved.

  In the present embodiment, the laser doping method was used to form the buried channel. In addition, for example, the present invention can be used for the purpose of controlling the threshold voltage. It will be clear from the description.

Embodiment 2 FIG. 9 shows an example in which a MOS device having a floating gate, for example, an EPROM, an EEPROM, or a flash memory is manufactured by using the present invention. First, a field insulator 751 is selectively formed on a (100) plane of a single crystal silicon substrate, and gate electrode portions 752 and 753 are formed. A detailed structure of the gate electrode portion is illustrated in FIG. Here, 761 is a gate oxide film, 762 is a floating gate of polysilicon doped with phosphorus, 763 is a control gate of polysilicon doped with phosphorus, and 764 is an insulating film covering them. Preferably, the insulating film 764 is formed of an oxide of a control gate and a floating gate. To oxidize these, an anodic oxidation method or a thermal oxidation method may be used. The width of the gate electrode was 0.5 μm. In the case of employing the anodic oxidation method, two methods, a wet method and a dry method, are used. These methods are described in Japanese Patent Application No. 3-278705 (filed on September 30, 1991). The method described in Japanese Patent Application No. 3-278706 (filed on Sep. 30, 1991) may be used.

  Thereafter, a mask material 754 was selectively formed, and phosphorus was implanted into the silicon substrate by ion implantation using the mask material and the gate electrode portion as a mask, and was heated and diffused to form an N-type region 755. . This N-type region was set to have a depth of about 0.2 μm. Further, as shown in FIG. 9A, the impurity region 755 formed at this time extends around the lower portion of the gate electrode portion.

  Next, as shown in FIG. 9B, a wiring 756 made of polysilicon doped with phosphorus was formed and used as a word line. However, when the resistance of the impurity region 755 is sufficiently small, the impurity region 755 can be used as a word line without providing such polysilicon.

Further, according to the present invention, laser doping of phosphorus was performed to form shallow (depth to 50 nm) impurity regions 757 and 758. In this embodiment, doping of impurities was performed using the apparatus shown in FIG. As shown in FIG. 6 (B), a large number of chambers (614 to 615) each containing one wafer were flowed and irradiated with laser light. Typical doping conditions are as follows.
Atmosphere PH ₃ 5% concentration (H ₂ dilution)
Sample temperature Room temperature Pressure 0.02-1.00 Torr
Laser KrF excimer laser (wavelength 248 nm)
Energy density 150 to 350 mJ / cm ²
Number of pulses 10 shots

  Through the above steps, a shallow impurity region was formed. Further, an interlayer insulator 759 was deposited by a conventional method, and a contact hole and metal electrodes / wirings 760 and 761 were formed to form an element. In FIG. 9D, two EEPROM elements are described, and wirings 760 and 761 serve as respective bit lines.

  In this embodiment, the shape of the impurity region differs between the left and right sides of the gate electrode portion. That is, one is a deep impurity region 755 extending to the lower portion of the gate electrode, and the other is a shallow impurity region 757 having no overlap at all and having an offset region formed by an oxide in the gate electrode portion. It is. The actual wrap around is less than 50 nm. As a result, when carriers are implanted into the floating gate, the carriers are implanted from deep impurity regions as indicated by arrows in FIG.

Embodiment 3 FIG. 10 shows an example in which a MOSFET using a low-concentration drain (LDD) structure is manufactured by using the present invention. First, a field insulator 802 is formed on a single crystal silicon substrate 801 by a conventional method, and a gate insulating film 803 and a gate electrode 804 are deposited. Then, phosphorus was doped using the laser doping method of the present invention to form a shallow (50 nm deep) low-concentration N ⁻ -type impurity region 805. (FIG. 10A)

Thereafter, a silicon oxide film 806 was deposited (FIG. 10B), and the silicon oxide film 806 was removed by anisotropic etching except for the side wall portion 807 of the gate electrode. Then, in this state, high-concentration phosphorus ions were implanted by ion implantation to form an N ⁺ region 808. At this time, only the lower portion of the side wall of the N ⁻ region 805 remains, and the LDD region 809 is formed. (FIG. 10 (C))

  Finally, an interlayer insulator 810 and a metal electrode / wiring 811 were formed to complete the device. In this embodiment, the LDD is formed by combining the conventional method and the doping method of the present invention. For example, Japanese Patent Application No. Hei 3-238710 (filed on Aug. 26, 1991), which is an application of the present inventors. And Japanese Patent Application No. 3-238711 (filed on Aug. 26, 1991) and Japanese Patent Application No. 3-238712 (filed on Aug. 26, 1991).

The effects of the present invention will be described conceptually. The problems of the prior art will be described. 1 shows a conceptual diagram of a semiconductor processing (impurity doping) apparatus of the present invention. 1 shows a conceptual diagram of a semiconductor processing (impurity doping) apparatus of the present invention. 1 shows an example of a semiconductor processing (impurity doping) apparatus of the present invention. 1 shows an example of a semiconductor processing (impurity doping) apparatus of the present invention. The example of the laser irradiation method of this invention is shown. An example of a method for manufacturing a semiconductor element using the present invention will be described. An example of a method for manufacturing a semiconductor element using the present invention will be described. An example of a method for manufacturing a semiconductor element using the present invention will be described.

Explanation of reference numerals

101 Substrate 102, 103 Diffusion region (source, drain)
104 gate insulating film 105 gate electrode 201 substrates 202, 203 diffusion region (source, drain)
204 gate insulating film 205 gate electrode

Claims (12)

On a semiconductor, a gate electrode portion having a gate oxide film, a floating gate on the gate oxide film, a control gate on the floating gate, and an oxide formed by oxidizing the floating gate and the control gate is formed. Forming
Adding an impurity to the semiconductor using the gate electrode portion as a mask to form an impurity region,
The method for manufacturing a semiconductor device, wherein the impurity region has a depth of 0.1 μm or less. On a semiconductor, a gate electrode portion having a gate oxide film, a floating gate on the gate oxide film, a control gate on the floating gate, and an oxide formed by oxidizing the floating gate and the control gate is formed. Forming
Adding an impurity to the semiconductor using the gate electrode portion as a mask to form an impurity region,
The method for manufacturing a semiconductor device, wherein the impurity region has a depth of 0.1 μm or less and does not overlap with the floating gate. On a semiconductor, a gate electrode portion having a gate oxide film, a floating gate on the gate oxide film, a control gate on the floating gate, and an oxide formed by oxidizing the floating gate and the control gate is formed. Forming
Adding an impurity to the semiconductor using the gate electrode portion as a mask to form an impurity region,
The method of manufacturing a semiconductor device, wherein the impurity region has a depth of 0.1 μm or less and is offset from the floating gate. On a semiconductor, a gate electrode portion having a gate oxide film, a floating gate on the gate oxide film, a control gate on the floating gate, and an oxide formed by oxidizing the floating gate and the control gate is formed. Forming
Adding an impurity to the semiconductor using the gate electrode portion as a mask to form an impurity region,
The method for manufacturing a semiconductor device, wherein the impurity region has a depth of 0.1 μm or less and a roundabout to the gate electrode portion is 50 nm or less.   The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the impurity is As.   5. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity is P. 6.   7. The method for manufacturing a semiconductor device according to claim 1, wherein the floating gate and the control gate are formed using phosphorus-doped polycrystalline silicon.   The method for manufacturing a semiconductor device according to claim 1, wherein polycrystalline or single-crystal silicon is used for the semiconductor.   The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein wafer-like single crystal silicon is used for the semiconductor.   The method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device is an EPROM.   10. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is an EEPROM.   10. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a flash memory.

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