JP2004296756A - Double-sided printed wiring board and its manufacturing method - Google Patents
Double-sided printed wiring board and its manufacturing method Download PDFInfo
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- JP2004296756A JP2004296756A JP2003086664A JP2003086664A JP2004296756A JP 2004296756 A JP2004296756 A JP 2004296756A JP 2003086664 A JP2003086664 A JP 2003086664A JP 2003086664 A JP2003086664 A JP 2003086664A JP 2004296756 A JP2004296756 A JP 2004296756A
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Abstract
Description
【０００１】
【発明が属する技術分野】
本発明は、両面プリント配線板及びその製造方法に関するものである。
【０００２】
【従来の技術】
プリント配線板のスルーホール部の導通処理には従来、無電解銅めっき及び電解銅めっきにて両面の銅はく面の全面に導通化処理が行われている。しかし、プリント基板の軽薄短小化により回路形成の細線形成が必要となっている。そのためには、スルーホールとその周辺部分のみを選択的にめっきする製造方法が行われるようになっている。
しかしながら、電解銅めっきにおいては、スルーホールとその周辺部分のみの銅めっきを行う場合、全面めっきと比較して極端にめっき面積が少なく、プリント配線板の個々のスルーホールでめっき厚さが安定しないため、導体層間の接続信頼性が劣る、あるいは回路形成工程においての感光性ドライフィルムレジスト（以下ＤＦＲと言うことがある）とプリント配線板の間に気泡が残り、エッチング処理の際に導体間導体残りとなる不具合が起こることがあった。
さらにＤＦＲの面積及び面付け等の要因によって、スルーホールのめっき厚さが極端に変動するため、個々の製品ごとに電流値条件を評価して、試行錯誤によって、条件を決定する必要があった。
【０００３】
これらの問題に対して、スルーホールとその周辺部分のめっき厚さを精度よく制御することで、導体層間の接続信頼性や、回路作成工程での歩留まりを向上させ、さらに細線形成が容易なめっき技術が望まれていた。
【０００４】
【発明が解決しようとする課題】
本発明は、スルーホールとその周辺部分のみを選択的に電解銅めっきするプリント配線板の製造において、スルーホール周辺のめっき厚さを精度よく制御することで、回路形成時の導体間導体残りを改善し、高精細な回路形成が可能なプリント配線板及びその製造方法を提供するものである。
【０００５】
【課題を解決するための手段】
本発明は、
（１）両面プリント配線板の導体回路及びスルーホール部に銅めっきを付ける方法であって、銅めっきの不要部分をめっきレジストでマスクする工程と、導体回路及びスルーホール部の必要とする部分に銅めっきを付ける工程と、前記めっきレジストを除去する工程を含む両面プリント配線板のスルーホールめっき方法において、前記めっき工程の電気めっき電流値の設定を以下の式によって得られた電流値でめっきすることを特徴とする両面プリント配線板の製造方法、
Ｘ＝Ｙ（ａ−ｂＺ）
Ｘ：電気銅めっきの電流値、Ｙ：回路基板の全面積（ｄｍ２）、Ｚ（部分めっき比率）：部分めっき面積（ｄｍ２）÷Ｙ、ａ：０．６５〜０．７５、ｂ：０．５８〜０．６２
（２）めっきマスク境界線とスルーホール部は、１０ｍｍ以上の距離とし、部分めっき比率を０．４〜０．９とする１項記載の両面プリント配線板の製造方法、
（３）１項又は２項の製造方法によって、スルホール部に銅めっきを１０〜２０μｍ析出させた両面プリント配線板、
である。
【０００６】
【発明の実施の形態】
以下に、本発明について説明する。
メッキレジストによるマスクはスルーホール及びスルーホール周辺のみに選択的にめっき処理するために銅めっき不要部分を被覆するものであり、種々の工法が実用化されており特には限定しないが、好ましくは光硬化性の樹脂を用いてスルーホールと高精度に位置あわせすることが望ましい。
【０００７】
電気銅めっきの電流値は
Ｘ＝Ｙ（ａ−ｂＺ）
Ｘ：電気銅めっきの電流値、Ｙ：回路基板の全面積（ｄｍ２）、Ｚ（部分めっき比率）：銅めっき不要部分の面積（ｄｍ２）÷Ｙ、ａ：０．６５〜０．７５、ｂ：０．５８〜０．６２ である、ａおよびｂがこの範囲を外れると、析出被膜の光沢、物性が著しく低下するので好ましくない。
【０００８】
めっきマスク境界線とスルーホール穴迄の距離は、１０ｍｍ以上であり、より好ましくは１５ｍｍ以上である。めっきマスク境界線とスルーホール穴迄の距離が１０ｍｍ未満では、めっき時電流密度が安定せず、１０〜２０μｍの範囲内で精度良くめっき厚さの制御をすることができない。
【０００９】
部分めっき比率は、０．４〜０．９とすることが好ましい。この範囲を外れると基板全面にめっきを析出させる工法との電流値の差が大きすぎるため、めっき設備の専用化が必要となり生産性が悪い。
【００１０】
スルーホール穴加工後にスルーホール内壁の導通処理を行う工法としては無電解銅めっき法、ダイレクトめっき法等数々の処理方法が実用化されているが特に限定しない。
【００１１】
本発明の工法により、銅めっきを安定して析出させることができるが、導体層間の接続信頼性及び後工程である回路作成工程でのドライフィルムレジストの埋め込み性を考慮し、めっき析出厚さは１０〜２０μｍとすることが好ましい。１０μｍ未満だとプリント基板へ加熱冷却などの使用環境中での導体層間の接続信頼性が劣り、２０μｍを越えると基板内のスルーホール周辺のめっき析出部と他の領域での厚み違いが大きいため、回路作成工程でのドライフィルムレジストと基板の間に気泡が形成され、エッチング処理工程で導体間導体残りが発生しやすい。
【００１２】
【実施例】
本発明を以下の実施例で具体的に説明する。
基板のサイズが５００ｍｍ×４７５ｍｍの両面銅張り板の場合、基板の全面積Ｙは、５００×４７５×２＝４７５０００ｍｍ２÷１００００＝４７．５ｄｍ２となる。この基板の銅めっき不要部の面積が３０．０ｄｍ２であるので、部分めっき比率Ｚは、Ｚ＝（３０．０／４７．５）＝０．６３となる。部分めっき比率として好ましい値は、０．４〜０．９の範囲であるので、０．６３は適正範囲内である。よって、関係式に当てはめると、
Ｘ＝Ｙ（ａ−ｂＺ）Ｘ＝４７．５×（０．７０−０．６０×０．６３）
＝１５．３
このとき、ａ＝０．７０、ｂ＝０．６０とする。
したがって、当基板の設定電流値は、１５．３Ａとなる。
当基板を電流値１５．３Ａにて銅めっきを行ったときのスルーホールのめっき厚さは、平均１６．４μｍとなり、最小値１１．０μｍ及び最大値１８．７μｍとなり上記の関係式を適用することでスルーホールめっき厚さ１０〜２０μｍに設定可能であった。
【００１３】
【発明の効果】
本発明は、プリント配線板において、スルーホールとその周辺のみを選択的に且つ１０〜２０μｍの範囲内で厚さ精度良く銅めっきを析出させることが可能なため、プリント配線板における細線回路の形成が容易となり、さらに導体層間の接続信頼性に優れたプリント配線板を得ることができる。
【図面の簡単な説明】
【図１】本発明のめっきマクス境界線とスルーホール穴の位置関係を示す図である。
【符号の説明】
１：めっきマスク境界線
２：スルーホール部
３：プリント配線板
４：めっきマスク
５：めっきマスク境界線とスルーホール部の距離が、１０ｍｍ以上離れている[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a double-sided printed wiring board and a method for manufacturing the same.
[0002]
[Prior art]
Conventionally, in the conduction treatment of the through-hole portion of the printed wiring board, the conduction treatment is performed on the entire surface of the copper foil on both sides by electroless copper plating and electrolytic copper plating. However, thinner and thinner printed circuit boards have necessitated the formation of fine lines for circuit formation. To this end, a manufacturing method of selectively plating only the through hole and its peripheral portion is performed.
However, in electrolytic copper plating, when copper plating is performed only on the through hole and its peripheral portion, the plating area is extremely small as compared with the entire surface plating, and the plating thickness is not stable in each through hole of the printed wiring board. Therefore, the connection reliability between the conductor layers is poor, or bubbles remain between the photosensitive dry film resist (hereinafter, sometimes referred to as DFR) and the printed wiring board in the circuit forming process, and the conductors between the conductors remain during the etching process. There was a problem that occurred.
Furthermore, the plating thickness of the through-hole fluctuates extremely due to factors such as the area and imposition of the DFR. Therefore, it was necessary to evaluate the current value condition for each product and determine the condition by trial and error. .
[0003]
To solve these problems, by precisely controlling the plating thickness of the through hole and its surroundings, it is possible to improve the connection reliability between the conductor layers and the yield in the circuit creation process, and to make the plating easier to form fine wires. Technology was desired.
[0004]
[Problems to be solved by the invention]
The present invention provides a method for manufacturing a printed wiring board in which only a through hole and a peripheral portion thereof are selectively electrolytically plated with copper, by accurately controlling a plating thickness around the through hole to reduce a conductor-to-conductor residual during circuit formation. An object of the present invention is to provide a printed wiring board capable of forming a high-definition circuit, and a method of manufacturing the same.
[0005]
[Means for Solving the Problems]
The present invention
(1) A method of applying copper plating to a conductor circuit and a through-hole portion of a double-sided printed wiring board, wherein a step of masking an unnecessary portion of the copper plating with a plating resist and a portion where the conductor circuit and the through-hole portion are required In a through-hole plating method for a double-sided printed wiring board including a step of applying copper plating and a step of removing the plating resist, the electroplating current value in the plating step is plated with a current value obtained by the following equation. A method for producing a double-sided printed wiring board,
X = Y (a-bZ)
X: current value of electrolytic copper plating, Y: total area of circuit board (dm 2 ), Z (partial plating ratio): partial plating area (dm 2 ) ÷ Y, a: 0.65 to 0.75, b: 0.58-0.62
(2) The method for producing a double-sided printed wiring board according to (1), wherein a distance between the plating mask boundary line and the through-hole portion is 10 mm or more, and a partial plating ratio is 0.4 to 0.9.
(3) A double-sided printed wiring board in which copper plating is deposited in a through-hole portion by 10 to 20 μm by the production method according to
It is.
[0006]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described.
The mask made of a plating resist covers portions that do not require copper plating in order to selectively plate only the through holes and the periphery of the through holes, and various methods have been put into practical use. It is desirable to position the through hole with high precision using a curable resin.
[0007]
The current value of the electrolytic copper plating is X = Y (a-bZ)
X: current value of copper electroplating, Y: total area of circuit board (dm 2 ), Z (partial plating ratio): area of unnecessary copper plating (dm 2 ) 不要 Y, a: 0.65 to 0.75 , B: 0.58 to 0.62 If a and b are out of this range, the gloss and physical properties of the deposited film are unpreferably reduced.
[0008]
The distance between the plating mask boundary line and the through-hole is at least 10 mm, and more preferably at least 15 mm. If the distance between the plating mask boundary line and the through-hole hole is less than 10 mm, the current density during plating is not stable, and the plating thickness cannot be accurately controlled within the range of 10 to 20 μm.
[0009]
The partial plating ratio is preferably set to 0.4 to 0.9. Outside of this range, the difference between the current value and the method of depositing plating over the entire surface of the substrate is too large, so that dedicated plating equipment is required and productivity is poor.
[0010]
Various processing methods such as electroless copper plating and direct plating have been put into practical use as a method of conducting the conduction of the inner wall of the through hole after the through hole processing, but are not particularly limited.
[0011]
By the method of the present invention, copper plating can be deposited stably, but in consideration of the connection reliability between conductor layers and the embedding property of a dry film resist in a circuit forming process which is a subsequent process, the plating deposition thickness is The thickness is preferably 10 to 20 μm. If the thickness is less than 10 μm, the connection reliability between conductor layers in a use environment such as heating and cooling the printed circuit board is inferior. If the thickness exceeds 20 μm, the thickness difference between a plating deposition portion around a through hole in the substrate and other areas is large. Air bubbles are formed between the dry film resist and the substrate in the circuit forming process, and the conductor-to-conductor residue tends to be generated in the etching process.
[0012]
【Example】
The present invention is specifically described in the following examples.
In the case of a double-sided copper-clad board with a substrate size of 500 mm × 475 mm, the total area Y of the substrate is 500 × 475 × 2 = 475000 mm 2 ÷ 10000 = 47.5 dm 2 . Since the area of the copper plating unnecessary portion of this substrate is 30.0 dm 2 , the partial plating ratio Z is Z = (30.0 / 47.5) = 0.63. Since the preferable value of the partial plating ratio is in the range of 0.4 to 0.9, 0.63 is within an appropriate range. Therefore, when applied to the relational expression,
X = Y (a−bZ) X = 47.5 × (0.70−0.60 × 0.63)
= 15.3
At this time, a = 0.70 and b = 0.60.
Therefore, the set current value of this substrate is 15.3 A.
The plating thickness of the through-hole when the substrate is plated with a current of 15.3 A is 16.4 μm on average, 11.0 μm minimum and 18.7 μm maximum, and the above relational expression is applied. Thus, the through-hole plating thickness could be set to 10 to 20 μm.
[0013]
【The invention's effect】
According to the present invention, it is possible to selectively deposit only a through hole and its periphery in a printed wiring board and to deposit copper plating with a high precision within a range of 10 to 20 μm. And a printed wiring board having excellent connection reliability between conductor layers can be obtained.
[Brief description of the drawings]
FIG. 1 is a diagram showing a positional relationship between a plating max boundary line and through-hole holes according to the present invention.
[Explanation of symbols]
1: Plating mask boundary line 2: Through hole portion 3: Printed wiring board 4: Plating mask 5: Distance between plating mask boundary line and through hole portion is 10 mm or more
Claims (3)
Ｘ＝Ｙ（ａ−ｂＺ）
Ｘ：電気銅めっきの電流値、Ｙ：回路基板の全面積（ｄｍ２）、Ｚ（部分めっき比率）：銅めっき不要部の面積（ｄｍ２）÷Ｙ、ａ：０．６５〜０．７５、ｂ：０．５８〜０．６２This is a method of applying copper plating to a conductor circuit and a through-hole portion of a double-sided printed wiring board, wherein a step of masking an unnecessary portion of the copper plating with a plating resist, and applying a copper plating to a portion where the conductor circuit and the through-hole portion are required. Attaching step and a through-hole plating method for a double-sided printed wiring board including a step of removing the plating resist, wherein the setting of the electroplating current value in the plating step is performed by plating with a current value obtained by the following equation. Method for manufacturing a double-sided printed wiring board.
X = Y (a-bZ)
X: current value of copper electroplating, Y: total area of circuit board (dm 2 ), Z (partial plating ratio): area of unnecessary portion of copper plating (dm 2 ) ÷ Y, a: 0.65 to 0.75 , B: 0.58 to 0.62
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003086664A JP2004296756A (en) | 2003-03-27 | 2003-03-27 | Double-sided printed wiring board and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003086664A JP2004296756A (en) | 2003-03-27 | 2003-03-27 | Double-sided printed wiring board and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2004296756A true JP2004296756A (en) | 2004-10-21 |
Family
ID=33401229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003086664A Pending JP2004296756A (en) | 2003-03-27 | 2003-03-27 | Double-sided printed wiring board and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2004296756A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113355709A (en) * | 2020-03-04 | 2021-09-07 | 北大方正集团有限公司 | Plating capability evaluation method, plating method and device |
-
2003
- 2003-03-27 JP JP2003086664A patent/JP2004296756A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113355709A (en) * | 2020-03-04 | 2021-09-07 | 北大方正集团有限公司 | Plating capability evaluation method, plating method and device |
| CN113355709B (en) * | 2020-03-04 | 2024-04-16 | 北大方正集团有限公司 | Electroplating capability assessment method, electroplating method and device |
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