JP2004288943A - Process for fabricating ferroelectric capacitor, process for fabricating ferroelectric memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for fabricating a ferroelectric capacitor having good characteristics. <P>SOLUTION: The process for fabricating a ferroelectric capacitor consisting of a first electrode 20, a ferroelectric film 30, and a second electrode 40 comprises a step for performing heat treatment after the second electrode 40 is formed at least on the ferroelectric film 30, and a step for performing polarization of the ferroelectric film 30 by applying a specified voltage at least between the first electrode 20 and the second electrode 40. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a ferroelectric capacitor and a method for manufacturing a ferroelectric memory.
[0002]
[Background Art]
In recent years, attention has been paid to a semiconductor device such as a ferroelectric memory including a ferroelectric capacitor utilizing spontaneous polarization of a ferroelectric thin film. Among them, a technique for performing a polarization process in a ferroelectric thin film forming process has been proposed in order to improve the hysteresis characteristics of a ferroelectric capacitor, but further improvement in characteristics is desired.
[0003]
[Patent Document 1]
JP 2000-68467 A
[Problems to be solved by the invention]
An object of the present invention is to provide a method for manufacturing a ferroelectric capacitor having good characteristics.
[0005]
It is another object of the present invention to provide a method of manufacturing a ferroelectric memory using the method of manufacturing a ferroelectric capacitor of the present invention.
[0006]
[Means for Solving the Problems]
A method of manufacturing a ferroelectric capacitor according to the present invention is a method of manufacturing a ferroelectric capacitor including a first electrode, a ferroelectric film, and a second electrode, wherein at least the second electrode is provided on the ferroelectric film. Performing a heat treatment after forming the electrode; and performing a polarization treatment on the ferroelectric film by applying a given voltage between at least the first electrode and the second electrode after the heat treatment. Including.
[0007]
According to the present invention, by performing a polarization process by applying a voltage between the first electrode and the second electrode, it is possible to precisely control an electric field applied to the ferroelectric film for the polarization process. it can. According to the present invention, the polarization treatment can be performed after the second electrode is formed and subjected to the heat treatment, that is, in a state where the defect density at the interface between the ferroelectric film and the second electrode is reduced. A ferroelectric capacitor having excellent hysteresis characteristics can be obtained.
[0008]
The present invention can adopt the following various aspects.
[0009]
(A) The heat treatment can be performed after processing at least one of the ferroelectric film and the second electrode into a desired shape.
[0010]
During processing such as patterning, a layer to be etched and its surrounding layers may have undesirable effects on their characteristics. Therefore, in the present invention, after at least one of the second electrode and the ferroelectric film is processed into a desired shape, heat treatment is performed to reduce defects and the like of the ferroelectric film, and then polarization processing is performed. Polarization can be performed on a favorable crystal state in which the defect density of the ferroelectric film is reduced. Therefore, according to the present invention, a ferroelectric capacitor having excellent hysteresis characteristics can be obtained.
[0011]
In addition, by improving the crystalline state of the ferroelectric film by heat treatment, a short circuit between the first and second electrodes due to a defect such as a pinhole in the ferroelectric film is less likely to occur. Therefore, according to the present invention, it is possible to improve the handleability of the device when probing is performed during the polarization process.
[0012]
(B) performing the heat treatment after performing at least processing of dividing the second electrode into a plurality of pieces, and performing the polarization processing by disposing a conductor that interconnects the plurality of second electrodes on the plurality of second electrodes; It can be performed by applying a given voltage between the conductor and the first electrode.
[0013]
According to such an embodiment, for example, in a configuration in which a plurality of ferroelectric capacitors are arranged on the same base, the third electrodes interconnecting the second electrodes of the ferroelectric capacitors make the capacitors uniform in each capacitor. And an electric field can be applied thereto, and the polarization process can be simplified.
[0014]
(C) The heat treatment can be performed in an oxygen atmosphere.
[0015]
According to such an embodiment, oxygen vacancies in the ferroelectric film can be replenished during the heat treatment, and the ferroelectric film can be restored to a favorable crystalline state.
[0016]
(D) The present invention can be applied to a method for manufacturing a ferroelectric memory, including the method for manufacturing a ferroelectric capacitor described above. In such a case, it is desirable to perform the step so that the heat load in the step after the polarization treatment is equal to or lower than the phase transition temperature (Curie temperature) of the ferroelectric film. In this manner, the phase transition of the ferroelectric film in the capacitor once subjected to the polarization treatment to the paraelectric substance can be prevented, and the hysteresis characteristic improved by the polarization treatment can be maintained in the subsequent steps. .
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0018]
(1st Embodiment)
FIG. 1 is a diagram schematically illustrating an example of a manufacturing process of the ferroelectric capacitor according to the first embodiment of the present invention.
[0019]
First, as shown in FIG. 1A, a given substrate 10 is prepared.
[0020]
The material of the base 10 can be selected from known substrate materials. For example, a semiconductor substrate such as silicon, a glass substrate, a resin substrate, or the like can be used.
[0021]
Next, as shown in FIG. 1B, a lower electrode (first electrode) 20, a ferroelectric film 30, and an upper electrode (second electrode) 40 are sequentially stacked on the base 10.
[0022]
The lower electrode 20 and the upper electrode 40 can be formed by using a known film forming method such as a sputtering method. The material of the lower electrode 20 and the upper electrode 40 can be appropriately selected from, for example, known conductive materials. For example, Pt, Ir, Ir oxide (IrO _x ), Ti, Ti oxide (TiO _x) ), Ru, Ru oxide (RuO _x ), SrRu composite oxide (SrRuO _x ), and the like. In addition, the lower electrode 20 and the upper electrode 40 can be composed of a single-layer film made of the material exemplified above and a multilayer film including a plurality of layers.
[0023]
The ferroelectric film 30 is formed of a composite oxide such as SBT (Strontium Bismuth Tantalates), PZT (Lead Zirconate Titanate), BIT (Bismuth Titanate), and BLT (Bismuth Lanthanum). As a method for forming the ferroelectric film 30, a suitable method can be selected from known methods and used, for example, a solution coating method (including a sol-gel method and a MOD (Metal Organic Decomposition) method) and a sputtering method. Or a CVD (Chemical Vapor Deposition) method (including a MOCVD (Metal Organic Chemical Vapor Deposition) method).
[0024]
In addition, the fatigue characteristics of the ferroelectric film 30 change depending on the state of the interface between the lower electrode 20 and the upper electrode 40 formed adjacently above and below the ferroelectric film 30. That is, if the state of the interface with the electrode is not good, the ferroelectric material is deteriorated by the electric field repeatedly applied during use, and eventually loses the ferroelectric characteristics. Also, according to a film forming method such as a sputtering method in which high-energy particles collide with the upper electrode 40, the ferroelectric film 30 may be damaged. For this reason, in the manufacturing process according to the present embodiment, a heat treatment is performed in a state where the upper electrode 40 is formed, and a process for restoring the crystal state of the ferroelectric film 30 is performed. Such a heat treatment is desirably performed in an oxygen atmosphere. In this manner, oxygen vacancies generated in the ferroelectric film 30 during the formation of the upper electrode or during the heat treatment can be supplemented, and the ferroelectric film 30 can be recovered to a more favorable crystalline state.
[0025]
Here, in a state where the ferroelectric film 30 is formed, as shown in FIG. 1B, the direction of polarization of the composite oxide crystal forming the ferroelectric film 30 is random. If the direction of polarization remains random, it is difficult to obtain desired ferroelectric characteristics. Therefore, in the manufacturing process of the present embodiment, as shown in FIG. 1C, a voltage source 50 is connected between the lower electrode 20 and the upper electrode 40 to apply a given voltage to perform a polarization process. . Then, the polarization of the composite oxide crystal forming the ferroelectric film 30 is oriented almost uniformly in the direction of the applied electric field. Note that the direction in which the polarization of the composite oxide crystal is oriented can be arbitrarily set by controlling the polarity of the voltage applied in the polarization process. Further, the voltage applied in the polarization processing may be any of a direct current and an alternating current (including a sine wave, a square wave pulse, and a triangular wave pulse).
[0026]
As described above, according to the manufacturing process of the present embodiment, the polarization process is performed by applying a voltage between the lower electrode 20 and the upper electrode 40, so that the polarization process is performed on the ferroelectric film 30. The applied electric field can be precisely controlled. Further, according to the manufacturing process of the present embodiment, after the upper electrode 40 is formed and heat-treated, that is, the defect density at the interface between the ferroelectric film 30 and the lower electrode 20 and the upper electrode 40 is reduced. Since the polarization treatment can be performed in a proper crystal state, a ferroelectric capacitor having excellent hysteresis characteristics can be obtained.
[0027]
Hereinafter, examples of the manufacturing process according to the present embodiment will be described.
[0028]
In the present embodiment, a silicon (Si) substrate was used as the base 10.
[0029]
Then, titanium (Ti) was formed to a thickness of 20 nm on the silicon substrate by a sputtering method, and the titanium film was heat-treated in an oxygen atmosphere at 650 ° C. to form a titanium oxide (TiO _x ) film. Subsequently, platinum (Pt) was formed with a thickness of 200 nm by a sputtering method to form a lower electrode 20 composed of a laminated film of a titanium oxide film and a platinum film.
[0030]
Next, a PZT film was formed as a ferroelectric film 30 on the platinum film by a solution coating method. The PZT film has a ratio of the constituent elements of Pb, Zr, and Ti of 110: 30: 70, and has a thickness of 200 nm and is crystallized by a heat treatment at 600 ° C. for 1 minute in an oxygen atmosphere.
[0031]
Next, a platinum film was formed on the PZT film as the upper electrode 40 to have a thickness of 200 nm by a sputtering method. After forming this platinum film, a heat treatment is performed in an oxygen atmosphere at 700 ° C. for 30 minutes to compensate for oxygen deficiency in the PZT film near the upper platinum film and to arrange the constituent elements at the interface between the PZT film and the platinum film. And the crystal orientation was improved. FIG. 2 shows the result of X-ray diffraction of the ferroelectric capacitor after the heat treatment. According to FIG. 2, a steep peak of PZT is observed around 38 deg, and a steep peak of platinum is observed near 40 deg, confirming that each layer of the capacitor is in a sufficiently good crystalline state.
[0032]
Next, a voltage of 5 V was applied between the lower electrode 20 and the upper electrode 40 for 10 seconds to perform a polarization process on the PZT film.
[0033]
FIG. 3 shows the hysteresis characteristics measured for the ferroelectric capacitor thus obtained and the ferroelectric capacitor not subjected to polarization processing. According to FIG. 3, it was confirmed that the ferroelectric capacitor of the present example subjected to the polarization treatment had a higher polarization value and a hysteresis shape with good squareness was obtained.
[0034]
(Second embodiment)
FIGS. 4A to 4C are diagrams schematically illustrating an example of a manufacturing process of the ferroelectric memory according to the second embodiment of the present invention. Members having substantially the same functions as those described in the first embodiment are denoted by the same reference numerals, and detailed description is omitted.
[0035]
In this embodiment, a substrate in which a transistor 16 is formed over a semiconductor substrate 11 is used. The transistor 16 includes a source / drain 13, a gate insulating film 14, and a gate electrode 15. In addition, a plug electrode 17 for making an electrical connection with a ferroelectric capacitor is formed on one of the source / drain 13. The transistor 16 can be formed using a known semiconductor formation technique. Further, in addition to the above, the base 10 may include an element isolation region 12 for isolating each transistor and an interlayer insulating film 18.
[0036]
In the manufacturing process of the present embodiment, a lower electrode (first electrode) 20, a ferroelectric film 30, and an upper electrode (second electrode) 40 are formed on the base 10 as shown in FIG. Laminate sequentially.
[0037]
Next, as shown in FIG. 4B, the lower electrode 20, the ferroelectric film 30, and the upper electrode 40 are etched and patterned into a desired shape. As a patterning technique, a known technique can be used. After the patterning, the device is subjected to a heat treatment in an oxygen atmosphere or the like to improve the crystal state of the ferroelectric film 30 and the interface state between the ferroelectric film 30 and each electrode to a good state. Then, as in the case of the first embodiment, a polarization process is performed on the ferroelectric film 30 by applying a given voltage to the lower electrode 20 and the upper electrode 40 using the voltage source 50. . Thus, the ferroelectric capacitor including the lower electrode 20, the ferroelectric film 30, and the upper electrode 40 has good hysteresis characteristics, as in the first embodiment.
[0038]
Finally, as shown in FIG. 4C, a hydrogen barrier film 60 made of, for example, an alumina film is formed on the capacitor by, for example, a sputtering method, and an interlayer insulating film made of, for example, a silicon oxide film is formed. 70 is formed using, for example, a TEOS-CVD method. Then, wiring layers 81 and 82 for connecting the upper electrode 40 of the capacitor and the source / drain 13 of the transistor 16 to the outside are formed, so that a ferroelectric memory can be obtained. In the manufacturing process of the present embodiment, the phase transition temperature (Curie temperature) of the ferroelectric film 30 in order to maintain the characteristics of the capacitor in the process after the polarization process on the ferroelectric film 30 is performed. It is preferable to select a process that results in a thermal load in the following.
[0039]
According to the manufacturing process of the present embodiment, the ferroelectric capacitor included in the ferroelectric memory has good hysteresis characteristics as in the case of the first embodiment. Obtainable.
[0040]
In this embodiment, the case where the plug electrode 17 is used to connect the source / drain 13 of the transistor 16 and the lower electrode 20 of the capacitor has been described. However, the present invention is not limited to this. A configuration in which the / drain 13 and the upper electrode 40 of the capacitor are connected by a wiring layer is also applicable.
[0041]
(Third embodiment)
FIG. 5 is a diagram schematically showing a ferroelectric memory formed in a manufacturing process according to the third embodiment of the present invention. Members having substantially the same functions as those described in the second embodiment are denoted by the same reference numerals, and detailed description is omitted.
[0042]
As shown in FIG. 5, the ferroelectric memory includes a memory cell array 100 formed so that a lower electrode 20 and an upper electrode 40 intersect, and peripheral circuits 210 and 220. In the memory cell array 100, a ferroelectric capacitor is formed in a region where the lower electrode 20 and the upper electrode 40 intersect and used as a memory cell. Further, the peripheral circuit sections 210 and 220 include various circuits for selectively writing or reading information to or from the memory cell array 100, and further include a signal detection circuit (not shown) such as a sense amplifier. Can be configured. The peripheral circuits 210 and 220 can be formed by using a known semiconductor element forming technique.
[0043]
Further, the memory cell array 100 and the peripheral circuits 210 and 220 can be formed on different regions of the semiconductor substrate 11 as shown in FIG. Hereinafter, a specific manufacturing process of the memory cell array 100 including the ferroelectric capacitor structure will be described.
[0044]
7A to 7D are diagrams schematically showing a manufacturing process of the memory cell array 100 according to the present embodiment.
[0045]
First, as shown in FIG. 7A, a lower electrode (first electrode) 20 is formed on the base 10 by using, for example, a sputtering method, and is patterned into a stripe shape composed of a plurality of lines.
[0046]
Next, as shown in FIG. 7B, a ferroelectric film 30 is formed by a solution coating method or the like. Subsequently, an upper electrode (second electrode) 40 is formed by, for example, a sputtering method or the like, and the upper electrode 40 is patterned into a stripe shape crossing the lower electrode 20. As a result, a ferroelectric capacitor is formed in a region where the lower electrode 20 and the upper electrode 40 intersect. In this step, the ferroelectric film 30 may be patterned according to the shape of the upper electrode 40.
[0047]
Next, a heat treatment is performed on the device to recover the crystal state of the ferroelectric film 30 and the interface state between the ferroelectric film 30 and each electrode. Subsequently, as shown in FIG. 7C, a voltage source 50 is connected between the lower electrode 20 and the upper electrode 40 to apply a given voltage to the ferroelectric film 30 to perform a polarization process. I do. Thereby, the direction of polarization of the composite oxide crystal constituting the ferroelectric film 30 is oriented substantially uniformly.
[0048]
Finally, as shown in FIG. 7D, a memory cell array 100 can be obtained by forming a hydrogen barrier film 60 and an interlayer insulating film 70 above the capacitor. As described above, also in the manufacturing process of the present embodiment, the same effects as in the case of the second embodiment can be obtained.
[0049]
(Fourth embodiment)
FIGS. 8A to 8E are diagrams schematically showing a manufacturing process of the memory cell array of the ferroelectric memory according to the fourth embodiment of the present invention. The basic structure of the ferroelectric memory formed in this embodiment is the same as that described in the third embodiment, but the structure of the memory cell array is different. Therefore, members having substantially the same functions as those described in the third embodiment are denoted by the same reference numerals, detailed description thereof will be omitted, and major differences from the third embodiment will be described. Will be described.
[0050]
First, as shown in FIG. 8A, a lower electrode (first electrode) 20 is formed on a base 10, a ferroelectric film 30, and an intermediate electrode (second electrode) 42 are formed. The manufacturing process of the present embodiment is characterized in that a given voltage is applied between the lower electrode 20 and the intermediate electrode 42 to perform a polarization process on the ferroelectric film 30. That is, when the intermediate electrode 42 is laminated on the base 10, the device is subjected to a heat treatment in an oxidizing atmosphere, and then the polarization process is performed using the voltage source 50.
[0051]
Next, as shown in FIG. 8B, the lower electrode 20, the ferroelectric film 30, and the intermediate electrode 42 are patterned in the same pattern in a stripe shape. Subsequently, as shown in FIG. 8C, a hydrogen barrier film 60 and an interlayer insulating film 70 are formed, and thereafter, as shown in FIG. 8D, the interlayer insulating film 70 is etched to expose the intermediate electrode 42. Let it. Note that the etching of the interlayer insulating film 70 may be performed at least to such a depth that the lower electrode 20 is not exposed. Finally, a memory cell array can be obtained by providing a metal wiring to be the upper electrode 40 on the intermediate electrode 42 and patterning it in a stripe shape so as to cross the lower electrode 20.
[0052]
Note that, in the manufacturing process of the present embodiment, the polarization treatment can be performed using the following method.
[0053]
FIG. 9 is a diagram schematically showing a modification of the manufacturing process of the present embodiment.
[0054]
First, after forming the lower electrode 20, the ferroelectric film 30, and the intermediate electrode 42 as shown in FIG. 9A, the ferroelectric film 30 and the intermediate electrode 42 are formed as shown in FIG. Only the same pattern is patterned in a stripe pattern. Thereafter, a heat treatment is performed on the device in an oxidizing atmosphere to recover the crystal state and the like of the ferroelectric film 30.
[0055]
Then, as shown in FIG. 9C, a conductor 90 for interconnecting the intermediate electrodes 42 divided by patterning is placed on the intermediate electrode 42, and the conductor 90 and the lower electrode 20 are placed between the conductor 90 and the lower electrode 20. First, the polarization process is performed on the ferroelectric film 30 using the voltage source 50.
[0056]
Thereafter, as shown in FIG. 9D, the lower electrode 20 is patterned into the same stripe shape as the ferroelectric film 30 and the intermediate electrode. In the subsequent steps, a memory cell array can be obtained by using the method described in this embodiment.
[0057]
Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the invention.
[Brief description of the drawings]
FIG. 1 is a view schematically showing a manufacturing process of a ferroelectric capacitor according to a first embodiment.
FIG. 2 is a diagram for explaining an example of the first embodiment.
FIG. 3 is a diagram for explaining an example of the first embodiment.
FIG. 4 is a view schematically showing a manufacturing process of the ferroelectric memory according to the second embodiment.
FIG. 5 is a plan view schematically showing a ferroelectric memory according to a third embodiment.
FIG. 6 is a sectional view schematically showing a ferroelectric memory according to a third embodiment.
FIG. 7 is a view schematically showing a manufacturing process of the ferroelectric memory according to the third embodiment.
FIG. 8 is a view schematically showing a manufacturing process of the ferroelectric memory according to the fourth embodiment.
FIG. 9 is a view schematically showing a modification of the manufacturing process of the ferroelectric memory according to the fourth embodiment.
[Explanation of symbols]
Reference Signs List 10 base, 20 lower electrode, 30 ferroelectric film, 40 upper electrode, 50 voltage source

Claims (5)

A method for manufacturing a ferroelectric capacitor comprising a first electrode, a ferroelectric film, and a second electrode,
Performing a heat treatment at least after forming the second electrode on the ferroelectric film;
Performing a polarization process on the ferroelectric film by applying a given voltage between at least the first electrode and the second electrode after the heat treatment;
A method for manufacturing a ferroelectric capacitor, comprising: In claim 1,
The method of manufacturing a ferroelectric capacitor, wherein the heat treatment is performed after at least one of the ferroelectric film and the second electrode is processed into a desired shape. In claim 1,
The heat treatment is performed after at least processing of dividing the second electrode into a plurality of pieces,
The polarization process is performed by disposing a conductor interconnecting the plurality of second electrodes on a plurality of the second electrodes and applying a given voltage between the conductor and the first electrode. And a method of manufacturing a ferroelectric capacitor. In any one of claims 1 to 3,
The method of manufacturing a ferroelectric capacitor, wherein the heat treatment is performed in an oxygen atmosphere. A method for manufacturing a ferroelectric memory, comprising the method for manufacturing a ferroelectric capacitor according to claim 1.

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