JP2004272448A - Memory control device and memory control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To change each storage area in a memory to a power-saving mode while retaining data continuously located in a plurality of storage areas in the memory. <P>SOLUTION: When data 41-44 stored in banks #1-#4 in an SDRAM 2 are used in a predetermined processing mode of CPU 11, a data transfer means 7 outputs a data address signal 17 for relocation of data to an access means 10 according to a relocation address signal 4 from a storage means 6. The access means 10 performs DMA transfer according to the data address signal 17, and collects the data 41-44 in the SDRAM 2 to a RAM 3. Further, according to a power-saving control signal 20, the four banks #1-#4 are changed to the power-saving mode. Thereafter, an address conversion means 9 converts the relocation address signal 4 to a converted address signal 21 every memory access from the CPU 11 according to the relocation address signal 4. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory control device and a memory control method that control a memory that is divided into a plurality of storage areas and that can be selectively used for each storage area.
[0002]
[Prior art]
Conventionally, an SDRAM (Synchronous Dynamic Random Access Memory) has been known as one of the synchronous memories that are this type of memory. The SDRAM has a storage area divided into a plurality of banks, and each bank can be selectively used. When a conventional memory controller selects and controls each bank in the SDRAM, for example, by stopping supply of a clock to a bank that is not currently being used or by shifting to a self-refresh mode, a low memory is used. The power consumption is reduced (for example, see Patent Document 1).
[0003]
In addition, the SDRAM is controlled so that a storage area storing image data is set to a power down mode (power saving mode), while a storage area not storing image data is not set to a power down mode. There is also known a memory control device capable of setting and releasing the power-down mode efficiently (for example, see Patent Document 2).
[0004]
[Patent Document 1]
JP 2000-339216 A [Patent Document 2]
JP-A-8-63391
[Problems to be solved by the invention]
However, the above-mentioned conventional memory control device has the following problems, and improvement thereof has been demanded. That is, when shifting to the power saving mode for each bank, such as stopping supply of a clock for each bank or shifting to the self-refresh mode for each bank, the corresponding bank is not used (accessed) in the current processing mode of the CPU. However, in SDRAM, data is often arranged continuously in a plurality of banks in order to avoid a delay in access. For this reason, power saving control for shifting to the power saving mode for each bank cannot be efficiently performed.
[0006]
Therefore, the present invention provides a memory control device and a memory control method that can shift to a power saving mode for each storage area while retaining data continuously arranged in a plurality of storage areas in the memory. The purpose is to:
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a memory control device of the present invention is a memory control device which is divided into a plurality of storage areas and controls a memory which can be selected and used for each storage area. Storage means for storing relocation information for relocating data stored in the area, and transferring the data stored in the predetermined storage area to another storage area based on the stored relocation information. Data transfer means for relocating data, address translation means for translating an address before the data relocation to an address after the relocation, and storing the data based on the converted address after the relocation. Access means for accessing the another storage area.
[0008]
Further, according to the memory control method of the present invention, in a memory control method for controlling a memory which is divided into a plurality of storage areas and is selectively used for each storage area, the data stored in a predetermined storage area in the memory is provided. A storage step of storing relocation information for relocating the data, transferring the data stored in the predetermined storage area to another storage area based on the stored relocation information, and relocating the data. A data transfer step to be performed; an address conversion step of converting an address before relocation of the data to an address after relocation; and the other storage in which the data is stored based on the converted address after relocation. Access step for accessing the area.
[0009]
As a result, it is possible to shift to the power saving mode for each storage area while holding data continuously arranged in a plurality of storage areas in the memory.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of a memory control device and a memory control method according to the present invention will be described with reference to the drawings.
[0011]
[First Embodiment]
FIG. 1 is a block diagram illustrating a configuration of the memory control device according to the first embodiment. The memory control device 1 of this embodiment includes a storage unit 6, a data transfer unit 7, a power saving control signal generation unit 8, an address conversion unit 9, and an access unit 10. Further, the CPU 11, the RAM 3, and the SDRAM (synchronous dynamic RAM) 2 are connected to the memory control device 1. The SDRAM 2 has a storage area divided into four banks # 1 to # 4, and each bank can be selectively used. For example, when each of the banks # 1 to # 4 of the SDRAM 2 is selected and controlled, it is possible to stop the clock supply to a bank that is not currently used or to shift to the self-refresh mode.
[0012]
FIG. 2 is a diagram showing the rearrangement information stored in the storage unit 6. The storage means 6 stores address information 30 before relocation, address information 31 after relocation, and bank memory selection information 32 in the form of a table as relocation information for relocating data between the SDRAM 2 and the RAM 3. I have. The pre-relocation address information 30, the post-relocation address information 31, and the bank memory selection information 32 are set in the storage unit 6 according to the table setting signal 13 from the CPU 11. The pre-relocation address information 30 and the post-relocation address information 31 in the storage means 6 are referred to as necessary and read out as the relocation address signal 4. Similarly, the bank memory selection information 32 is Read as signal 5.
[0013]
The data transfer means 7 outputs a data address signal 17 for relocating data between a specific bank of the SDRAM 2 and the RAM 3 to the access means 10 based on the relocation address signal 4 from the storage means 6. After the data is rearranged between the specific bank of the SDRAM 2 and the RAM 3, the power saving control signal generating means 8 shifts the specific bank of the SDRAM 2 and the RAM 3 selected by the bank memory selection signal 5 to the power saving mode. The power saving control signal 20 for access to the access means 10. Further, the address conversion means 9 converts the address signal 14 from the CPU 11 to the memory control device 1 into a converted address signal 21 based on the rearranged address signal 4 from the storage means 6 and outputs the converted address signal 21 to the access means 10.
[0014]
The access unit 10 rearranges data between a specific bank of the SDRAM 2 and the RAM 3 based on the data address signal 17 from the data transfer unit 7. Further, based on the power saving control signal 20 from the power saving control signal generating means 8, the selected bank of the selected SDRAM 2 and the RAM 3 are shifted to the power saving mode. Further, based on the converted address signal 21 from the address conversion means 9, the data signal 15 and the command signal 16 are accessed to a specific bank of the SDRAM 2 and the RAM 3.
[0015]
Here, the storage unit 6 corresponds to the storage unit described in claim 1. The data transfer means 7 and the access means 10 correspond to the data transfer means according to the first aspect. The address conversion means 9 corresponds to the address conversion means according to the first aspect. The access unit 10 corresponds to the access unit according to the first aspect. The power saving control signal generating means 8 and the access means 10 correspond to the power saving control means according to claim 5.
[0016]
FIG. 3 is a flowchart showing a data relocation processing procedure in the memory control device 1. First, when the table setting signal 13 is output from the CPU 11 to the memory control device 1, the memory control device 1, based on the table setting signal 13, stores the pre-relocation address information 30, the post-relocation address information 31 and the bank memory The selection information 32 is set in the storage means 6 (step S1).
[0017]
Thereafter, when a start signal / end signal 12 from the CPU 11 which is issued in response to the start of the predetermined processing mode is input, the data transfer unit 7 in the memory control device 1 relocates the data from the storage unit 6. Based on the address signal 4, a data address signal 17 for relocating data between a specific bank of the SDRAM 2 and the RAM 3 is output to the access means 10 (step S2). The access means 10 performs direct data transfer (DMA transfer) between a specific bank of the SDRAM 2 and the RAM 3 in accordance with a data address signal from the data transfer means 7. As a result, data stored in all the banks # 1 to # 4 in the SDRAM 2 or the selected bank is transferred and stored in a predetermined area of the RAM 3.
[0018]
When the direct data transfer is completed, the power-saving control signal generating means 8 performs power-saving control for shifting a specific bank of the SDRAM 2 to the power-saving mode after the rearrangement according to the bank / memory selection signal 5 from the storage means 6. The signal 20 is output to the access means 10 (step S3). The access unit 10 shifts all the banks # 1 to # 4 of the SDRAM 2 or the selected bank to the power saving mode according to the power saving control signal 20.
[0019]
FIG. 4 is a diagram showing an arrangement of data stored in the banks # 1 to # 4 of the SDRAM 2 and the RAM 3. FIG. 2A shows the arrangement of data stored in the SDRAM 2 and the RAM 3 before the rearrangement. For example, it is assumed that, in a predetermined processing mode of the CPU 11, data 41 of the bank # 1, data 42 of the bank # 2, data 43 of the bank # 3, and data 44 of the bank # 4 in the SDRAM 2 are used (accessed). I do. FIG. 3B shows the arrangement of data stored in the SDRAM 2 and the RAM 3 after the rearrangement. In the process of step S2 described above, the data 41 to 44 stored in the banks # 1 to # 4 of the SDRAM 2 are rearranged so that the data 41 to 44 are collected in the storage area of the RAM 3. Will no longer have data used in this processing mode. As a result, in the process of step 3, the clock supplied to all the banks # 1 to # 4 of the SDRAM 2 is stopped, and control for shifting to the power saving mode such as shifting to the self-refresh mode can be performed.
[0020]
Then, the power saving control signal 20 is output from the power saving control signal generating means 8 to the access means 10, and all the banks # 1 to # 4 of the SDRAM 2 shift to the power saving mode. Until the signal / end signal 12 is output, the address conversion means 9 in the memory control device 1 responds to the access to the SDRAM 2 and the RAM 3 by the address signal 14 from the outside (CPU 11) from the storage means 6 The address after the rearrangement is determined based on the signal 4 and is output to the access unit 10 as the converted address signal 21. The access unit 10 accesses the SDRAM 2 and the RAM 3 according to the converted address signal 21. Thus, the CPU 11 can access the SDRAM 2 and the RAM 3 at the same physical address as before the data relocation.
[0021]
FIG. 5 is a flowchart showing a data arrangement return processing procedure in the memory control device 1. When a start signal / end signal 12 issued in response to the end of a predetermined processing mode of the CPU 11 is input from the CPU 11 to the memory control device 1, the memory control device 1 rearranges based on the table setting signal 13. The pre-relocation address information 30, the post-relocation address information 31, and the bank / memory selection information 32 are set in the storage means 6 as information (step S11). The pre-relocation address information 30, the post-relocation address information 31, and the bank memory selection information 32 are information for returning the data arrangement to the original state. For example, the information is obtained by replacing the pre-relocation address information and the post-relocation address information for each bank or memory specified by the bank / memory selection information 32.
[0022]
The power saving control signal generating means 8 sets all the banks # 1 to # 4 of the SDRAM 2 which have shifted to the power saving mode or the selected bank to the normal mode according to the bank / memory selection signal 5 from the storage means 6. It is returned (step S12). This cancels the setting of the power saving mode. Then, the data transfer means 7 outputs the data address signal 17 for returning the data between the specific bank of the SDRAM 2 and the RAM 3 to the original arrangement to the access means 10 according to the relocation address signal 4 (step S13). . The access means 10 returns the arrangement of the data stored in the specific bank of the SDRAM 2 and the RAM 3 to the state before the rearrangement in accordance with the data address signal 17.
[0023]
In this way, the data stored in all the banks # 1 to # 4 of the SDRAM 2 or the selected bank is rearranged, and the data to be used exists in all the banks or the selected bank in the SDRAM 2. By shifting this storage area to the power saving mode after it has been exhausted, many banks can be shifted to the power saving mode, and the efficiency of power saving can be increased. Further, since address conversion is performed in the memory control device 1 for access from the outside (CPU 11) to the SDRAM 2, memory access can be performed from the outside (CPU 11) at the same physical address as before the rearrangement.
[0024]
[Second embodiment]
In the first embodiment, the RAM 3 is used for data relocation. In the second embodiment, a case where data relocation is performed only by the SDRAM 2 is shown. The same parts as those in the first embodiment will be described with the same reference numerals.
[0025]
FIG. 6 is a diagram showing an arrangement of data stored in banks # 1 to # 4 of the SDRAM 2 in the second embodiment. FIG. 2A shows the arrangement of data stored in the SDRAM 2 before the rearrangement. FIG. 2B shows the arrangement of data stored in the SDRAM 2 after the rearrangement. For example, when only data 51 of bank # 1, data 52 of bank # 2, data 53 of bank # 3 and data 54 of bank # 4 in the SDRAM 2 are used in a predetermined processing mode of the CPU 11, these data By rearranging the data so that the banks 51 to 54 are collected in the bank # 1, the remaining banks # 2 to # 4 are not used in this processing mode after the rearrangement. As a result, it is possible to control the remaining banks # 2 to # 4 that are not used to shift to the power saving mode, such as shifting to the self-refresh mode and stopping the clock supply.
[0026]
According to the memory control device 1 of the present embodiment, data can be rearranged using a specific bank in the SDRAM 2 or the RAM 3 as another memory, and is not used in the current processing mode of the CPU 11. It is possible to easily specify a bank or a memory that can be shifted to the power saving mode. Then, it is possible to control such a bank or memory to shift to a power saving mode, such as stopping clock supply for each bank or memory, or shifting to a self-refresh mode. Further, since the address is converted in the memory control device 1 in response to the access from the CPU 11, the memory access can be performed to the bank of the SDRAM 2 with the same physical address as before the rearrangement. Further, by performing the data rearrangement operation in accordance with the switching of the specific processing mode of the CPU 11, further power saving can be achieved.
[0027]
In the above embodiment, when data is rearranged using the RAM 3, the entire SDRAM 2 is shifted to the power saving mode after all the banks # 1 to # 4 in the SDRAM 2 are not used. Of course, after at least one bank in the SDRAM 2 is no longer used, only that bank may be shifted to the power saving mode.
[0028]
Further, in the above embodiment, the memory control device 1 has the storage unit 6 built therein. However, an external memory may be provided instead of the storage unit 6, and the relocation information may be set in the external memory. Thus, the circuit scale of the memory control device can be reduced.
[0029]
Furthermore, in step S11 of the above-described embodiment, a case has been described in which, after data relocation, relocation information that returns to the original data location is set in the storage unit 6 in accordance with the table setting signal 13 from the CPU 11. For example, without resetting according to the table setting signal 13 from the CPU 11, the original arrangement information is temporarily saved in the stack memory, and the original arrangement saved when the original data arrangement is restored. It may be replaced with information.
[0030]
Further, in the above-described embodiment, the case where the SDRAM is used as the synchronous memory has been described. However, the present invention is not limited to this. For example, an SGRAM (synchronous graphic RAM) may be used.
[0031]
Further, in the above embodiment, each time the predetermined processing mode by the CPU 11 ends, the mode is returned from the power saving mode to the normal mode and the data arrangement is returned to the original state. When the storage area of the memory has room, the data stored in each bank in the SDRAM used in the next processing mode is rearranged without returning the data arrangement to the original state. It is also possible to shift the unused bank in the power saving mode to the power saving mode.
[0032]
【The invention's effect】
According to the present invention, it is possible to shift to the power saving mode for each storage area while holding data continuously arranged in a plurality of storage areas in the memory.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a memory control device according to a first embodiment.
FIG. 2 is a diagram showing rearrangement information stored in a storage unit 6;
FIG. 3 is a flowchart showing a data relocation processing procedure in the memory control device 1;
FIG. 4 is a diagram showing an arrangement of data stored in banks # 1 to # 4 of an SDRAM 2 and a RAM 3;
FIG. 5 is a flowchart illustrating a data arrangement return processing procedure in the memory control device 1;
FIG. 6 is a diagram showing an arrangement of data stored in banks # 1 to # 4 of the SDRAM 2 in the second embodiment.
[Explanation of symbols]
1 memory controller 2 SDRAM
3 RAM
6 storage means 7 data transfer means 8 power saving control signal generating means 9 address conversion means 10 access means 11 CPU
41-44, 46, 51-54 Data

Claims (14)

In a memory control device that is divided into a plurality of storage areas and controls a memory that can be selected and used for each storage area,
Storage means for storing relocation information for relocating data stored in a predetermined storage area in the memory,
Data transfer means for transferring data stored in the predetermined storage area to another storage area based on the stored relocation information, and performing data relocation;
Address conversion means for converting an address before the data relocation to an address after the data relocation,
Access means for accessing the other storage area in which the data is stored, based on the converted address after the rearrangement;
A memory control device comprising: 2. The data transfer unit according to claim 1, wherein the data transfer unit transfers data stored in the predetermined storage area in the memory to the other storage area in the memory, and relocates the data. Memory control unit. When controlling the memory and the other memory having the other storage area, the data transfer unit transfers the data stored in the predetermined storage area in the memory to the other storage in the other memory. 2. The memory control device according to claim 1, wherein the data is transferred to an area and data is rearranged. 2. The memory control device according to claim 1, wherein the relocation information includes address information before relocation, address information after relocation, and selection information of the predetermined storage area. 2. A power saving control means for controlling a transition of the predetermined storage area in the memory to a power saving mode after the data transfer means rearranges the data. Memory controller. The data transfer means performs the data rearrangement in response to a start signal from a CPU, and returns the data arrangement to a state before the rearrangement in response to an end signal from the CPU. The memory control device according to claim 1, wherein 2. The data according to claim 1, wherein the data stored in a predetermined area in the memory, wherein the rearrangement is performed according to a processing mode of the CPU, is data used in the processing mode of the CPU. Memory control unit. In a memory control method for controlling a memory which is divided into a plurality of storage areas and is selectively used for each storage area,
A storage step of storing relocation information for relocating data stored in a predetermined storage area in the memory,
A data transfer step of transferring data stored in the predetermined storage area to another storage area based on the stored relocation information, and relocating the data;
An address conversion step of converting an address before relocation of the data to an address after relocation,
Accessing the other storage area in which the data is stored based on the converted address after the rearrangement. 9. The data transfer method according to claim 8, wherein in the data transfer step, data stored in the predetermined storage area in the memory is transferred to the other storage area in the memory, and data is rearranged. Memory control method. When controlling the memory, and another memory having the other storage area, the data transfer step includes transferring the data stored in the predetermined storage area in the memory to the other storage in the other memory. 9. The memory control method according to claim 8, wherein the data is transferred to an area and the data is rearranged. 9. The memory control method according to claim 8, wherein the relocation information includes address information before relocation, address information after relocation, and selection information of the predetermined storage area. 9. The method according to claim 8, further comprising: a power saving control step of performing a control for shifting the predetermined storage area in the memory to a power saving mode after the data is rearranged in the data transfer step. Memory control method. In the data transfer step, the data is rearranged in response to a start signal from a CPU, and the data arrangement is returned to a state before the rearrangement in response to an end signal from the CPU. 9. The memory control method according to claim 8, wherein: 9. The data according to claim 8, wherein the data stored in a predetermined area in the memory, wherein the rearrangement is performed according to a processing mode of the CPU, is data used in the processing mode of the CPU. Memory control method.

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