JP2012256263A - Power control method, electronic apparatus, program and generation method of program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption by memory.SOLUTION: A processor 2 controls power control states of plural memory areas 3a,3b to which functions in a program executed by the processor 2 are allocated and which have the power control states of a normal state and a power-saving state, so that, during the execution of a function fa arranged in a memory area 3a, the memory area 3a is put into the power-saving state and the memory area 3b is put into the normal state immediately before a function fb arranged in a memory area 3b is invoked.

Description

  The present invention relates to a power control method, an electronic apparatus, a program, and a program generation method.

  In a system having a processor and a memory, a method is known in which the processor controls the operation of the memory so as to reduce the power consumption of the memory in accordance with the contents of a program supplied to the processor. In particular, a memory control method for reducing the power consumption of an SOC (System On Chip) in which a system having a processor and a memory is mounted on a single semiconductor chip is drawing attention.

  For example, a method is known in which an OS (Operating System) examines the allocation and release status of a memory area of a main memory for an application program and controls the power supply to the main memory according to the status of the memory area.

  There is also known a method of dividing a source program by extracting each phase in units of loops and reference data referenced in each phase. In this method, a memory area required for storing reference data of each phase is distributed to a cache memory in the processor and an on-chip memory outside the processor to reduce power.

  In addition, a call graph that represents the call relationship between instructions from the source program is created and classified into frequently used instruction groups and other instruction groups, and the frequently used instruction groups are always supplied with power. A method of arranging in (memory bank) is known. By this method, a situation in which the memory bank as the power supply destination is frequently switched is avoided, and efficient power control is achieved.

JP-A-9-212416 JP 2008-102733 A JP 2010-257437 A

However, in the conventional method, depending on the structure of the program, the memory area that can save power is limited, and the effect of reducing power consumption may be reduced.
For example, in a method of arranging a frequently used instruction group in a memory bank to which power is always supplied, a less frequently used instruction group is arranged in a memory bank in which power control is performed in a power saving state and a normal state. In this method, a memory bank that has been once changed from a power saving state to a normal state for execution of a certain function is set to a normal state until the execution of the function is completed. Therefore, the memory bank in which the caller function is placed remains in a normal state while a function placed in another memory bank is called and executed when a certain function is executed. Therefore, it has been difficult to sufficiently reduce the power consumption in such a program having many calling relationships.

  According to one aspect of the invention, the following power control method is provided. In this power control method, a function in a program executed by a processor is assigned, and a first memory area is arranged in a first memory area among a plurality of memory areas having a power control state of a normal state and a power saving state. When executing the function, immediately before the second function arranged in the second memory area is called, the first memory area is set to the power saving state, and the second memory area is set to the normal state. The processor controls the power control state of the plurality of memory areas.

  According to another aspect of the invention, the following program generation method is provided. The program generation method generates a program for controlling the power control state of a plurality of memory areas having a power control state of a normal state and a power saving state, and a computer performs the plurality of functions in the program. The allocation to the memory area is determined, and in the first function arranged in the first memory area among the plurality of memory areas, immediately before the call instruction of the second function arranged in the second memory area An instruction for inserting the first memory area into the power saving state and inserting the second memory area into the normal state is inserted.

  According to the disclosed power control method, electronic device, program, and program generation method, power consumption by the memory can be reduced.

It is a figure which shows an example of the electric power control method and electronic device of 1st Embodiment. It is a figure which shows an example of the electronic device of 2nd Embodiment. It is a figure which shows an example of the code | cord | chord of the program stored in the memory part. It is a figure which shows the example of the power control state of a memory bank in case a function is performed in order of func1 ()-> func2 ()-> func1 (). It is a figure which shows the example of the power control state of a memory bank in case a function is performed in order of func3 ()-> func2 ()-> func3 (). It is a figure which shows an example of the computer which produces | generates a program. It is a flowchart which shows an example of the program production | generation method. It is a flowchart which shows an example of a memory map creation process. It is a figure which shows an example of memory bank structure information. It is a figure which shows an example of a static call graph. It is a figure which shows an example of function size information. It is a flowchart which shows an example of a program division | segmentation process. It is a figure which shows an example of the table for division | segmentation work. It is a flowchart which shows an example of a recursion detection process. An example of an array variable visited [f] after initialization is shown. It is a flowchart which shows an example of the process of a subroutine A. 7 is a flowchart illustrating an example of processing of a subroutine B. It is a figure which shows the example of the static call graph containing a some recursion part. It is a figure which shows the example of the updated array variable visited [f]. It is a figure which shows the example of the array variable visited [f] updated to the function f9a. It is a figure which shows the example by which the array variable visited [f] in the function f9a was changed. It is a flowchart which shows an example of a division | segmentation process. It is a figure which shows the example of an update of the table for division | segmentation work. It is a figure which shows the example of the table for a division | segmentation operation | work after the division process performed after the detection of the 1st recursive part. It is a figure which shows the example of the updated array variable visited [f]. It is a figure which shows the example of the division | segmentation work table output by the process of step S79. It is a figure which shows the example of division | segmentation information. It is a flowchart which shows an example of the division plan creation process of a recursive part. It is a figure which shows the example of the division information containing a division plan. It is a figure which shows the example of table tbl1. It is a figure which shows the example of table tbl2. It is a flowchart which shows an example of a function allocation process. It is a figure which shows an example of the variable m_rest [M] after initialization. It is a figure which shows an example of the division information after initialization. It is a figure which shows an example of the allocation information at the time of initialization. It is a figure which shows the example of an update of allocation information. It is a figure which shows the example of an update of division | segmentation information. It is a figure which shows the example of the allocation information output. It is a flowchart which shows an example of an address calculation process. It is a figure which shows an example of the memory map output. It is a flowchart which shows an example of a power control code insertion process. It is a flowchart which shows an example of the function allocation process in 3rd Embodiment. It is a figure which shows an example of the division information after initialization. It is a figure which shows the example of an update of division | segmentation information. It is a figure which shows the example of an update of allocation information. It is a flowchart which shows an example of the function allocation process in 4th Embodiment. It is a figure which shows an example of a quick reference table. It is a figure which shows the example of an update of a quick reference table. It is a flowchart which shows the example of a quick reference table preparation process. It is a flowchart which shows the example of the update process of a quick reference table.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of a power control method and an electronic apparatus according to the first embodiment.

  The power control method of the first embodiment is executed by an electronic device 1 as shown in FIG. The electronic device 1 includes a processor 2 and a plurality of memory areas 3a and 3b. Functions in a program executed by the processor 2 are assigned to the memory areas 3a and 3b.

  Here, it is assumed that the function fa arranged in the memory area 3a includes a call instruction to the function fb arranged in the memory area 3b. When executing the program including such functions fa and fb, the processor 2 executes power control as shown in the flowchart of FIG. 1, for example.

  Note that the power control states of the memory areas 3a and 3b include a normal state and a power saving state. The normal state is a power control state when, for example, writing or reading to the memory areas 3a and 3b is performed, and the power saving state is, for example, for holding the contents stored in the memory areas 3a and 3b. In this state, a voltage lower than the normal state is applied.

When the function fa is executed, it is assumed that the power control state of the memory area 3a is a normal state and the power control state of the memory area 3b is a power saving state.
When the execution of the function fa is started, the processor 2 sets the memory area 3a to the power saving state and makes the memory area 3b transition to the normal state immediately before the call instruction of the function fb (step S1).

Since the processing of the function fa is interrupted when the function fb is executed, the power consumption of the electronic device 1 can be reduced by setting the memory area 3a to the power saving state.
When a call instruction to the function fb is executed during the execution of the function fa (step S2), the execution of the function fb assigned to the memory area 3b in the normal state is started (step S3).

  After that, the processor 2 changes the memory area 3a to the normal state immediately before returning to the function fa (just before the end of the function fb) (step S4). When the execution of the function fb is completed, a return to the function fa is performed (step S5).

When the function fa is restored, the processor 2 shifts the memory area 3b to the power saving state (step S6).
Thereafter, the remaining processing of the function fa is executed (step S7), and the execution of the function fa ends.

  Note that the instruction for performing the process of step S1 is described in the function fa, for example, immediately before the instruction for calling the function fb. Further, the instruction for performing the process of step S4 is described in the function fb, for example, immediately before the end instruction of the function fb. Further, the instruction for performing the process of step S6 is described in the function fa, for example, immediately after the calling instruction for the function fb. Details will be described later.

When the processor 2 executes such a program including the functions fa and fb, the power control method as described above is executed.
According to the power control method as described above, the memory area to which the caller function is assigned is set to the power saving state when the callee function is executed, and the memory area in which the function execution is suspended is set to the power saving state. It is said. As a result, even when a program having a lot of calling relationships is executed, the power consumption by the memory areas 3a and 3b can be reduced, and as a result, the low power consumption electronic device 1 can be obtained.

(Second Embodiment)
FIG. 2 is a diagram illustrating an example of an electronic device according to the second embodiment.
The electronic device 50 is, for example, a memory device, a semiconductor device such as an SOC (System On Chip), or a computer.

The electronic device 50 includes a memory unit 10, a processor 20, a control register unit 30, a power control unit 40, a bus 41, and a power supply line 42.
The memory unit 10 is an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory) or the like, and includes a plurality of memory banks 11-0, 11-1, 11-2, 11-3,. Have. The memory banks 11-0 to 11-n function as the instruction code memory 12 or the data memory 13. The memory banks 11-0 to 11-n are connected to the processor 20 via the bus 41.

  The processor 20 is, for example, a CPU (Central Processing Unit), a DSP (Digital Signal Processor), and the like, and includes a processor core 21 and a memory controller 22. The processor core 21 uses the memory controller 22 to control writing or reading of data or instruction codes to the memory banks 11-0 to 11-n.

  The control register unit 30 stores the power control state of the memory banks 11-0 to 11-n according to the power supply control signal from the processor 20. The control register unit 30 includes, for example, a plurality of registers c0, c1, c2, c3,..., Cn that store the power control states of the memory banks 11-1 to 11-n.

  For example, as shown in FIG. 2, when "1" is set in the registers c0 and c2 and "0" is set in the subsequent registers c1 and c3 to cn, the memory bank 11- The power control state of 0, 11-2 becomes the normal state, and the power control state of the memory banks 11-1, 11-3 to 11-n becomes the power saving state.

  The power control unit 40 includes power control circuits 40-0, 40-1, 40-2, 40-3,..., 40-n connected between the memory banks 11-0 to 11-n and the power supply line 42. is doing. The power control circuits 40-0 to 40-n control the power supply states of the memory banks 11-0 to 11-n according to signals from the control register unit 30. The power supply state includes, for example, a power-off state, a power saving supply state, and a normal power supply state.

  In the power-off state, the connection between the power supply line 42 and each of the memory banks 11-0 to 11-n is disconnected. In the power saving supply state, the power from the power supply line 42 is supplied to the memory banks 11-0 to 11-n with a reduced voltage. In the normal power supply state, the power from the power supply line 42 is supplied to the memory banks 11-0 to 11-n while maintaining the voltage.

  In the power-off state, no data is held, and neither reading nor writing is performed in each of the memory banks 11-0 to 11-n. In the power saving supply state, data is held in each of the memory banks 11-0 to 11-n. In the normal power supply state, data retention, reading, or writing is performed in each of the memory banks 11-0 to 11-n.

  Note that, when “0” is set in the control register unit 30, any one of the power-off state and the power-saving supply state among the above-described power states is, for example, the power control circuits 40-0 to 40-. determined by n.

In such an electronic device 50, for example, the following program is stored in the memory unit 10.
FIG. 3 is a diagram illustrating an example of program codes stored in the memory unit.

  In the example of FIG. 3, func1 (), func2 (), and func3 () are shown as functions. In the example of FIG. 3, the number of memory banks 11-0 to 11-n is eight (that is, n = 7).

  func1 () includes a call instruction (call func2 ()) of func2 () and is arranged in the memory bank 11-1. Further, func1 has an instruction to change the power control state of the memory bank 11-1 to the power saving state and to change the power control state of the memory bank 11-2 to the normal state immediately before the calling instruction of func2 (). Power control code). In addition, immediately after the call instruction, a power control code for transitioning the power control state of the memory banks 11-2 to 11-7 to the power saving state is described.

  func2 () called in func1 is arranged in the memory bank 11-2. In func2, a power control code for shifting the power control state of the memory banks 11-1 and 11-3 including the calling instruction of func2 to the normal state immediately before “end function” indicating the end of func2 (). Is described.

  func3 includes a call instruction of func2 () and is arranged in the memory bank 11-3. Furthermore, in func3, immediately before the call instruction to func2 (), the power control for changing the power control state of the memory bank 11-3 to the power saving state and for changing the power control state of the memory bank 11-2 to the normal state. The code is written. In addition, immediately after the call instruction, a power control code for transitioning the power control state of the memory banks 11-1, 11-2, 11-4 to 11-7 to the power saving state is described.

The electronic device 50 performs power control of the memory banks 11-0 to 11-n by executing the program as described above.
Hereinafter, an example of a power control method by the electronic device 50 when the program shown in FIG. 3 is executed will be described.

FIG. 4 is a diagram illustrating an example of a power control state of the memory bank when functions are executed in the order of func1 () → func2 () → func1 ().
FIG. 4 shows the power control state of the memory banks 11-0 to 11-7 when each code of the program is executed. Memory bank numbers 0 to 7 indicate memory banks 11-0 to 11-7, respectively.

  Note that the main function is arranged in the memory bank 11-0, and the power control state is always the normal state. In FIG. 4, when func1 is executed for the first time, the power control states of the memory banks 11-2 to 11-7 other than the memory banks 11-0 and 11-1 are in the power saving state. To do. That is, the registers c0 to c7 of the control register unit 30 shown in FIG.

  During the execution of func1 () by the processor 20, the power control state of the memory bank 11-1 is changed to the power saving state immediately before the call instruction of func2 (), and the power control state of the memory bank 11-2 is changed to the normal state. The power control code for making a transition to is executed. At this time, the processor 20 rewrites the registers c0 to c7 of the control register unit 30 as “10100000”. As a result, when the call instruction of func2 () is executed, the power control state of the memory bank 11-1 becomes the power saving state, and the power control state of the memory bank 11-2 becomes the normal state.

  The execution of func2 () proceeds, and immediately before the end, the power control code for shifting the memory banks 11-1 and 11-3 to the normal state is executed. At this time, the processor 20 rewrites the registers c0 to c7 of the control register unit 30 as “11110000”. As a result, at the end of func2 () (when returning to func1 ()), the power control state of the memory banks 11-0 to 11-3 becomes the normal state, and the power of the memory banks 11-4 to 11-7 The control state remains in the power saving state. By doing so, the problem of accessing the memory bank in the power saving state does not occur even if it returns to either func1 () or func3 () without referring to the execution status.

  After the return to func1 (), the power control code for changing the power control state of the memory banks 11-2 to 11-7 to the power saving state immediately after the call instruction of func2 () is executed in func1 (). . At this time, the processor 20 rewrites the registers c0 to c7 of the control register unit 30 as “11000000”. As a result, the power control states of the memory banks 11-2 to 11-7 other than the memory banks 11-0 and 11-1 become the power saving state. Since information indicating that the function has been returned to func1 () has been added, it is possible to increase the number of memory banks in the power saving state.

FIG. 5 is a diagram illustrating an example of the power control state of the memory bank when functions are executed in the order of func3 () → func2 () → func3 ().
Similarly to FIG. 4, the power control states of the memory banks 11-0 to 11-7 at the time of executing each code of the program are shown. Memory bank numbers 0 to 7 indicate memory banks 11-0 to 11-7, respectively. Similarly to FIG. 4, the main function is arranged in the memory bank 11-0, and the power control state is always the normal state.

  In FIG. 5, when func3 is executed for the first time, the power control states of the memory banks 11-1, 11-2, 11-4 to 11-7 other than the memory banks 11-0 and 11-3 are omitted. Assume that it is in a power state. That is, the registers c0 to c7 of the control register unit 30 shown in FIG. 2 are “10010000”.

  At the time of execution of func3 () by the processor 20, the power control state of the memory bank 11-2 is changed to the normal state immediately before the call instruction of func2 (), and the power control state of the memory bank 11-3 is changed to the power saving state The power control code for making a transition to is executed. At this time, the processor 20 rewrites the registers c0 to c7 of the control register unit 30 as “10100000”. As a result, when the call instruction of func2 () is executed, the power control state of the memory bank 11-3 becomes the power saving state, and the power control state of the memory bank 11-2 becomes the normal state.

  The execution of func2 () proceeds, and immediately before the end, the power control code for shifting the memory banks 11-1 and 11-3 to the normal state is executed. At this time, the processor 20 rewrites the registers c0 to c7 of the control register unit 30 as “11110000”. As a result, at the end of func2 () (at the time of returning to func3 ()), the power control state of the memory banks 11-0 to 11-3 becomes the normal state, and the power of the memory banks 11-4 to 11-7 The control state remains in the power saving state. By doing so, the problem of accessing the memory bank in the power saving state does not occur even if it returns to either func1 () or func3 () without referring to the execution status.

  After returning to func3 (), the power control state of the memory banks 11-1, 11-2, 11-4 to 11-7 immediately after the calling instruction of func2 () in func3 () is changed to the power saving state. The power control code to be executed is executed. At this time, the processor 20 rewrites the registers c0 to c7 of the control register unit 30 as “10010000”. As a result, the power control states of the memory banks 11-1, 11-2, 11-4 to 11-7 other than the memory banks 11-0 and 11-3 become the power saving state. Since information indicating that the function has been returned to func3 () has been added, it is possible to increase the number of memory banks in the power saving state.

  According to the power control method as described above, the memory bank to which the caller function is assigned is placed in the power saving state when the callee function is executed, and the execution of functions other than the main function is suspended. Is in a power saving state. As a result, even when a program having a lot of calling relationships, particularly a program including a structure in which a plurality of functions call the same function, is executed, the electronic device 50 can be arranged without devising arrangement of the program in the memory bank. The power consumption by the memory unit 10 can be reduced, and as a result, the low power consumption electronic device 50 can be obtained.

Next, a method for generating a program in which the power control code as shown in FIG. 3 is inserted will be described in detail.
(Program generation method)
FIG. 6 is a diagram illustrating an example of a computer that generates a program.

The entire computer 100 is controlled by a CPU 101. The CPU 101 is connected to the RAM 102 and a plurality of peripheral devices via the bus 108.
The RAM 102 is used as a main storage device of the computer 100. The RAM 102 temporarily stores at least a part of OS programs and application programs to be executed by the CPU 101. The RAM 102 stores various data used for processing by the CPU 101.

  Peripheral devices connected to the bus 108 include a hard disk drive (HDD) 103, a graphic processing device 104, an input interface 105, an optical drive device 106, and a communication interface 107.

  The HDD 103 magnetically writes and reads data to and from the built-in disk. The HDD 103 is used as a secondary storage device of the computer 100. The HDD 103 stores an OS program, application programs, and various data. Note that a semiconductor storage device such as a flash memory can also be used as the secondary storage device.

  A monitor 104 a is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 104a in accordance with a command from the CPU 101. Examples of the monitor 104a include a display device using a CRT (Cathode Ray Tube) and a liquid crystal display device.

  A keyboard 105 a and a mouse 105 b are connected to the input interface 105. The input interface 105 transmits signals sent from the keyboard 105a and the mouse 105b to the CPU 101. Note that the mouse 105b is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

  The optical drive device 106 reads data recorded on the optical disc 106a using laser light or the like. The optical disk 106a is a portable recording medium on which data is recorded so that it can be read by reflection of light. The optical disk 106a includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (ReWritable), and the like.

  The communication interface 107 is connected to the network 107a. The communication interface 107 transmits / receives data to / from other computers or communication devices via the network 107a.

With the hardware configuration as described above, the following program generation method is realized.
FIG. 7 is a flowchart illustrating an example of a program generation method.

  First, for example, when a program (source code) d1 is input to a compiler realized by the CPU 101 and compilation is performed, a program (assembly) d2 is generated as a result (step S10).

  Thereafter, the CPU 101 creates a memory map d4 based on the program d2 and the memory bank configuration information d3 including the start address and capacity of each memory bank of the electronic device incorporating the program d2 (step S11). The memory map d4 indicates which function of the program d2 is assigned to which memory bank address.

  Next, the CPU 101 inserts the power control code as described above into the program d2 based on the memory map d4, and generates a program (assembly) d5 containing the power control code (step S12).

  Subsequently, the power control code-containing program d5 is assembled by the assembler realized by the CPU 101, and a power control code-containing program (object) d6 is generated (step S13). Further, the linker realized by the CPU 101 is linked with another library such as a standard library or a numerical calculation library based on the memory map d4 to generate a program (binary) d7 containing a power control code (step S14). The program generation process ends.

Hereinafter, details of the processing of step S11 and step S12 will be described.
(Memory map creation process)
FIG. 8 is a flowchart illustrating an example of the memory map creation process.

  First, the CPU 101 creates a static call graph d10 and function size information d11 based on the program (assembly) d2 and the memory bank configuration information d3 (step S20).

FIG. 9 is a diagram illustrating an example of the memory bank configuration information.
The memory bank configuration information d3 includes information about the start address and capacity of each memory bank. For example, the start address of the memory bank with memory bank number 0 is 0x0000, and the capacity is 4.0 KB.

FIG. 10 is a diagram illustrating an example of a static call graph.
The static call graph d10 shows a function calling relationship in the program (assembly) d2. For example, it is shown that there are functions f1a and f1b as functions called by the main function (function main).

FIG. 11 is a diagram illustrating an example of function size information.
The function size information includes the code size of each function. For example, the code size of the function main is 0.1 KB, and the code size of the function f1a is 1.0 KB.

  When the static call graph d10 and the function size information d11 as described above are created, program division is performed based on these information (step S21). In the process of step S21, the CPU 101 detects and divides a function that is a recursion unit and other functions from the static call graph d10. Further, the CPU 101 calculates the total code size of each division unit, and generates division information d12 including the function and code size included in each division unit.

  Subsequently, the CPU 101 creates a recursive division proposal d13 based on the created division information d12 (step S22). In the process of step S22, the total code size of both function groups when the function group serving as the recursive part is divided into two arbitrary functions is calculated. The total code size of the two functions to be divided and both function groups obtained by the division is stored in, for example, the RAM 102 as one of the division plans d13. Details will be described later.

  Thereafter, the CPU 101 determines a function to be assigned to each memory bank of the electronic device to be controlled based on the created division information d12, division plan d13, and memory bank configuration information d3, and generates allocation information d14 ( Step S23).

  Then, the CPU 101 calculates the start address of each function based on the generated allocation information d14 and memory bank configuration information d3, and creates a memory map d4 based on the calculated start address (step S24). Thus, the memory map creation process ends.

Next, the program division process, the recursive division division plan creation process, and the function allocation process in the memory map creation process will be described in more detail.
(Program division processing)
FIG. 12 is a flowchart illustrating an example of the program dividing process.

  When the CPU 101 inputs the static call graph d10 as shown in FIG. 10 (step S30), preparation processing is performed (step S31). In the preparation process, the CPU 101 creates a division work table, which will be described later, and gives an initial value of the division name of each function. Thereafter, the CPU 101 detects a recursive function group from the static call graph d10 (step S32). When a recursive function group is detected, a dividing process is performed (step S33). In the division process, the CPU 101 divides the function group into a recursive function group and other function groups, and updates the division name of the division work table. Thereafter, the process returns to step S32.

  If no recursive function group is detected in the process of step S32, the CPU 101 generates and outputs division information d12 based on the information in the division work table at that time (step S34). Then, the program is stored in the RAM 102, and the program dividing process is terminated.

Details of steps S31, S32, and S33 in FIG. 12 will be described below.
(Preparation process)
In the preparation process in step S31 of FIG. 12, a division work table as shown below is created.

FIG. 13 is a diagram illustrating an example of the division work table.
The division work table includes a function included in the static call graph d10 and a division name for the function. In the stage of the preparation process, for example, “MAIN” is given as an initial value of the division name as shown in FIG. Although details will be described later, after being divided as a recursive part or other parts, it is changed to a different division name.

(Recursion detection processing)
FIG. 14 is a flowchart illustrating an example of the recursion detection process.
In the example shown below, an example is shown in which a function group that is recursive (closed) is detected from the static call graph d10 by depth-first search.

  For example, when the static call graph d10 and the divided work table stored in the RAM 102 are input to the CPU 101 (step S40), initialization is performed (step S41).

In the initialization process, the CPU 101 initializes an array variable visited [f] indicating whether or not the function f has been passed through the search path from the main function.
FIG. 15 shows an example of the array variable visited [f] after initialization.

In the initialization of the array variable visited [f], it is set to true when f is the function main, and is set to false otherwise.
In the initialization process, the CPU 101 empties the list-type variable PATH that stores the search path from the function main to the function f, and sets the variable flag indicating whether the recursive part has been extracted to false. To do.

  Subsequently, the CPU 101 sets the function main in the argument function f, executes the subroutine A (step S42), and uses the return value of the subroutine A (the variable flag and the function group of the recursive unit) as the recursion detection result, for example, And output to the RAM 102 (step S43).

FIG. 16 is a flowchart illustrating an example of processing of the subroutine A.
First, the CPU 101 adds the function f passed as an argument to the variable at the end of the variable PATH (step S50). Subsequently, the CPU 101 executes the subroutine B by passing each child function fc called by the function f as an argument (step S51). Thereby, the recursive part is detected. If the child function fc does not exist, nothing is performed in the process of step S51. Thereafter, the CPU 101 deletes the function f added to the last variable of the variable PATH (step S52) and returns to the flowchart of FIG.

FIG. 17 is a flowchart illustrating an example of the processing of the subroutine B.
In FIG. 17, “: =” indicates that the value on the right side is assigned (or set) to the variable on the left side, and the comparison between the value of the variable on the left side and the value on the right side is “==”. It is clearly stated. The same meaning applies to the following figures.

  First, the CPU 101 determines whether or not a variable flag indicating whether or not a recursive part has been extracted (step S60). If the variable flag is false, the process of step S61 is performed. If the variable flag is true, the process of the subroutine B ends.

  When the variable flag is false, the CPU 101 determines whether the array variable visited [fc] is true or false (step S61). If the array variable visited [fc] is false, the process of step S62 is performed, and if true, the process of step S65 is performed.

  If the array variable visited [fc] is false, the CPU 101 sets the array variable visited [fc] to true (step S62), sets the child function fc passed as an argument as the function f of the subroutine A argument, The subroutine A shown in FIG. 16 is executed (step S63).

  Thereafter, the CPU 101 sets the array variable visited [fc] of the child function fc passed as an argument to false (step S64), and returns to the subroutine A shown in FIG.

  On the other hand, if the array variable visited [fc] is true in the process of step S61, the CPU 101 indicates that the division names of the functions after the child function fc of the variable PATH are all the same except for the recursive part in the division work table. It is determined whether or not (step S65).

  When the division names of the functions after the child function fc of the variable PATH are all the same except for those indicating the recursive part, the CPU 101 extracts the function group after the child function fc of the variable PATH as a recursive part (step S66). The variable flag is set to true (step S67).

  After the process of step S67, or when there is a difference in the division names of functions after the child function fc of the variable PATH other than those indicating the recursive part, the extraction as shown in step S66 is not performed, and the subroutine A Return to.

For example, a case where the above recursion detection process is applied to a static call graph as shown below will be described.
FIG. 18 is a diagram illustrating an example of a static call graph including a plurality of recursive units.

  The static call graph d10 shown in FIG. 18 is the same as that shown in FIG. 10, but the function calling relationship is indicated by arrows. For example, an arrow indicates that the function main calls the function f1a and the function f1a calls the function f2a. Here, the portions of the functions f1a to f9a are closed circuits, which are the recursive unit 110. The parts of the functions f3b to f6b are also closed and are recursive parts 111.

Below, the example which detects the recursion part 110 by said recursion detection process is demonstrated.
After the initialization process of step S41 shown in FIG. 14, the subroutine A shown in FIG. 16 is executed with the function main as an argument (function f). At this time, in the process of step S50 of the subroutine A, the variable PATH = (main). Child functions fc of the function main are functions f1a and f1b. In the processing of step S51, when processing is performed in the order of registration of the static call graph d10 shown in FIGS. 10 and 18, first, subroutine B is executed with function f1a as an argument.

  In the subroutine B shown in FIG. 17, in step S60, the variable flag is set to false, so the process of step S61 is performed. In the process of step S61, as shown in FIG. 15, since the array variable visited [f1a] is false, the process of step S62 is performed, the array variable visited [f1a] is set to true, and the array variable is set to true. Visited [f] is updated.

FIG. 19 is a diagram illustrating an example of the updated array variable visited [f].
In the array variable visited [f] in the initial state shown in FIG. 15, the part of the array variable visited [f] related to the function f1a is false, but in the array variable visited [f] shown in FIG. 19, it is changed to true. Has been.

Thereafter, the CPU 101 passes the function f1a to the subroutine A as an argument (function f) and executes the subroutine A.
In the process of step S50 of the subroutine A, the function f1a is added to the end of the variable PATH so that the variable PATH = (main, f1a). Thereafter, since the child function fc of the function f1a is the function f2a, the subroutine B is executed with the function f2a as an argument.

  In subroutine B, in step S60, since the variable flag is false, the process of step S61 is performed. Further, in the process of step S61, as shown in FIG. 19, since the verified [f2a] is false, the process of step S62 is performed, and the verified [f2a] becomes true, and the array variable visited [f] is updated. Is done.

Thereafter, the CPU 101 passes the function f2a as an argument to the subroutine A in the process of step S63, and executes the subroutine A.
Thereafter, the same processing is repeated. The array variable visited [f] when the function f9a is passed as an argument to the subroutine B and updated by the process of step S62 is as follows.

FIG. 20 is a diagram illustrating an example of the array variable visited [f] updated up to the function f9a.
As shown in FIG. 20, the array variable visited [f] for the functions main, f1a to f9a is true.

Thereafter, the CPU 101 passes the function f9a as an argument to the subroutine A in the process of step S63, and executes the subroutine A.
In the process of step S50 of the subroutine A, the function f9a is added to the end of the variable PATH, and the variable PATH = (main, f1a, f2a, f3a, f4a, f5a, f6a, f7a, f8a, f9a). Thereafter, since the child function fc of the function f9a is the function f1a, the subroutine B is executed with the function f1a as an argument.

  In subroutine B, in step S60, since the variable flag is false, the process of step S61 is performed. Further, in the process of step S61, the array variable visited [f1a] is true as shown in FIG. 20, so the process of step S65 is performed.

  In the process of step S65, the division names of the function f1a and subsequent functions passed as arguments (child functions fc), that is, the division names of the functions f1a to f9a are all MAIN in the division work table shown in FIG. That is, the division name of the function group after the function f1a is the initial value MAIN, which indicates that it is not a recursive part, and since it is the same, the process of step S66 is performed.

  In the process of step S66, a child function fc of the variable PATH, that is, a function group after the function f1a (functions f1a, f2a, f3a, f4a, f5a, f6a, f7a, f8a, f9a) is extracted as a recursive part. The Thereafter, the variable flag is set to true in the process of step S67, the process returns to the process of subroutine A, and the process of step S52 is performed.

  In step S52, the function f at the end of the variable PATH, ie, the function f9a is deleted, and the variable PATH = (main, f1a, f2a, f3a, f4a, f5a, f6a, f7a, f8a). Thereafter, the process returns to the subroutine B, and the process of step S64 is performed. In the process of step S64, the array variable visited [f9a] for the function f9a of the child function fc is set to false.

FIG. 21 is a diagram illustrating an example in which the array variable visited [f] in the function f9a is changed.
In the array variable visited [f] shown in FIG. 20, the portion of the array variable validated [f] related to the function f9a is true, but in the array variable visited [f] shown in FIG. 21, it is changed to false. .

  Thereafter, the same processing is performed, and when the variable PATH becomes empty and the array variable validated [f] becomes false for all functions, the subroutine A ends, and the process returns to the processing flow shown in FIG. Is performed. That is, the functions f1a to f9a detected as the recursion unit and the variable flag = true are output as the recursion detection result.

Next, details of the division process in step S33 illustrated in FIG. 12 will be described.
(Division processing)
Below, the example which performs a division | segmentation process according to the recursive function list | wrist which shows the function group of the recursive part detected i-th is demonstrated.

FIG. 22 is a flowchart illustrating an example of the division process.
When the dividing process is started and, for example, a recursive function list indicating the function group of the recursive unit stored in the RAM 102 and a dividing work table are input to the CPU 101 (step S70), the counter variable j is initialized to 1. (Step S71).

  Subsequently, the CPU 101 sets the division name of the function f_i, j corresponding to the jth in the input recursive function list as Ri (step S72). Thereafter, the CPU 101 determines whether or not the counter variable j is smaller than the number n (i) of functions of the i-th recursive unit (step S73).

  If the counter variable j is smaller than n (i), the CPU 101 increments the counter variable j (step S74) and repeats the processing from step S72. When the counter variable j reaches n (i), the CPU 101 initializes the counter variable j to 1 again (step S75).

The division work table at the time of the processing in step S75 in the division processing after the detection processing of the recursive unit 110 is as follows, for example.
FIG. 23 is a diagram illustrating an example of updating the division work table.

As shown in FIG. 23, the division name of the functions f1a to f9a, which is a function group of the recursive unit 110, is changed from MAIN to R1.
After that, the CPU 101 uses the descendant functions of the function f_i, j in the recursive function list for those whose partition names in the partitioning work table are not Rj, Rk (k <j), or rk, l (l is a natural number). A division name ri, j is set (step S76). This is a function other than the child function (f_i, (j + 1)) constituting the recursion among the descendant functions of the function f_i, j, and the function whose division name has been previously set as the function of the recursive part and its function This means that the division name ri, j is given to the function excluding descendant functions.

  For example, after the recursive unit 110 is detected from the static call graph d10 illustrated in FIG. 18, the function f3b that is a descendant function of the function f2a included in the recursive unit 110 is still divided as a function of the recursive unit 111. Since no name is set, split names r1, 1 are set.

Thereafter, again, the CPU 101 determines whether or not the counter variable j is smaller than the number n (i) of functions of the i-th recursive unit (step S77).
If the counter variable j is smaller than n (i), the CPU 101 increments the counter variable j (step S78) and repeats the processing from step S76. When the counter variable j reaches n (i), the CPU 101 outputs a division work table (step S79), stores it in the RAM 102, for example, and finishes the division process in step S33.

The division work table when the counter variable j reaches n (i) is, for example, as follows.
FIG. 24 is a diagram illustrating an example of a division work table after division processing performed after detection of the first recursive part.

  For the functions f3b, f4b, f5b, f5d, f6b, and f7b, which are descendant functions of the function f2a included in the recursive unit 110, split names r1 and 1 are set. The division names r1 and 2 are set for the functions f5c, f6c, f7c, and f8c that are descendant functions of the function f4a included in the recursive unit 110. For the function f7d, which is a descendant function of the function f7a included in the recursive unit 110, split names r1 and 3 are set.

When such division processing is performed, the recursion detection processing in step S32 in FIG. 12 is performed again.
Below, the example which detects the recursive part 111 of the static call graph d10 shown in FIG. 18 is demonstrated.

  Similar to the detection of the recursion unit 110, the processes shown in FIGS. 14, 16, and 17 are performed. Processing proceeds in the same manner as described above, and variable PATH = (main, f1a, f2a, f3a, f4a, f5a, f6a, f7a, f8a, f9a), and subroutine B related to function f1a passed as an argument is executed. In the determination in step S61 of the subroutine B, since the array variable visited [f1a] is true, the process of step S65 is executed.

  In the processing of step S65, the CPU 101 refers to the division work table as shown in FIG. Here, all the division names after the function f1a of the variable PATH are R1. Since the division name R1 indicates the recursive unit 110, the process of the subroutine B ends, the process returns to the subroutine A, and the process of step S52 is performed.

  In step S52, the function f at the end of the variable PATH, ie, the function f9a is deleted, and the variable PATH = (main, f1a, f2a, f3a, f4a, f5a, f6a, f7a, f8a). Thereafter, the process returns to the subroutine B, and the process of step S64 is performed. In the process of step S64, the array variable visited [f9a] for the function f9a of the child function fc is set to false.

  Thereafter, similarly, the process of step S52 of the subroutine A is performed, the function f8a at the end of the variable PATH is deleted, and the variable PATH = (main, f1a, f2a, f3a, f4a, f5a, f6a, f7a). Thereafter, the process of step S64 of the subroutine B is performed. In the process of step S64, the array variable visited [f8a] for the function f8a of the child function fc is set to false.

  Subsequently, in step S51 of the subroutine A, the function f7d, which is another child function fc of the function f7a, is passed as an argument to the subroutine B, and the subroutine B is executed.

  In subroutine B, in step S60, since the variable flag is false, the process of step S61 is performed. In the process of step S61, since the search for the function f7d has not been performed so far, the array variable visited [f7d] is false. Thereby, the process of step S62 is performed, the array variable validated [f7d] is set to true, and the array variable validated [f] is updated.

FIG. 25 is a diagram illustrating an example of the updated array variable visited [f].
In the array variable validated [f] in FIG. 25, the portion of the array variable validated [f] related to the function f7d is changed to true.

Thereafter, in the process of step S63, the subroutine A is executed with the function f7d as an argument.
In the process of step S50 of the subroutine A, the function f7d is added to the end of the variable PATH, and the variable PATH = (main, f1a, f2a, f3a, f4a, f5a, f6a, f7a, 7d). Thereafter, since the child function fc of the function f7d does not exist, the subroutine B of step S51 is not executed, the processing of step S52 is executed, and the variable PATH = (main, f1a, f2a, f3a, f4a, f5a, f6a, f7a). )

Subsequently, returning to the process of step S64 of the subroutine B, the array variable validated [f7d] for the function f7d is set to false.
Thereafter, the process returns to step S52 of the subroutine A, the function f7a at the end of the variable PATH is deleted, and the variable PATH = (main, f1a, f2a, f3a, f4a, f5a, f6a).

Thereafter, when the same processing proceeds, in step S51 of the subroutine A, the subroutine B having the function f3b, which is another child function of the function f2a, as an argument is executed.
In subroutine B, in step S60, since the variable flag is false, the process of step S61 is performed. In the process of step S61, since the search for the function f3b has not been performed so far, the array variable visited [f3b] is false. As a result, the process of step S62 is performed, the array variable validated [f3b] is set to true, and the array variable validated [f] is updated.

  Thereafter, the subroutine A with the function f3b as an argument is executed. In step S50, the function f3b is added to the end of the variable PATH, and the variable PATH = (main, f1a, f2a, f3b).

  Next, the same applies to the function f4b that is a child function fc of the function f3b, a function f5b that is a child function fc of the function f5b, and a function f6b that is a child function fc of the function f5b. Processing is performed.

  When the subroutine B is executed with the function f3b, which is the child function fc of the function f6b, as an argument, the array variable visited [f3b] is set to true. Therefore, the determination process of step S61 of the subroutine B causes the process of step S65 to Will be done.

  At the time of the process of step S65, the variable PATH is variable PATH = (main, f1a, f2a, f3b, f4b, f5b, f6b). In the division work table as shown in FIG. 24, the division names of the functions f4b, f5b, and f6b after the function f3b are the same division names r1, 1, and do not indicate the recursive unit 110. The process of step S66 is performed.

  In other words, the CPU 101 extracts the function f3b and subsequent functions of the variable PATH as the recursive unit 111. In step S67, the variable flag is set to true. After that, similarly to the detection process of the recursive unit 110 described above, after the process of setting the array variable visited [f] to false and the process of deleting the function at the end of the variable PATH are repeated, step S43 in FIG. 14 is performed. Returning to the process, the function group (functions f3b to f6b) and the variable flag = true that become the recursion unit 111 are output as the recursion detection result.

Thereafter, division processing as shown in FIG. 22 is performed again.
Although detailed description is omitted, the process of FIG. 22 is executed according to the recursive function list indicating the function group (functions f3b to f6b) of the recursive unit 111 detected as i = 2nd detected as described above. The

For each function of the second recursive unit 111, R2 is given as a division name by the process of step S72.
FIG. 26 is a diagram illustrating an example of the division work table output in the process of step S79.

  The division name R2 is given to the functions f3b to f6b included in the recursive unit 111. Of the descendant functions of the function f3b, the division name r2,1 is given to the function f5d not included in the recursive unit 111, and the division name r2,2 is given to the function f7b.

(Division information output processing)
In the process of step S34 shown in FIG. 12, for example, the CPU 101 generates and outputs division information based on the function size information shown in FIG. 11 and the division work table updated as shown in FIG. To do.

FIG. 27 is a diagram illustrating an example of division information.
The division information includes a list of functions of each division name, a total code size of the functions of each division name, a division plan to be described later, and an adoption division plan. In the initial value of the division information, the division plan and the adoption division plan are NULL.

Next, details of the division plan creation process of the recursive unit in step S22 of FIG. 8 will be described.
(Recursion part division plan creation process)
FIG. 28 is a flowchart illustrating an example of the division plan creation process of the recursive unit.

  For example, the CPU 101 inputs division information as shown in FIG. 27 (step S80). Then, the CPU 101 sets 1 as the initial value of the counter variable i with the number of the recursive part as the counter variable i (step S81). Further, the CPU 101 sets 1 as the initial value of the counter variable j with the number of the function to be divided in the recursive unit as the counter variable j (step S82). Further, the CPU 101 sets the value of the counter variable j as the initial value of the counter variable k (step S83).

  Next, the CPU 101 divides proposals (j, k) including the total code sizes σ and τ of each function group when divided before the function fj and before the function fk included in the recursive part of the division name Ri. (Σ, τ), division plan (k, j) = (τ, σ) is calculated (step S84).

  For example, in the recursive unit 110 shown in FIG. 18, to divide before the function f1a and before the function f2a means to divide the recursive unit 110 into a function f1a and two division units of function f2a to function f9a. It is.

  Here, in the recursive unit 110 shown in FIG. For example, when j = 1 and k = 2, division plans (1, 2) and (2, 1) are obtained when division is performed before the function f1 and before the function f2, and σ is a code of the function f1. The size τ is the total code size of the functions f2 to f9.

  The code sizes σ and τ are expressed by the following equations.

In equation (1), s (f _{i, t} ) indicates the code size of the t-th function f _{i, t} of the i-th recursive part. In the equation (2), s (f _{i, u} ) indicates the code size of the u th function f _{i, u} of the i th recursive part. n (i) indicates the number of functions included in the i-th recursive part.

Next, the CPU 101 determines whether or not the counter variable k is smaller than n (i) (step S85).
When the counter variable k is smaller than n (i), the CPU 101 increments the counter variable k (step S86) and repeats the processing from step S84. When the counter variable k reaches n (i), the CPU 101 determines whether or not the counter variable j is smaller than n (i) (step S87).

  If the counter variable j is smaller than n (i), the CPU 101 increments the counter variable j (step S88) and repeats the processing from step S83. When the counter variable j reaches n (i), the CPU 101 determines whether or not the counter variable i is smaller than N indicating the number of recursive parts (step S89).

  If the counter variable i is smaller than N, the CPU 101 increments the counter variable i (step S90) and repeats the processing from step S82. When the counter variable i has reached N, the CPU 101 outputs the division information including the above division plan and stores it in, for example, the RAM 102 (step S91).

FIG. 29 is a diagram illustrating an example of division information including a division plan.
In the division information shown in FIG. 29, a table tbl1 is added as a division plan of the recursive unit 110 with the division name R1. Further, a table tbl2 is added as a division plan of the recursion unit 111 of the division name R2.

FIG. 30 is a diagram illustrating an example of the table tbl1.
FIG. 30 shows the code size (σ and τ described above) of the function group corresponding to the division position in the functions f1a to f9a of the recursive unit 110. In FIG. 30, the code sizes of the functions f1a to f9a are each 1 KB.

  For example, when division is performed before the function f1a and before the function f2a (division plan (f1a, f2a)), σ is the code size of the function f1a, and τ is the total code size of the functions f2a to f9a, which is 8 KB. . Therefore, (1, 8) is obtained as shown in FIG. Note that the division proposals (f1a, f1a), (f2a, f2a), and the like indicate that they are not divided.

FIG. 31 is a diagram illustrating an example of the table tbl2.
FIG. 31 shows the code size (σ and τ described above) of the function group corresponding to the division position in the functions f3b to f6b of the recursive unit 111. In FIG. 31, the code size of the function f3a is 0.5 KB, the code size of the function f4b is 1.0 KB, the code size of the function f5b is 1.5 KB, and the code size of the function f6b is 2.0 KB. Yes.

  For example, when division is performed before the function f6b and before the function f3b (division plan (f6b, f3b)), τ is the code size of the function f6b and 2.0 KB, and σ is the total code size of the functions f3b to f5b. 0KB. Therefore, as shown in FIG. 31, (2.0, 3.0) is obtained.

The tables tbl1 and tbl2 as described above are used in the process of step S23 together with the division information d12 as the division plan d13 shown in FIG.
Next, details of the function assignment process in step S23 of FIG. 8 will be described.

(Function assignment processing)
FIG. 32 is a flowchart illustrating an example of a function assignment process.
For example, the CPU 101 inputs information such as the division information d12, the division plan d13, the memory bank configuration information d3, and the function size information d11 that are held in the RAM 102 (step S100).

Thereafter, the CPU 101 initializes various variables (step S101).
FIG. 33 is a diagram illustrating an example of the variable m_rest [M] after initialization.
A variable m_rest [M] indicates the remaining capacity of each memory bank. M indicates the number of the memory bank. The CPU 101 sets the capacity of each memory bank in the variable m_rest [M] based on the memory bank configuration information d3 as shown in FIG.

FIG. 34 is a diagram illustrating an example of the division information after initialization.
The CPU 101 adds information indicating whether or not the function of the division name has been assigned to the division information, and sets the information as “not yet” at the time of initialization.

Further, in the process of step S101, the following allocation information is generated.
FIG. 35 is a diagram illustrating an example of allocation information at the time of initialization.
The allocation information includes a partition name, a function indicated by the partition name, and a memory bank number to which the function of the partition name is allocated. At the time of initialization, since the assignment to the memory bank is not performed, the column of the memory bank number is blank.

  When the initialization is completed, the CPU 101 assigns the function whose division name is MAIN to the memory bank (step S102). For example, the function group of the division name MAIN including the function main is assigned to the memory bank in which the power control state is always the normal state. If a memory bank that is always in the normal state is a memory bank with M = 0, the memory bank number in the column of the division name of the allocation information shown in FIG. Further, the CPU 101 updates the information indicating whether or not the allocation is completed in the division information shown in FIG. 34 from “not yet” to “completed”. Further, the CPU 101 subtracts the total code size of the function whose division name is MAIN from the variable m_rest of the memory bank of M = 0 shown in FIG. If no other division name function is placed in the memory bank in which the power control state is always the normal state, the variable m_rest [0] of the memory bank with M = 0 may be set to 0.0 KB.

  Subsequently, the CPU 101 selects the memory bank M_Max having the largest remaining capacity and the dividing unit F_Max having the largest total code size (step S103). For M_Max, the memory bank with the largest variable m_rest [M] is selected. For F_Max, a function group having a division name having the maximum total code size is selected.

  Then, the CPU 101 determines whether or not the selected F_Max is a recursion unit (step S104). If F_Max is a recursive part, the process of step S105 is performed. If F_Max is not a recursive part, the process of step S109 is performed.

  For example, in the division information shown in FIG. 34, since the total code size of the function group with the division name R1 is the maximum and tbl1 is set as the division plan, it is determined as a recursive unit, and the process of step S105 is performed. Is called. When the division plan is NULL, it is determined that it is not a recursive part. Note that the CPU 101 may determine whether or not F_Max is a recursive part from the division name. For example, the split names R1 and R2 indicate the recursive part. Therefore, in the case of F_Max having such a split name, it may be determined that it is the recursive part.

  When F_Max is a recursive unit, the CPU 101 refers to the division information as illustrated in FIG. 34 and determines whether or not the division plan to be adopted has been set (step S105). If it has not been set, the process of step S106 is performed, and if it has been set, the process of step S108 is performed.

For example, in the division information, when the adopted division plan remains NULL as shown in FIG. 34, the process of step S106 is performed.
If the division plan to be adopted has not been set, the CPU 101 selects the adoption division plan and sets the function group F to be assigned to M_Max (step S106).

  In the process of step S106, the CPU 101 refers to the tables tbl1 and tbl2 indicating the division plan as shown in FIGS. For example, the table tbl1 is set as the division plan in the division unit of the division name R1 selected as F_Max. The CPU 101 selects the division plan that maximizes the second element in a range not exceeding the variable m_rest among the code sizes of the two function groups when the division is performed.

  When the maximum m_rest [M] is 8 KB, for example, (f1a, f2a) = (1, 8) obtained by dividing before each of the functions f1a and f2a is selected from the division plans shown in FIG. Is done. A function group (f2a to f9a) having the code size (8 KB) of the second element of the division plan is set as the function group F.

  Thereafter, the CPU 101 sets the adoption division plan as division information (step S107). In the case of the above example, the CPU 101 changes the adoption division proposal part of the division unit of the division name R1 from NULL to (f1a, f2a). Thereafter, the process of step S110 is performed.

  If it is determined in step S105 that the adoption division plan has been set, the CPU 101 sets the unassigned side of the two elements of the adoption division plan as the function group F (step S108). For example, when the division plan (f1a, f2a) is adopted and the function group (f2a to f9a) has been assigned to the memory bank, the remaining function f1a is set as the function group F. . Thereafter, the process of step S110 is performed.

On the other hand, if it is determined in step S104 that F_Max is not a recursive part, F_Max is set as the function group F.
Next, the CPU 101 determines whether or not the code size s (F) of the function group F is equal to or less than the remaining capacity (m_rest [M_Max]) of M_Max (step S110). Since assignment is possible if s (F) is equal to or less than m_rest [M_Max], the CPU 101 assigns the function group F to M_Max (step S111). In addition, the CPU 101 subtracts s (F) from m_rest [M_Max].

For example, when the functions f2a to f9a are allocated to the memory bank with M = 1 among the division units of the division name R1, the allocation information is as follows.
FIG. 36 is a diagram illustrating an example of updating allocation information.

  Since the division part (recursion part) of the division name R1 is further divided into two, as shown in FIG. 36, one division name is R1_1 and the other is R1_2. In the example of the present embodiment, among these, the one with the larger code size is first assigned to the memory bank. In the example of FIG. 36, the functions f2a to f9a of the division name R1_1 are assigned to the memory bank with the memory bank number 1, and the remaining functions f1a of the division name R1_2 are in an unassigned state.

FIG. 37 is a diagram illustrating an example of updating the division information.
For the division part of the division name R1, (f1a, f2a) is set as the adoption division plan. Whether the function group with the division name R1_1 of the allocation information has been assigned to the memory bank, but if the function group with the division name R1_2 has not been assigned yet, is the allocation managed by the division information completed? The information indicating whether or not remains “not yet”.

After assigning the function group F to M_Max, the CPU 101 determines whether the function groups of all the division names included in the assignment information have been assigned (step S112).
If all assignments have been made, the CPU 101 outputs the updated assignment information (step S113) and stores it in the RAM 102, for example, and the function assignment process ends. If there is something that has not been assigned, the processing from step S103 is repeated.

  For example, when the division name R1 is assigned to the memory bank and the function group of the division name R1_2 has not been assigned, whether or not the division part of the division name R1 managed by the division information has already been assigned. As shown in FIG. 37, the information indicating “No” remains “not yet”. Therefore, in the process of step S103, the division part with the division name R1 is selected again as F_Max.

  Thereafter, the process proceeds from the determination process of step S105 to the process of step S108, where a function group with an unassigned division name R1_2 is set as a function group F and is assigned to M_Max in step S111.

  On the other hand, if s (F) exceeds m_rest [M_Max] in the process of step S110, the function group F is not assigned to any memory bank, and an error is output (step S114). For example, the CPU 101 controls the graphic processing device 104 to display an error on the screen of the monitor 104a, and ends the function assignment processing.

FIG. 38 is a diagram illustrating an example of allocation information to be output.
In the example of FIG. 38, the function of each division name is assigned to the memory banks with memory bank numbers 0 to 4.

When the function assignment process as described above is completed, the address calculation in step S24 in FIG. 8 is performed using the assignment information as shown in FIG.
Details of the address calculation process will be described below.

(Address calculation processing)
FIG. 39 is a flowchart illustrating an example of the address calculation process.
For example, the CPU 101 inputs information such as allocation information d14, memory bank configuration information d3, and function size information d11 held in the RAM 102 (step S120).

  Thereafter, the CPU 101 initializes variables (step S121). Here, the CPU 101 sets the variable start_addr [M] indicating the start address of the function as the start address of the memory bank whose memory bank number is M, based on the memory bank configuration information d3.

  Subsequently, the CPU 101 extracts a function group having the same division name from the allocation information d14 (step S122). For example, from the allocation information as shown in FIG. 38, first, the functions main, f1b, f2b, and f2c of the division name MAIN allocated to the memory bank with the memory bank number 0 are extracted.

  Then, the CPU 101 sets 1 to the counter variable i (step S123), and assigns the variable start_addr [M] as the start address of the i-th function fi in the extracted function group (step S124).

  Thereafter, the CPU 101 updates the variable start_addr [M] based on the code size of the assigned function fi (step S125), and then determines whether or not the counter variable i is smaller than the number n of the extracted functions. (Step S126). If i <n, the CPU 101 increments the counter variable i (step S127) and repeats the processing from step S124. When the counter variable i has reached n, the CPU 101 determines whether the assignment has been completed for all the division name function groups in the assignment information d14 (step S128).

  When all the assignments are completed, the CPU 101 outputs a memory map (step S128), stores it in the RAM 102, for example, and finishes the address calculation process. If all assignments have not been completed, the CPU 101 repeats the processing from step S122.

FIG. 40 is a diagram showing an example of an output memory map.
In the memory map, the start address of each function assigned to each memory bank is set.

  When the address calculation process as described above is completed and a memory map is created, the power control code insertion process in step S12 is performed as shown in FIG. Details of the power control code insertion process will be described below.

(Power control code insertion process)
FIG. 41 is a flowchart illustrating an example of the power control code insertion process.
For example, the CPU 101 inputs information such as a program (assembly) d2 and a memory map d4 held in the RAM 102 (step S130). Next, the CPU 101 extracts an instruction from the head of the program d2 (step S131), and determines whether or not the instruction is a function call instruction (step S132).

If the instruction is a function call instruction, the process of step S133 is performed. If the instruction is not a function call instruction, the process of step S135 is performed.
If the instruction is a function call instruction, the CPU 101 refers to the memory map d4 to determine whether the memory bank of the caller function and the callee function are the same (step S133).

If the memory banks of the caller function and the callee function are not the same, the process of step S134 is performed, and if they are the same, the process of step S135 is performed.
When the memory banks of the caller function and the callee function are not the same, the CPU 101 generates a power control code and inserts it immediately before and after the function call instruction (step S134).

  The power control code inserted immediately before the function call instruction sets the power control state of the memory bank in which the caller function is placed to the power saving state, and normally sets the power control state of the memory bank in which the callee function is placed. It is a state.

  In addition, the power control code inserted immediately after the function call instruction includes the power control state of the memory bank other than the memory bank in which the caller function is disposed and the memory bank in which the function main is disposed. To do.

  Thereafter, the CPU 101 determines whether or not the fetched instruction is at the end of the function (step S135). If the instruction fetched by the CPU 101 is the end of the function, the process of step S136 is performed. If the instruction is not the end of the function, the process of step S138 is performed.

When the fetched instruction is the end of the function, the CPU 101 determines whether or not the memory bank of the function and all the caller functions of the function are the same (step S136).
If the memory bank of the function and all the caller functions of the function are not the same, the process of step S137 is performed. If the memory bank is the same, the process of step S138 is performed.

When the memory bank of the function and all the caller functions of the function are not the same, the CPU 101 inserts a power control code at the end of the function (step S137).
This power control code sets the power control state of the memory bank in which all the functions calling the function are arranged to the normal state.

  Subsequently, the CPU 101 detects the end of the entire program (step S138). When the end of the entire program is detected, the CPU 101 outputs the program (assembly) d5 containing the power supply control code (step S139), stores it in the RAM 102, for example, and finishes the power control code insertion process.

On the other hand, if the end of the entire program is not detected in the process of step S138, the process from step S131 is repeated.
The program (assembly) d5 containing the power control code generated as described above becomes a program (object) d6 containing the power control code by assembling as shown in FIG. Further, the linker is linked with another library such as the memory map d4 to generate a power control code-containing program (binary) d7 (step S14), and the program generation process ends.

  When the power control code-containing program d7 generated as described above is input to the electronic device 50 as shown in FIG. 2, for example, the processor 20 converts the function into an instruction code based on the memory map d4. Are allocated to memory banks 11-0 to 11-3.

  Even when the processor 20 executes the program d7 including the power control code in the memory banks 11-0 to 11-3. The power consumption of the memory unit 10 can be reduced. As a result, the low power consumption electronic device 50 is obtained.

Hereinafter, an example of power consumption reduction will be described.
For example, the instruction code memory 12 of the electronic device 50 subject to power control has four memory banks 11-0 to 11-3, and the power consumption in the normal state of the memory banks 11-0 and 11-1 is 2 mW. The power consumption in the power saving state is 0.5 mW. The power consumption in the normal state of the memory banks 11-2 and 11-3 is 4 mW, and the power consumption in the power saving state is 1.0 mW.

  It is assumed that the program has a recursive part with functions f1, f2, and f3 and a function main. Further, the function main is arranged in the memory bank 11-0, the function f1 is arranged in the memory bank 11-1, the function f2 is arranged in the memory bank 11-2, and the function f3 is arranged in the memory bank 11-3.

For example, assume that a program is executed as follows for a certain input.
After the function main is executed for 15 msec, the function f1 is called, after 380 msec is executed, the function f2 is called, after 3 msec is executed, the function f3 is called, and after 10 msec is executed, the function f2 is restored. . Then, after the function f2 is executed for 7 msec, the function f1 is returned to. After the function f1 is executed for 580 msec, the function main is returned to and the function main is executed for 5 msec.

  When the program operation as described above is performed, according to the power control method of the present embodiment, the total energy consumption of the memory banks 11-0 to 11-3 is 6 mJ. On the other hand, when processing the recursive unit, the total energy consumption when the memory banks 11-1 to 11-3 in which the functions f1 to f3 included in the recursive unit are arranged is always in the normal state is 11.85 mJ. A significant power reduction is possible.

  In the above description, for example, the computer 100 as shown in FIG. 6 generates the program, but the present invention is not limited to this. For example, the processor 20 itself of the electronic device 50 shown in FIG. 2 may read a program stored in the memory unit 10 and generate a program including the power control code as described above.

(Third embodiment)
In the second embodiment, in the function assignment process as shown in FIG. 32, the recursive part larger than the capacity of the memory bank is divided, one function group is assigned to the memory bank, and the other function group is assigned. Are assigned to other memory banks prior to the other division units.

However, the function can be efficiently and quickly assigned to a small number of memory banks as follows.
FIG. 42 is a flowchart illustrating an example of a function assignment process according to the third embodiment.

  Similarly to the example shown in FIG. 32, the CPU 101 inputs various information (step S140) and initializes various variables (step S141), but adds the following items to the division information.

FIG. 43 is a diagram illustrating an example of the division information after initialization.
In the division information shown in FIG. 43, instead of information indicating whether or not the function of the division name has been assigned as shown in FIG. The item “Size” has been added. The remaining code size indicates the total code size of the functions included in the division unit indicated by the division name but not assigned to the memory bank.

  When the initialization is completed, the CPU 101 assigns the function whose division name is MAIN to the memory bank in the same manner as the processing in step S102 of FIG. 32 described above (step S142).

  Subsequently, the CPU 101 selects the memory bank M_Max having the largest remaining capacity and the division unit F_Max having the largest remaining code size (step S143). For M_Max, the memory bank with the largest variable m_rest [M] is selected. For F_Max, a function group having a division name with the largest remaining code size is selected.

  Hereinafter, steps S144 to S154 are substantially the same as the processing of steps S104 to S114 of FIG. 32 described above. However, in the process of step S151, after assigning the function group F to M_Max, the CPU 101 subtracts the code size of the function group F from the remaining code size of the division unit including the assigned function group F in the division information.

FIG. 44 is a diagram illustrating an example of updating the division information.
FIG. 44 shows an example of updating the division information after the functions f2a to f9a are allocated to the memory banks in the division unit of the division name R1.

  In the above example, the code size of each function f2a to f9a is 1.0 KB, so the total code size is 8.0 KB. The CPU 101 subtracts this from the total code size of the division part of the division name R1, and sets the remaining code size to 1.0 KB.

  Thereby, when returning to the process of step S143, the functions f3b to f6b of the division unit having the largest remaining code size R2 are selected as the function group F from the division units managed by the division information, and the memory Assignment to the bank is performed.

FIG. 45 is a diagram illustrating an example of updating allocation information.
After the function group with the division name R1_1 is assigned to the memory bank with the memory bank number 1, the function group with the division name R2 is assigned to the memory bank (memory bank number = 2) before the function group with the division name R1_2. The state assigned to is shown.

If a code having a small code size is assigned to a memory bank first, the remaining capacity of the memory bank is insufficient, and a large function group cannot be arranged, resulting in an error.
However, according to the function allocation process as described above, since the division unit having a large remaining code size is allocated to the memory bank, the function can be allocated efficiently and quickly to a small memory bank. .

(Fourth embodiment)
In the following, a function assignment process that can assign functions to memory banks more quickly will be described.

FIG. 46 is a flowchart illustrating an example of a function assignment process according to the fourth embodiment.
Similar to the third embodiment, the CPU 101 inputs various information (step S160) and initializes various variables (step S161).

Thereafter, the CPU 101 creates a quick reference table as shown below (step S162).
FIG. 47 is a diagram showing an example of a quick reference table.
The quick reference table summarizes the code size of each division plan. The code size of each division plan is the value of the second element of the division plan. For example, in the table tbl1 as shown in FIG. 30, since the code size of each function group when it is divided by the division plan (f1a, f2a) is (1, 8), the value of the second element is 8 (KB) is the code size in the quick reference table.

For a division unit that is not a recursive part, such as division names r1, r2, and MAIN, the division plan is NULL, and the code size of the division unit is indicated.
When the creation of the quick reference table as described above is completed, the CPU 101 assigns the function whose division name is MAIN to the memory bank in the same manner as the processing in step S102 of FIG. 32 described above (step S163).

  Subsequently, the CPU 101 refers to the memory bank M_Max with the largest remaining capacity and the quick reference table, and selects the division unit F_Max with the largest code size (step S164). When the maximum remaining capacity is 8 KB in a plurality of memory banks, in the example of the quick reference table in FIG. 47, the code size of the division plan (f1a, f2a) is the maximum within the range of 8 KB. The division part having the division name R1 is selected as the division part F_Max.

  Steps S165 to S172 are substantially the same as the processing of steps S144 to S151 shown in FIG. 42, but in the processing of step S167, the above-mentioned division plan of the maximum code size in the quick reference table is selected, and A function group of the second element is set as a function group F.

For example, the aforementioned division plan (f1a, f2a) is set, and the function group (functions f2a to f9a) of the second element is set as the function group F.
After assigning the function group F to M_Max, the CPU 101 updates the quick reference table (step S173). For example, after assigning the function group (functions f2a to f9a) of the second element of the division plan (f1a, f2a) to the memory bank, the quick reference table is updated as follows.

FIG. 48 is a diagram illustrating an example of updating the quick reference table.
As shown in FIG. 48, the division name MAIN assigned to the memory bank and the data of the division name R1 (hereinafter referred to as an entry) are deleted. However, since the function f1a which is the first element of the division plan (f1a, f2a) among the division units of the division name R1 is not assigned, the entry of the division name R1_2 described by the assignment information shown in FIG. Is newly added to the chart.

The entry of the division name R1_2 has a code size of 1.0 KB because it is the code size of the function f1a, and the division plan is NULL.
The processing in steps S174 to S176 in FIG. 46 is the same as the processing in steps S152 to S154 in FIG. Allocation of the function group F to M_Max and updating of the quick reference table are repeated, and finally allocation information is output.

FIG. 49 is a flowchart illustrating an example of a quick reference table creation process.
For example, the CPU 101 inputs division information as shown in FIG. 43 (step S180), and acquires one entry (data in one row of a table as shown in FIG. 43) from the division information (step S181).

  Then, the CPU 101 determines whether or not the acquired entry is a recursive part (step S182). Whether or not it is a recursive part can be determined by, for example, the division name of the division information. In the example of the division information shown in FIG. 43, when the division name is R1 or R2, it is determined as a recursion unit, and the process of step S184 is performed. When the division name is other than that (for example, MAIN, r1, 2, etc.), it is determined not to be a recursive part, and the process of step S188 is performed.

  When the CPU 101 determines that the entry is a recursive part, the CPU 101 obtains one entry of a division plan for the recursive part (step S184). For example, the division plan of the division unit (recursion unit) of the division name R1 has combinations such as the table tbl1 shown in FIG. Obtained as one entry.

  Then, the CPU 101 determines whether or not an entry with the same division name and the same code size has been registered in the quick reference table (step S185). If not, the entry is registered in the quick reference table (step S186). .

  After registration in the chart, or when an entry with the same division name and code size as the acquired entry has already been registered, the CPU 101 determines whether or not the processing of steps S184 to S186 has been completed for all entries of the division plan Is determined (step S187). When the processes of steps S184 to S186 for all the entries of the division plan are completed, the process of step S189 is performed. When there are uncompleted entries, the process from step S184 is performed for the entry. Is repeated.

  On the other hand, if the CPU 101 determines in step S182 that the entry of the division information is not a recursive part, the CPU 101 registers the entry in the quick reference table and proceeds to the process of step S189.

  When the processing of steps S184 to S186 for all entries of the division plan is completed, or after the processing of step S188, the CPU 101 determines whether or not the processing of steps S181 to S188 has been completed for all entries of the division information. Determination is made (step S189).

  When the processing of steps S181 to S188 is completed for all entries of the division information, the CPU 101 outputs a quick reference table (step S190), stores it in the RAM 102, for example, and ends the quick reference table creation processing. If the processing of steps S181 to S188 has not been completed for all entries of the division information, the processing from step S181 is repeated.

Through the processing as described above, a quick reference table as shown in FIG. 47 is created.
FIG. 50 is a flowchart illustrating an example of a quick reference table update process.
The CPU 101 inputs the quick reference table and the division information (step S200), and determines whether or not the entry to be updated is a recursive unit for which the division plan has not been determined (step S201). If the entry to be updated is a recursive part for which the division plan has not been determined, the process of step S202 is performed. If the entry to be updated is not a recursive part for which the division plan has not been determined, the process of step S204 is performed. .

  For example, in the quick reference table as shown in FIG. 47, when updating the entry having the code size of 8.0 KB, the division name R1, and the division plan (f1a, f2a), the division information shown in FIG. The division plan for R1 is NULL. Therefore, it is determined that the recursion unit has not yet been determined, and the CPU 101 deletes the entry having the same division name as the update target entry from the quick reference table (step S202).

  Thereafter, the CPU 101 registers the entry after the division plan decision in the quick reference table (step S203). As a result, for example, as shown in FIG. 48, an entry for the division name R1 is deleted, and a quick reference table to which an entry for the division name R1_2 is added is obtained.

On the other hand, if the entry to be updated is not a recursive part for which the division plan has not been determined, the CPU 101 deletes the entry from the quick reference table (step S204).
After the processing of step S203 or S204, the CPU 101 outputs the quick reference table (step S205), stores it in the RAM 102, for example, and ends the quick reference table update processing.

As described above, by assigning a function to a memory bank using a quick reference table, it becomes possible to assign a function to a memory bank more quickly.
Note that the above-described power control method and generation processing of a program including a power control code can be realized by, for example, a computer having a hardware configuration as shown in FIG. In that case, a program describing the processing contents of the functions that the electronic devices 1 and 50 and the computer 100 should have is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic storage device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Magnetic storage devices include HDDs, flexible disks (FD), and magnetic tapes. Optical discs include DVD, DVD-RAM, CD-ROM / RW, and the like. Magneto-optical recording media include MO (Magneto-Optical disk).

  When distributing the program, for example, portable recording media such as a DVD and a CD-ROM in which the program is recorded are sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time a program is transferred from a server computer connected via a network, the computer can sequentially execute processing according to the received program.

  In addition, at least a part of the above processing functions can be realized by an electronic circuit such as a DSP, an ASIC (Application Specific Integrated Circuit), or a PLD (Programmable Logic Device).

  As described above, one aspect of the power control method, the electronic device, the program, and the program generation method of the present invention has been described based on the embodiments. However, these are merely examples, and are not limited to the above description. .

DESCRIPTION OF SYMBOLS 1,50 Electronic device 2,20 Processor 3a, 3b Memory area 10 Memory unit 11-0 to 11-n Memory bank 12 Memory for instruction code 13 Memory for data 21 Processor core 22 Memory controller 30 Control register unit 40 Power control unit 40 −0 to 40−n Power control circuit 41 Bus 42 Power supply line

Claims (11)

A function in a program executed by the processor is assigned, and when executing a first function arranged in the first memory area among a plurality of memory areas having a power control state of a normal state and a power saving state, Just before the second function arranged in the second memory area is called, the first memory area is set to the power saving state, and the second memory area is set to the normal state.
The power control method, wherein the processor controls a power control state of the plurality of memory areas. Immediately before returning from the second function to the first function, the first memory area is set to the normal state.
Immediately after returning from the second function to the first function, the second memory area is set to the power saving state.
The power control method according to claim 1, wherein the processor controls a power control state of the plurality of memory areas. When there are a plurality of the first function and the first memory area,
Immediately before returning from the second function to the first function, all the first memory areas are set to the normal state,
Immediately after returning from the second function to the first function, the second memory area other than the memory area that is the return destination among the plurality of first memory areas and the second memory area are set in the power saving state. In addition,
The power control method according to claim 1, wherein the processor controls a power control state of the plurality of memory areas.   In the first function, an instruction for setting the first memory area to the power saving state and the second memory area to the normal state is described immediately before the instruction to call the second function. The power control method according to any one of claims 1 to 3.   5. The instruction according to claim 1, wherein an instruction for setting the second memory area in the power saving state is described immediately after the instruction for calling the second function in the first function. The power control method according to claim 1. A processor;
A function in a program executed by the processor is assigned, and has a plurality of memory areas having a power control state of a normal state and a power saving state;
The processor, when executing the first function arranged in the first memory area among the plurality of memory areas, immediately before calling the second function arranged in the second memory area. An electronic apparatus characterized in that one memory area is placed in the power saving state. A function in a program executed by the processor is assigned, and when executing a first function arranged in the first memory area among a plurality of memory areas having a power control state of a normal state and a power saving state, Immediately before the second function arranged in the second memory area is called, the first memory area is set to the power saving state, and the second memory area is set to the normal state.
A program that causes a computer to execute processing. In a method for generating a program for controlling the power control state of a plurality of memory areas having a power control state of a normal state and a power saving state,
Computer
Determining allocation of functions in the program to the plurality of memory areas;
Among the plurality of memory areas, in the first function arranged in the first memory area, the first memory area is set immediately before the call instruction of the second function arranged in the second memory area. Inserting an instruction to set the power saving state and the second memory area to the normal state;
A program generation method characterized by the above. Dividing the program into a plurality of division units including one or more functions;
Among the plurality of division units, create a plurality of division plans that further divide the function group to be a recursion unit,
From the plurality of division plans, select a division plan to be adopted according to the remaining capacity of the plurality of memory areas,
9. The program according to claim 8, wherein a memory map for designating a memory area in which the recursive unit divided based on the selected division plan and a divided unit other than the recursive unit are arranged is created. Generation method.   The program generation method according to claim 9, wherein the allocation is determined from a division unit having a large code size that is not allocated to the memory area among the plurality of division units. Create a table including the code size of each function group obtained when dividing the recursive unit according to each of the plurality of division plans,
11. The division plan to be adopted is selected from the plurality of division plans according to the remaining capacity of each of the plurality of memory areas and the code size with reference to the table. A method for generating the program described in 1.

Images