KR101863590B1 - Cache memory apparatus and method having function of saving energy for refresh - Google Patents

Abstract

The present invention relates to a cache memory device and a method thereof. The cache memory device has a cache memory which is configured to compress cache data line by line and store the cache data compressed in each line in different storage areas in a divided manner, execute a refresh process only in the storage areas storing the compressed cache line data, and minimize the execution of the refresh process, thereby reducing the power consumption. According to the present invention, the cache memory device with a refresh power consumption reduction function includes: the cache memory which stores the cache data in the unit of cache lines, is configured to include multiple sub-arrays in a predetermined size while storing the data in the unit of cache lines, and stores the cache line data in different sub-arrays in a divided manner; and a cache management module which compresses the cache data in the unit of cache lines, divides the cache data in a preset size unit, stores the divided cache data to different and individual sub-arrays in the memory array in a divided manner, calls compressed in the cache line data are divided and stored in the sub-arrays in the memory array when accessing the cache data, executes a compression restoration process for the accessed cache data, and executes a refresh process only in the sub-arrays in the corresponding memory array storing the cache line data used as a refresh target when executing the refresh operation.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a cache memory apparatus having a refresh power-

The present invention relates to a cache memory device, in which a cache memory is configured to compress cache data in units of lines and to divide and store the cache data in different storage areas, and to perform refresh processing only on storage areas in which compressed cache line data are stored, And more particularly, to a cache memory device and a method thereof that can minimize power consumption and thereby reduce power consumption.

A cache memory is a buffer-type high-speed storage device filled with commands or programs read from main memory, and is an area in which frequently accessed data or program commands are stored for immediate use without repeatedly searching.

As the performance of recent processors has improved, the importance of cache memory to reduce bottlenecks between processor cores and main memory has been increasing.

In addition, as the utilization of the cache memory becomes higher and the capacity of the cache becomes larger and more complicated, the influence of the cache on the power consumption of the entire chip is also increasing.

Particularly, eDRAM (Embedded DRAM) -based cache memory, which is a capacitor type DRAM built in a die or a package of a processor or an ASIC, is recently applied.

Since the eDRAM-based cache memory has a higher density than the SRAM and has a larger capacity than the SRAM, more memory can be used, but a refresh operation must be periodically performed to maintain data.

The refresh operation in the dynamic memory device increases the power consumption, and the more the refresh operation, the more the latency and the consumed power increase, which causes a problem of lowering the data input / output speed and energy efficiency.

1. Korean Patent Publication No. 10-2016-0111643 (titled Dynamic memory device using page residence information of conversion index buffer and its selective refresh method) 2. Korean Registered Patent No. 10-1436442 (name: dynamic memory device with optional selective refresh function for read and write access and its selective refresh method)

Accordingly, the present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method and apparatus for compressing cache data in units of lines and dividing them into different storage areas, The present invention provides a cache memory device and a method thereof that can reduce power consumption according to refreshing through a refresh operation of a cache memory.

According to an aspect of the present invention, a memory array for storing cache data in units of cache lines and storing data in units of cache lines includes a plurality of subarrays having a predetermined size, A cache memory configured to divide and store cache data in units of cache lines and to divide the cache data in units of predetermined sizes and to divide the cache data into different subarrays in a memory array, When accessing the memory array, the compressed cache line data divided and stored in the subarray of the memory array is called to perform decompression processing on the compressed cache line data. In the refresh execution, only the subarrays of the memory array in which the refresh target cache line data is stored are refreshed Configure to perform Is a cache memory device having a refresh power savings features, characterized in that comprising: a cache management module is provided.

A cache memory device having a refresh power saving function is provided, wherein a plurality of subarrays constituting the one memory array are configured to be accessible simultaneously.

Also, the cache memory is configured by eDRAM (Embedded Dynamic Random Access Memory), and a cache memory device having a refresh power saving function is provided.

In addition, a multiplexer is coupled so as to correspond one-to-one with respect to each of the sub-arrays. In performing the refresh, the cache management module simultaneously provides a refresh signal to the multiplexers of all sub-arrays constituting the memory array, The number of subarrays corresponding to the compressed cache line data size is checked and the refresh selection signal is provided only to the multiplexer associated with the subarray storing the compressed cache line data so that the refresh signal and the refresh selection signal are both input to the multiplexer Wherein the cache memory device is configured to perform a refresh operation only in a sub-array having a refresh power consumption.

In addition, the memory array is configured to have a storage area equal in size to the size of the cache line data, and the N subarrays constituting the memory array are configured to have a storage area in which the memory array storage area is divided into N areas, And the cache management module divides the compressed cache line data into sub-array storage area units and sequentially stores the compressed cache line data in a sub-array in a predetermined storage order. do.

In addition, the carry management module includes a cache table in which sub-array usage information corresponding to the compressed data size for each cache line is stored. After the cache line data compression process, the carry management module includes a storage area Arrays corresponding to the calculated number of subarrays, and stores the generated subarray usage information in the cache table. The cache memory device has a function of saving the refresh power consumption.

In the cache table, the sub-array usage information is composed of bit data capable of representing N sub-arrays in different forms, wherein the number of sub-arrays in which the compressed cache line data is stored, A cache memory device having a function is provided.

According to an aspect of the present invention, there is provided a cache management module coupled between a cache memory and a processor for storing and retrieving cache data in a cache memory in response to a request from a processor, The cache management module compresses cache data on a cache line by cache line basis in response to a cache data storage request from a processor and stores the compressed cache line data in a cache memory The compressed cache line data is divided into storage area size units of the sub-array in which the corresponding memory array storage area is divided into N sub-arrays, and the N sub-arrays serving as the memory array Sequentially store the array in a predetermined order Storing cache data stored in a subarray of the memory array in response to a cache data access request from a processor in a cache management module, performing decompression processing on the compressed cache line data, and providing cache data And a refresh step of performing refresh processing only on a sub-array of the memory array in which the refresh target cache line data is stored in accordance with the refresh request from the processor in the cache management module. A refresh power saving method is provided.

In addition, the cache management module may calculate the number of subarrays corresponding to the compressed cache line data size, generate subarray usage information corresponding to the calculated number of subarrays, And a cache table is generated and managed in the cache memory device.

The sub-array usage information in the cache table may include the number of sub-arrays in which compressed cache line data is stored, and bit data that can represent N sub-arrays in different forms. There is provided a method for reducing refresh power consumption.

The cache data accessing step may include a step of checking the number of sub-arrays for the cache line through the cache table in the cache management module, a step of accessing the sub-arrays corresponding to the number of sub-arrays, Generating one compressed cache line data by calling and combining the cache line data; and compressing and decompressing the compressed cache line data to reduce the refresh power consumption in the cache memory device. Method is provided.

The refresh step may further include the steps of providing a refresh signal to all sub-arrays of the memory array in which the refresh target cache line data is stored for the refresh request from the processor in the cache management module, The method comprising the steps of: determining a number of subarrays for the cache line; providing a refresh selection signal only to the subarrays corresponding to the number of subarrays; performing a refresh operation only on the subarrays to which both the refresh signal and the refresh selection signal are input The method of reducing power consumption of a refreshing power supply is provided.

According to the present invention, cache data on a line-by-line basis is compressed, divided and stored in different storage areas, and then only the area where the compressed cache data is stored is subjected to refresh processing, Power consumption can be reduced.

Accordingly, the efficiency of use data input / output speed and power consumption of the processor configured by employing the cache memory device according to the present invention can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining a configuration of a cache memory device having a refresh power-saving function according to an embodiment of the present invention; FIG.
2 and 3 are diagrams for explaining the structure of the cache memory 20 shown in FIG.
FIG. 4 is a block diagram showing the internal structure of the cache management module 30 shown in FIG. 1 functionally separated. FIG.
5 to 7 are flowcharts for explaining cache data storage, cache data access, and refresh operation of the cache memory device having the refresh power-saving function shown in FIG.

The description of the present invention is merely an example for structural or functional explanation, and the scope of the present invention should not be construed as being limited by the embodiments described in the text. That is, the embodiments are to be construed as being variously embodied and having various forms, so that the scope of the present invention should be understood to include equivalents capable of realizing technical ideas. Also, the purpose or effect of the present invention should not be construed as limiting the scope of the present invention, since it does not mean that a specific embodiment should include all or only such effect.

Meanwhile, the meaning of the terms described in the present invention should be understood as follows.

The terms "first "," second ", and the like are intended to distinguish one element from another, and the scope of the right should not be limited by these terms. For example, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" to another element, it may be directly connected to the other element, but there may be other elements in between. On the other hand, when an element is referred to as being "directly connected" to another element, it should be understood that there are no other elements in between. On the other hand, other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

It should be understood that the singular " include "or" have "are to be construed as including a stated feature, number, step, operation, component, It is to be understood that the combination is intended to specify that it does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In each step, the identification code (e.g., a, b, c, etc.) is used for convenience of explanation, the identification code does not describe the order of each step, Unless otherwise stated, it may occur differently from the stated order. That is, each step may occur in the same order as described, may be performed substantially concurrently, or may be performed in reverse order.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Commonly used predefined terms should be interpreted to be consistent with the meanings in the context of the related art and can not be interpreted as having ideal or overly formal meaning unless explicitly defined in the present invention.

1 is a diagram for explaining a configuration of a cache memory device having a refresh power consumption reduction function according to an embodiment of the present invention.

As shown in FIG. 1, a cache memory device having a refresh power saving function according to the present invention includes a cache management module 30 between a processor 10 and a cache memory 20. At this time, the processor 10 may be a processor included in various devices using a cache memory such as a general desktop, a laptop, and a mobile computing system. The cache management module 30 and the cache memory 20 are one cache memory device and may be configured independently of the processor 10 or may be integrated in the processor 10.

The cache memory 20 is for storing cache data and is composed of eDRAM (Embedded Dynamic Random Access Memory). The cache memory 20 stores cache data on a line-by-line basis. At this time, the cache data (hereinafter referred to as "cache line data") on a line-by-line basis is divided into a plurality of different storage areas (hereinafter, sub-arrays shown in FIG. Further, the cache line data includes a tag area and a data area having a predetermined address space.

The cache management module 30 compresses cache line data for each line in response to a cache data storage request from the processor 10, divides the cache line data in units of a predetermined size, and stores the data in the cache memory 20.

The cache management module 30 checks whether there is a cache line whose tag matches the address received from the processor 10 in response to a cache data call request from the processor 10, It calls and decompresses the corresponding cache line data stored in the cache memory 20, and provides the decompressed cache line data to the processor 10.

The cache management module 30 may be configured to cache cache line data that are stored in the cache memory 20 for the refresh target cache line whose tag matches the address received from the processor 10 for a refresh request from the processor 10 Is configured to perform the refresh operation only for the storage area where the storage area is stored.

2 is a view for explaining the structure of the cache memory 20 shown in FIG.

As shown in FIG. 2, the cache memory 20 is composed of a plurality of memory banks (MB), and is configured to access only one memory bank (MB) for one cache request. Here, each memory bank (MB) may be simultaneously accessed in parallel.

Also, the memory banks (MB) are divided into a plurality of memory subbanks (SB), and the memory subbanks (SB) are configured so that only one memory subb bank (SB) is accessed at a time of one access.

In addition, the memory sub-bank SB is composed of a plurality of memory arrays MA having a storage area of a cache line data size, which is also configured so that only one memory array MA is accessed at a time of access.

The memory array MA is composed of N sub-arrays SA having a storage area of a predetermined size (hereinafter, N is a natural number), and the sub-array SA is a storage area of the memory array MA The storage area is set to the size of N divided. The number of subarrays SA can be varied and set in conjunction with the number of divisions of cache line data. For example, the total number of subarrays SA constituting one memory array MA can be set to a multiple of four. In FIG. 2, the memory array MA is composed of four first to fourth subarrays SA1, SA2, SA3, and SA4.

And, for one memory array (MA) access, all subarrays (SA) constituting the memory array (MA) are configured to be accessed simultaneously.

In addition, the subarrays SA are configured to have a constant data storage order. For example, when the compressed cache line data is divided into three subarrays, the first compressed data corresponding to the first portion of the compressed cache line data is stored in the first subarray SA1, The second compressed data is stored in the second sub-array SA2, and the third compressed data corresponding to the last portion is sequentially stored in the third sub-array SA3.

As shown in FIG. 3, the first through fourth multiplexers MUX1, MUX2, MUX3, and MUX4 correspond to each other in a one-to-one correspondence. At this time, the first to fourth multiplexers MUX1, MUX2, MUX3, and MUX4 are turned on only when a refresh signal (refresh) and a refresh selection signal (select) applied from the cache management module 30 are input, Set it as a refresh target.

FIG. 4 is a functional block diagram of the internal structure of the cache management module 30 shown in FIG.

As shown in FIG. 4, the cache management module 30 includes a compression processing unit 31, a decompression unit 32, a cache table storage unit 33, and a control unit 34.

The compression processing unit 31 performs a series of compression processing on the cache data requested to be saved from the processor 10 in units of a predetermined cache line size. At this time, the compression algorithm is not limited to a specific algorithm but various algorithms can be used. For example, compression methods such as Huffman coding or base-delta-immediate may be used.

The compression processing unit 31 provides the control unit 34 with compression information corresponding to the compressed data size of the cache line data. For example, cache line data having a size of 64 bytes can be compressed into data having a size of at least 1 byte and a maximum size of 64 bytes according to the cache line data.

The decompression unit 32 restores the compressed cache line data to the data of the original cache line size before the compression processing by using the compression restoration algorithm corresponding to the compression algorithm of the compression processing unit 31. [

The cache table storage unit 33 stores sub-array usage information, that is, sub-array number information, in which compressed cache line data for each cache line tag is stored. At this time, the sub-array number information may be composed of bit data capable of representing N sub-arrays constituting one memory array in different forms. For example, when one memory array is composed of four subarrays, the subarray number information is composed of two bits of data capable of expressing four different types.

The control unit 34 stores the cache line data compressed through the compression processing unit 31 in the memory array MA of the cache memory 20 in response to a cache data storage request from the processor 10. [ At this time, the control unit 34 calculates the number of sub-arrays (SA) corresponding to the storage area where the compressed cache line data can be stored based on the compressed data size information provided from the compression processing unit 31, Array usage information corresponding to the number of sub-arrays is generated and stored in the cache table.

The control unit 34 divides the cache line data compressed through the compression processing unit 31 by the storage area size of the sub array SA and sequentially stores the cache line data in the sub array SA in a predetermined storage order.

For example, when the cache line size is 64 bytes, the memory array may be composed of four sub-arrays of 16 bytes, and the 64-byte cache line data is compressed according to the number of subarrays And can be divided into the first to fourth compression ranges.

 That is, the size of the compressed data in the first compression range is greater than or equal to 0 bytes and less than 16 bytes, the size of the compressed data in the second compression range is in the range of 16 bytes or more to less than 32 Bytes, To 48 bytes and the compression range of the fourth compression range is set to a range of 48 bytes or more to 64 bytes or less.

Since the control unit 34 requires only one sub-array for the compressed cache line data corresponding to the first compression range and needs to have two sub-arrays for the second compression range, the control unit 34 sets "01" Since three subarrays are required for the compression range, "10" is required for the fourth compression range, and four subarrays are required for the fourth compression range, so that the subarray number information composed of two bits of "11" is generated to manage the cache table.

The control unit 34 refers to the cache table for the cache line access request from the processor 10 and calls the cache line data compressed from the subarray SA in which the cache line data is stored in compression, To the restoring unit 32, and provides the cache line data restored to the pre-compression state provided from the decompression restoring unit 32 to the processor 10. [

The control unit 34 refers to the cache table for the refresh request from the processor 10 and provides the refresh selection signal select only to the sub array SA in which the compressed refresh target cache line data is actually stored , The refresh operation is performed only on the subarray (SA) in which the refresh target cache line data is stored.

Referring to FIG. 3, the first to fourth multiplexers MUX1 to MUX4, which are coupled to the first to fourth subarrays SA1 to SA4 of the memory array MA in which the corresponding cache line is stored, And the refresh selection signal select is applied only to the multiplexer (MUX) of the sub array SA in which the actually compressed cache line data is divided and stored. Therefore, only the sub-array SA coupled with the multiplexer into which both the refresh signal (refresh) and the refresh selection signal (select) are inputted is finally determined as the refresh target.

Next, the operation of the cache memory device having the above-described configuration with the refresh power consumption reduction function will be described with reference to the flowcharts shown in FIGS. 5 to 7. FIG.

Basically, the operation of the cache memory device having the refresh power saving function according to the present invention includes a cache data storing process (FIG. 5), a cache data accessing process (FIG. 6), and a cache data refreshing process .

As shown in FIG. 5, when a cache data storage request is received from the processor 10 (ST110), the controller 34 compresses the cache data in units of cache lines (ST120).

Then, the controller 34 calculates the number of sub-arrays to be used corresponding to the size of the compressed cache line data, and updates the cache table based on the calculated number of sub-arrays (ST140, ST140).

In addition, the controller 34 divides the compressed cache line data and stores the divided data in the memory array of the cache memory 33. The controller 34 sequentially stores the divided data in the sub-arrays constituting the memory array in accordance with a preset storage order (ST150 ).

Table 1 below illustrates the number of subarrays according to the size of compressed cache line data. The size of original cache line data is 64 bytes, and the memory array MA is composed of 4 subarrays (SA) having 16 byte storage areas. Lt; / RTI >

Compressed cache line data Number of sub-arrays used  0Byte ~ 16Byte One Less than 16Byte ~ 32Byte 2 Less than 32Byte ~ 48Byte 3 48Byte ~ 64Byte 4

That is, after compressing the cache line data, the cache line data is divided and divided into sub-array storage area units, thereby minimizing the storage area for independently controllable cache line data.

6, when the cache data access request is received from the processor 10 in a state where the cache line data is compressed and stored in the cache memory 20, the control unit 34 reads the cache table Array number information that actually stores the cache line data (ST210, ST220).

Next, the controller 34 accesses the memory array in which the corresponding cache line data is stored, and calls the cache line data divided and stored by sequentially or simultaneously approaching the sub-array storing order by the number of the corresponding sub-array in which the actual cache line data is stored And combines them to generate one compressed cache line data, and performs compression decompression processing on the compressed cache line data through the decompression unit 32 (ST230 to ST250).

Then, the controller 34 provides the cache line data decompressed to the original cache line size to the processor 10 (ST260).

7, when a cache data refresh request is issued from the processor 10 in a state where the cache line data is compressed and stored in the cache memory 20, the control unit 34 reads the cache table Array number information in which the corresponding cache line data is actually stored with respect to the refresh target cache line (ST310 and ST320).

The control unit 34 provides a refresh signal refresh to the memory array MA in which the cache line data to be refreshed is stored and outputs a refresh selection signal select And provides them to the subarrays SA in which the corresponding cache line data is stored (ST330 and ST340). At this time, the controller 34 provides a refresh signal and a refresh selection signal (select) to a multiplexer (MUX) coupled to the sub-array SA in FIG. 3, Only the refresh operation is performed.

Therefore, the refresh operation is performed for a smaller storage area than the cache memory device in which the conventional cache line data is stored in the memory array MA as it is, thereby reducing the refresh energy.

10: processor, 20: cache memory,
30: cache management module,
31: compression processing unit, 32: compression decompression unit,
33: cache table storage unit, 34: control unit.

Claims (12)

A processor for requesting storage of cache data and calling the stored cache data;
The memory array, which stores cache data in units of cache lines in response to a request from the processor, is composed of a plurality of subarrays having a predetermined size, and the cache line data is divided and stored in different subarrays A cache memory configured; And
The cache data is divided into units of a predetermined size by compressing the cache data in units of cache lines and then divided into different subarrays of the memory array and stored in the subarrays of the memory array, And a cache management module for calling compression cache line data divided and stored in the array to perform a decompression process on the compressed cache line data,
The cache management module comprising:
When a refresh signal and a refresh selection signal are both applied to a sub array in which refresh target cache line data having the same tag as an address received by the processor is stored in accordance with a refresh command of the processor, The cache memory device having a refresh power saving function.
The method according to claim 1,
And a plurality of subarrays constituting one memory array are configured to be able to access simultaneously.
The method according to claim 1,
Wherein the cache memory is comprised of eDRAM (Embedded Dynamic Random Access Memory).
The method according to claim 1,
A multiplexer is coupled and configured to correspond one-to-one to the sub-arrays,
The cache management module simultaneously provides the refresh signal to the multiplexers of all the subarrays constituting the memory array and checks the number of subarrays corresponding to the size of the compressed cache line data stored in the memory array, Only the sub-arrays combined with the multiplexer into which both the refresh signal and the refresh selection signal are inputted are configured to perform the refresh operation by providing the refresh selection signal only to the multiplexer combined with the sub-array in which the cache line data is stored A cache memory device having a refresh power saving function.
The method according to claim 1,
The memory array is configured to have a storage area equal in size to the cache line data size,
The N subarrays constituting the memory array are configured to have a predetermined storage order while being set to have a storage area of a size obtained by dividing the memory array storage area by N,
Wherein the cache management module is configured to divide the compressed cache line data into units of storage area size of the sub-array, and sequentially store the compressed cache line data in the sub-array in a preset storage order.
The method according to claim 1,
Wherein the cache management module includes a cache table in which sub-array usage information corresponding to a size of compressed data for each cache line is stored,
After the cache line data compression processing, the number of subarrays corresponding to the storage area capable of storing the compressed cache line data is calculated, and the subarray usage information corresponding to the calculated number of subarrays is generated and stored in the cache table Wherein the cache memory device has a refresh power consumption reduction function.
The method according to claim 6,
Wherein the sub-array usage information in the cache table is a number of sub-arrays in which compressed cache line data is stored, and bit data capable of representing N sub-arrays in different forms. / RTI >
A method for saving refresh power consumption of a cache memory device performing a refresh operation on a cache memory in addition to storing and recalling cache data in a cache memory in response to a request from the processor through a cache management module coupled between the cache memory and the processor In this case,
The cache management module compresses the cache data in units of cache lines in response to a cache data storage request from the processor and stores the compressed cache line data in a memory array having a cache line data size storage area of the cache memory, A cache data storage step of dividing the memory array storage area into N storage sub-arrays divided into N storage sub-arrays and sequentially storing the N sub-arrays constituting the memory array in a predetermined order;
A cache data access step of causing the cache management module to call decompression cache line data divided and stored from a subarray of the memory array according to a cache data access request from the processor,
When the cache management module receives a refresh signal and a refresh selection signal for a sub-array in which refresh target cache line data having a tag identical to an address received by the processor is stored in response to a refresh request from the processor, And a refresh step of performing refresh processing only on the sub-array in which the line data is stored.
9. The method of claim 8,
Wherein the cache management module calculates the number of subarrays corresponding to the compressed cache line data size and generates subarray usage information corresponding to the calculated number of subarrays,
And a cache table including sub-array usage information for each cache line is generated and managed.
10. The method of claim 9,
Wherein the sub-array usage information in the cache table is the number of sub-arrays in which compressed cache line data is stored, and bit data capable of representing N sub-arrays in different forms. How to save power consumption.
10. The method of claim 9,
The cache data accessing step includes: checking a number of sub-arrays for a corresponding cache line through the cache table in a cache management module; checking a number of sub-arrays corresponding to the number of sub- Generating one compressed cache line data by calling and combining the data; and decompressing the compressed cache line data. ≪ Desc / Clms Page number 19 >
10. The method of claim 9,
Wherein the refresh step comprises the steps of: providing the refresh signal to all sub-arrays of a memory array in which the refresh target cache line data is stored for a refresh request from the processor in the cache management module; A step of providing a refresh selection signal only to the subarrays corresponding to the number of subarrays, and a step of performing a refresh operation only on the subarrays to which both the refresh signal and the refresh selection signal are inputted Wherein the step of controlling the refresh power consumption comprises the steps of:

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