JP2004265972A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2004265972A
JP2004265972A JP2003052553A JP2003052553A JP2004265972A JP 2004265972 A JP2004265972 A JP 2004265972A JP 2003052553 A JP2003052553 A JP 2003052553A JP 2003052553 A JP2003052553 A JP 2003052553A JP 2004265972 A JP2004265972 A JP 2004265972A
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Japan
Prior art keywords
substrate
semiconductor element
brazing
solder
oxide film
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JP2003052553A
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Japanese (ja)
Inventor
Goro Ideta
吾朗 出田
Junichi Murai
淳一 村井
Koji Hiraoka
功治 平岡
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2003052553A priority Critical patent/JP2004265972A/en
Publication of JP2004265972A publication Critical patent/JP2004265972A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent generation of a sink mark in a wax member when bonding a semiconductor element and a ceramic substrate or bonding the ceramic substrate and a base substrate or the like. <P>SOLUTION: A method for manufacturing a semiconductor device is provided with a process for supplying the wax material to a part between the semiconductor element and the substrate, a process for melting the wax material, a process for holding the perimeter of the wax material to an oxidizing atmosphere in the state that the wax material is melted, and a process for solidifying the wax material after holding to a oxidizing atmosphere. Melting point of the wax material is at most 400°C, and it is desirable to include any one metal out of Sn, Pb, Bi, Zn, In, Au and Ag as main component. In the semiconductor device formed by the method, an oxide film whose thickness is at least 5 nm is formed in circumference surface of the wax member. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
この発明は、半導体素子をろう材で基板に接合した半導体装置に関し、特にその接合の信頼性を向上させる方法に関するものである。
【0002】
【従来の技術】
半導体素子とセラミック基板、或いはセラミック基板とベース基板などは半田等のろう材によって接合されることが多い。特許文献1は、半田を不活性雰囲気下(例えば窒素ガス中で)或いは還元性雰囲気下(例えば水素を4%程度含む窒素ガス中で)で溶融・凝固させる方法を開示している。こうすることによって、半導体素子とセラミック基板との接合面に酸化膜が形成されることを防いでいる。この時、固体の半田を接合部に供給してから外部より加熱し、半田を溶融させる方法と、予め溶融させた半田を接合部にあたる空隙に流し込む方法とがある。どちらの場合も、その後、冷却して半田を凝固させることによって接合が完成する。
【0003】
【特許文献1】
特開平10−163620号公報
【0004】
【発明が解決しようとする課題】
【0005】
半田は、溶融状態から固体状態に変化する時に、凝固収縮によって体積が3%程度減少する。そのため、基板と基板との接続部では、半田が最後に凝固する部分に入江状に半田が後退したエリアが発生することがある。この後退したエリアをここではヒケと呼ぶことにする。ヒケには半田が存在しないため、セラミック基板からベース板へ熱が流れる時の抵抗となり、放熱特性に悪影響を及ぼす。さらにこのヒケは、製品の使用される環境下で温度変化が加わった時に、セラミック基板とベース板の熱膨張係数の差異によって半田に熱応力が作用し、半田に疲労亀裂が発生する場合の起点となる。
【0006】
この発明は以上のような不具合を解決するためになされたもので、ろう材を使用して半導体装置を製作する際に、ろう材にヒケが発生することを防ぐことを目的とする。
【0007】
【課題を解決するための手段】
この発明に係る半導体装置は、半導体素子と、この半導体素子を搭載する基板と、半導体素子と基板の間に供給されたろう部材を備えており、ろう部材の外周表面に厚さ5nm以上の酸化膜が形成されているものである。
【0008】
【発明の実施の形態】
実施の形態1.
図1は、本発明に係わる半導体装置の断面を表す側面図である。シリコン基板等に形成された半導体素子1はセラミック基板2に搭載されている。セラミック基板2は、AlN等の熱伝導性の良いセラミック板で芯材が構成され、このセラミック板の上面と下面にはCu等の導体層11が形成されている。セラミック基板2はガラスエポキシなどの複合材料を基材とした基板であってもよく、リードフレームやブロック状の金属であってもよい。ベース板3はセラミック基板2を固定するための基材で、例えばCu合金、Al合金、あるいはSiCなどのセラミックスとの複合材料からなる。
【0009】
ソルダレジスト4はエポキシ樹脂等で形成され、ろう部材6の拡散範囲を制限する。ろう部材5、6はSnを主成分とするSn−37Pb合金半田で、その外周表面(通称フィレット)には厚さ5nm以上のSnの酸化膜8が形成されている。ろう部材5は半導体素子1とセラミック基板2とを接続し、ろう部材6はセラミック基板2とベース板3とを接続している。
【0010】
なお、ろう部材5、6はSn−37Pb合金に限られるものではなく、Sn,Pb,Bi,Zn,In,Au,Agの何れかを主成分とする、融点が400℃以下の合金であれば本発明に同様に適用出来る。中でも、Snを基合金とする半田は酸化膜が形成され易いので、好ましい。例えば金を主成分とする半田(例えば80Au−20Sn)であっても、酸素が十分な環境であれば、Snの酸化膜がフィレットを覆うことができる。また、ろう部材5とろう部材6は、同じ材質である必要はなく、異なる種類のものを適宜選択することが出来る。半導体素子1とセラミック基板2との間の熱伝導に比べ、セラミック基板2とベース板3との間の熱伝導の方が重要であるため、より酸化膜の形成され易いろう材をセラミック基板2とベース板3の間に供給してもよい。
【0011】
図2は、ろう部材5、6のフィレット部を拡大した図であり、酸化膜8aはろう部材5、6が溶融している時、酸化膜8bはろう部材5、6が凝固した時の形状を示している。図3は、ろう部材6のフィレットの外周形状を上面側から見た時の模式図であり、フィレット9aはろう部材6が溶融している時の形状を、フィレット9bはろう部材6が凝固した時の形状を示している。
【0012】
次に図4に従って、この半導体装置の製造方法を説明する。まず、大気中、不活性雰囲気中または還元性雰囲気中で、半導体素子1,板状半田5a,セラミック基板2,板状半田6a,ベース板3を重ね合わせる。このとき、電子部品の半田付け工程ではロジン系フラックスを用いることが一般的であるが、半導体素子の汚損を防ぐためにフラックスの使用を避けてもよい。
【0013】
その後、この重ね合わせた物を不活性雰囲気または還元性雰囲気中において半田の融点である183℃以上に加熱し、板状半田5a,6aを溶融させる。ここで、事前に、半導体素子1,セラミック基板2,ベース板3の接続面を清浄にしておく必要がある。溶融半田5b,6bは、それぞれ半導体素子1とセラミック基板2の間、セラミック基板2とベース板3の間に濡れ拡がり、空隙を満たす。
【0014】
その後、溶融半田5b,6bが溶融したままの状態で、雰囲気を大気に開放するなどして酸素を導入すると、溶融半田5b,6bの表面は直ちに強制酸化され、酸化膜8aが形成される。冷却して溶融半田5b,6bを凝固させると酸化膜8aは溶融半田5b,6bの凝固収縮によって変形し、酸化膜8bになる。この時、酸化膜8bが存在するために、溶融半田5b,6bは自由な変形を抑制されるので、半田接合部の全周で一様に収縮し、酸化膜8bの形状になるだけで、ヒケは発生しなくなる。
【0015】
すなわちフィレットの酸化膜8が溶融半田5b,6bから剥離しない限り溶融半田5b,6bの変形は抑制され、体積変化が生じても溶融半田5b,6bは自由に形状を変えることができない。その結果、酸化膜8aが酸化膜8bの形状に変形することでフィレットが一様に収縮するので一部分に凝固収縮が集中してヒケを形成することがなくなる。
【0016】
ただし、酸化膜8が常温の空気中で自然に形成されたいわゆる自然酸化膜であると、その厚さは2〜3nm程度にしかならず、膜強度が不十分になって破れてしまう。その結果,溶融半田5b,6bの自由な変形を許してしまい、ヒケを防止できない。フィレットの一様な収縮を確保するには、酸化膜8の厚さは5nm以上必要であるが、特に10nm以上であると効果がより確実になった。図5は図3と対比して比較されるべき図で、溶融半田6bの自由な変形によって、ヒケ7が形成されている状態を示している。半導体素子1に比べると、セラミック基板2の面積の方がかなり大きいため、ヒケ7はセラミック基板2とベース基板3の間で発生しやすいが、本発明によればセラミック基板2とベース基板3の間でもヒケの発生を防ぐことが出来た。
【0017】
なお、酸化膜を強制的に形成した後に冷却する過程で、溶融したろう材が中央部よりも先に接続部の外周部から凝固が開始しない様に、ベース板の中央部の温度を外周部よりも低くしておくことが好ましい。例えば、中央部の温度を周辺部よりも低温度に保持可能なヒートシンクをベース板に接触させることが考えられる。
【0018】
実施の形態2.
図6は、本発明の実施の形態2にかかわる半導体装置の製造方法を説明するための工程図である。図に従って、工程を説明する。まず、大気中、不活性雰囲気または還元性雰囲気中で、予め表面を清浄にしたベース板3の上に半田6cを供給し、加熱して溶融させる。この時、供給する半田6cの形態はペレット状でもワイヤ状でもリボン状でもあるいは液状でもよい。また、加熱は、半田6cを供給する前から行っても、供給後に行ってもよい。その後に、予め表面を清浄にしたセラミック基板2を重ね合わせると、溶融した半田6cはベース板3とセラミック基板2の間で広がって溶融半田6bの形状となり、濡れが完了する。
【0019】
さらに、セラミック基板2の上に半田5cを供給し、溶融させる。この時も、供給する半田の形態はペレット状でもワイヤ状でもリボン状でもあるいは液状でもよい。その後、予め表面を清浄にした半導体素子1を重ね合わせると、溶融した半田5cは半導体素子1とセラミック基板2の間で広がって溶融半田5bの形状となり、濡れが完了する。次いで、溶融半田5b,6bが溶融したままの状態で、雰囲気を大気に開放するなどして酸素を導入すると、溶融半田5b,6bの表面が強制酸化され、酸化膜8aが形成される。
【0020】
その後、冷却して溶融半田5b,6bを凝固させると酸化膜8aは半田5b,6bの凝固収縮によって変形し、酸化膜8bの形状になる。この時、酸化膜8aが存在するために、溶融半田5b,6bは自由な変形を抑制され、半田接続部の全周で一様に収縮するため、酸化膜8bの形状になるだけで、ヒケ7の発生を防止することができる。
【0021】
実施の形態3.
図7は、本発明の実施の形態3にかかわる半導体装置の製造方法における冷却工程を表す図である。図においてノズル10は冷却ガスを噴出する。実施の形態1または2に従って、工程を進めてきた後、最終工程において、ここに示すノズル10から酸化性のガス、例えば空気、酸素等を噴出させ、溶融半田5b,6bのフィレットに吹き付け、急冷する。これによって、溶融半田5b,6bはフィレットの周辺から凝固が始まり、最終凝固部分が半田接合部の内部に収まるため、実施の形態1または2の場合よりも、さらにヒケ7を防止しやすくなる。
【0022】
【発明の効果】
この発明に係る半導体装置は、半導体素子と、この半導体素子を搭載する基板と、半導体素子と基板の間に供給されたろう部材を備え、ろう部材の外周表面に厚さ5nm以上の酸化膜が形成されていることにより、ヒケの発生を抑止できる。
【図面の簡単な説明】
【図1】本発明に係わる半導体装置の断面を表す側面図である。
【図2】半導体装置のフィレットを説明するための拡大図である。
【図3】ヒケが形成されていないフィレットの形状を説明するための図である。
【図4】実施の形態1に係わる製造方法を説明するための図である。
【図5】ヒケが形成されているフィレットの形状を説明するための図である。
【図6】実施の形態2に係わる製造方法を説明するための図である。
【図7】実施の形態3に係わる製造方法を説明するための図である。
【符号の説明】
1 半導体素子、2 セラミック基板、3 ベース板、4 ソルダレジスト、5 ろう部材、 6 ろう部材、 7 ヒケ、 8 酸化膜、 9 フィレット、 10 ノズル。
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device in which a semiconductor element is joined to a substrate with a brazing material, and particularly to a method for improving the reliability of the joining.
[0002]
[Prior art]
A semiconductor element and a ceramic substrate, or a ceramic substrate and a base substrate, are often joined by a brazing material such as solder. Patent Document 1 discloses a method of melting and solidifying solder under an inert atmosphere (for example, in nitrogen gas) or a reducing atmosphere (for example, in nitrogen gas containing about 4% of hydrogen). This prevents an oxide film from being formed on the joint surface between the semiconductor element and the ceramic substrate. At this time, there are a method in which solid solder is supplied to the joint and then heated from the outside to melt the solder, and a method in which the solder melted in advance is poured into a gap corresponding to the joint. In either case, the joint is then completed by cooling and solidifying the solder.
[0003]
[Patent Document 1]
JP 10-163620 A
[Problems to be solved by the invention]
[0005]
When the solder changes from a molten state to a solid state, the volume is reduced by about 3% due to solidification shrinkage. For this reason, in the connection portion between the substrates, an area where the solder retreats in a cove shape may occur at a portion where the solder solidifies last. This retreated area will be called a sink here. Since there is no solder in the sink, it becomes a resistance when heat flows from the ceramic substrate to the base plate, which adversely affects the heat radiation characteristics. In addition, this sink mark is a starting point in the case where a thermal stress is applied to the solder due to the difference in the coefficient of thermal expansion between the ceramic substrate and the base plate when a temperature change is applied in the environment where the product is used, and a fatigue crack occurs in the solder. It becomes.
[0006]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to prevent sinks from occurring in a brazing material when a semiconductor device is manufactured using the brazing material.
[0007]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes a semiconductor element, a substrate on which the semiconductor element is mounted, and a brazing member supplied between the semiconductor element and the substrate. An oxide film having a thickness of 5 nm or more is formed on an outer peripheral surface of the brazing member. Are formed.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a side view showing a cross section of a semiconductor device according to the present invention. A semiconductor element 1 formed on a silicon substrate or the like is mounted on a ceramic substrate 2. The ceramic substrate 2 has a core made of a ceramic plate having good thermal conductivity such as AlN, and a conductor layer 11 such as Cu is formed on the upper and lower surfaces of the ceramic plate. The ceramic substrate 2 may be a substrate made of a composite material such as glass epoxy, or may be a lead frame or a block-shaped metal. The base plate 3 is a base material for fixing the ceramic substrate 2 and is made of, for example, a composite material with a ceramic such as a Cu alloy, an Al alloy, or SiC.
[0009]
The solder resist 4 is formed of an epoxy resin or the like, and limits the diffusion range of the brazing member 6. The brazing members 5 and 6 are Sn-37Pb alloy solder containing Sn as a main component, and a Sn oxide film 8 having a thickness of 5 nm or more is formed on the outer peripheral surface (commonly called fillet). The brazing member 5 connects the semiconductor element 1 and the ceramic substrate 2, and the brazing member 6 connects the ceramic substrate 2 and the base plate 3.
[0010]
The brazing members 5 and 6 are not limited to the Sn-37Pb alloy, but may be any alloy containing Sn, Pb, Bi, Zn, In, Au, or Ag as a main component and having a melting point of 400 ° C. or less. The present invention can be similarly applied to the present invention. Among them, a solder using Sn as a base alloy is preferable since an oxide film is easily formed. For example, even with a solder containing gold as a main component (for example, 80Au-20Sn), an Sn oxide film can cover the fillet if oxygen is sufficient. Further, the brazing member 5 and the brazing member 6 do not need to be made of the same material, and different types can be appropriately selected. Since the heat conduction between the ceramic substrate 2 and the base plate 3 is more important than the heat conduction between the semiconductor element 1 and the ceramic substrate 2, the brazing material on which an oxide film is more easily formed is replaced with the ceramic substrate 2. And the base plate 3.
[0011]
FIG. 2 is an enlarged view of the fillet portions of the brazing members 5 and 6. The oxide film 8a is formed when the brazing members 5 and 6 are melted, and the oxide film 8b is formed when the brazing members 5 and 6 are solidified. Is shown. FIG. 3 is a schematic diagram when the outer peripheral shape of the fillet of the brazing member 6 is viewed from the upper surface side. The fillet 9a has a shape when the brazing member 6 is molten, and the fillet 9b has a solidified brazing member 6. The shape at the time is shown.
[0012]
Next, a method for manufacturing the semiconductor device will be described with reference to FIG. First, the semiconductor element 1, the plate-like solder 5a, the ceramic substrate 2, the plate-like solder 6a, and the base plate 3 are superposed in the air, in an inert atmosphere, or in a reducing atmosphere. At this time, a rosin-based flux is generally used in the soldering step of the electronic component, but the use of the flux may be avoided in order to prevent the semiconductor element from being stained.
[0013]
Thereafter, the superposed material is heated to 183 ° C. or more, which is the melting point of the solder, in an inert atmosphere or a reducing atmosphere to melt the plate-like solders 5a and 6a. Here, it is necessary to clean the connection surfaces of the semiconductor element 1, the ceramic substrate 2, and the base plate 3 in advance. The molten solders 5b and 6b spread between the semiconductor element 1 and the ceramic substrate 2 and between the ceramic substrate 2 and the base plate 3 to fill the gaps.
[0014]
Thereafter, when oxygen is introduced by releasing the atmosphere to the atmosphere while the molten solders 5b and 6b remain molten, the surfaces of the molten solders 5b and 6b are immediately forcibly oxidized to form an oxide film 8a. When the molten solders 5b and 6b are solidified by cooling, the oxide film 8a is deformed by the solidification shrinkage of the molten solders 5b and 6b to become the oxide film 8b. At this time, since the molten solder 5b, 6b is restrained from free deformation due to the presence of the oxide film 8b, the molten solder 5b, 6b uniformly shrinks over the entire periphery of the solder joint, and only has the shape of the oxide film 8b. No sink marks will occur.
[0015]
That is, as long as the oxide film 8 of the fillet does not peel off from the molten solders 5b, 6b, the deformation of the molten solders 5b, 6b is suppressed, and the shape of the molten solders 5b, 6b cannot be freely changed even if the volume changes. As a result, the fillet is uniformly shrunk by the deformation of the oxide film 8a into the shape of the oxide film 8b, so that coagulation and shrinkage do not concentrate on a part of the fillet, so that sink is not formed.
[0016]
However, if the oxide film 8 is a so-called natural oxide film formed naturally in air at normal temperature, the thickness is only about 2 to 3 nm, and the film strength is insufficient and the film is broken. As a result, free deformation of the molten solders 5b and 6b is allowed, and sinks cannot be prevented. In order to ensure uniform shrinkage of the fillet, the thickness of the oxide film 8 needs to be 5 nm or more, but if the thickness is 10 nm or more, the effect becomes more reliable. FIG. 5 is a diagram to be compared with FIG. 3 and shows a state in which sink marks 7 are formed by free deformation of the molten solder 6b. Since the area of the ceramic substrate 2 is much larger than that of the semiconductor element 1, the sink marks 7 are more likely to be generated between the ceramic substrate 2 and the base substrate 3; It was possible to prevent the occurrence of sink marks in the meantime.
[0017]
In addition, in the process of cooling after forcibly forming the oxide film, the temperature of the central portion of the base plate is set at the outer peripheral portion so that the molten brazing material does not start solidifying from the outer peripheral portion of the connection portion before the central portion. It is preferable to keep it lower. For example, it is conceivable that a heat sink capable of maintaining the temperature of the central part lower than that of the peripheral part is brought into contact with the base plate.
[0018]
Embodiment 2 FIG.
FIG. 6 is a process chart illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. The steps will be described with reference to the drawings. First, the solder 6c is supplied on the base plate 3 whose surface has been cleaned in advance in the air, an inert atmosphere or a reducing atmosphere, and is heated and melted. At this time, the form of the supplied solder 6c may be a pellet, a wire, a ribbon, or a liquid. The heating may be performed before or after the solder 6c is supplied. Thereafter, when the ceramic substrate 2 whose surface has been cleaned in advance is overlaid, the molten solder 6c spreads between the base plate 3 and the ceramic substrate 2 to have a shape of the molten solder 6b, and the wetting is completed.
[0019]
Further, the solder 5c is supplied onto the ceramic substrate 2 and melted. Also at this time, the form of the supplied solder may be a pellet, a wire, a ribbon, or a liquid. Thereafter, when the semiconductor element 1 whose surface has been cleaned in advance is overlapped, the molten solder 5c spreads between the semiconductor element 1 and the ceramic substrate 2 to have a shape of the molten solder 5b, and the wetting is completed. Next, when oxygen is introduced by, for example, opening the atmosphere to the atmosphere while the molten solders 5b and 6b remain molten, the surfaces of the molten solders 5b and 6b are forcibly oxidized to form an oxide film 8a.
[0020]
Thereafter, when the molten solders 5b and 6b are solidified by cooling, the oxide film 8a is deformed by the solidification shrinkage of the solders 5b and 6b, and takes the shape of the oxide film 8b. At this time, the presence of the oxide film 8a suppresses the free deformation of the molten solders 5b and 6b, and uniformly shrinks over the entire periphery of the solder connection portion. 7 can be prevented.
[0021]
Embodiment 3 FIG.
FIG. 7 is a diagram illustrating a cooling step in the method for manufacturing a semiconductor device according to the third embodiment of the present invention. In the figure, a nozzle 10 jets a cooling gas. After proceeding according to the first or second embodiment, in the final step, an oxidizing gas, for example, air, oxygen, or the like is ejected from the nozzle 10 shown here, and is sprayed on the fillets of the molten solders 5b and 6b, and quenched. I do. As a result, the molten solders 5b and 6b begin to solidify from the periphery of the fillet, and the final solidified portion is accommodated inside the solder joint, so that the sink mark 7 can be more easily prevented than in the case of the first or second embodiment.
[0022]
【The invention's effect】
A semiconductor device according to the present invention includes a semiconductor element, a substrate on which the semiconductor element is mounted, and a brazing member supplied between the semiconductor element and the substrate, and an oxide film having a thickness of 5 nm or more is formed on an outer peripheral surface of the brazing member. By doing so, the occurrence of sink marks can be suppressed.
[Brief description of the drawings]
FIG. 1 is a side view showing a cross section of a semiconductor device according to the present invention.
FIG. 2 is an enlarged view for explaining a fillet of a semiconductor device.
FIG. 3 is a view for explaining the shape of a fillet in which sink marks are not formed.
FIG. 4 is a view for explaining the manufacturing method according to the first embodiment;
FIG. 5 is a view for explaining the shape of a fillet in which sink marks are formed.
FIG. 6 is a diagram for explaining the manufacturing method according to the second embodiment.
FIG. 7 is a view for explaining a manufacturing method according to a third embodiment;
[Explanation of symbols]
Reference Signs List 1 semiconductor element, 2 ceramic substrate, 3 base plate, 4 solder resist, 5 brazing member, 6 brazing member, 7 sink mark, 8 oxide film, 9 fillet, 10 nozzle.

Claims (7)

半導体素子と、この半導体素子を搭載する基板と、半導体素子と基板の間に供給されたろう部材を備えてなり、前記ろう部材の外周表面に厚さ5nm以上の酸化膜が形成されていることを特徴とする半導体装置。A semiconductor element, a substrate on which the semiconductor element is mounted, and a brazing member supplied between the semiconductor element and the substrate, wherein an oxide film having a thickness of 5 nm or more is formed on an outer peripheral surface of the brazing member. Characteristic semiconductor device. 半導体素子と、この半導体素子を搭載する基板と、半導体素子と基板の間に供給された第1のろう部材と、前記基板を搭載するベース板と、前記基板とベース板の間に供給された第2のろう部材を備えてなり、少なくとも前記第2のろう部材の外周表面に厚さ5nm以上の酸化膜が形成されていることを特徴とする半導体装置。A semiconductor element, a substrate on which the semiconductor element is mounted, a first brazing member supplied between the semiconductor element and the substrate, a base plate mounting the substrate, and a second brazing member supplied between the substrate and the base plate. A semiconductor device, comprising: a brazing member; and an oxide film having a thickness of 5 nm or more is formed on at least an outer peripheral surface of the second brazing member. 半導体素子と基板の間にろう材を供給する工程と、前記ろう材を溶融させる工程と、前記ろう材が溶融した状態でろう材の周辺を酸化性雰囲気に保持する工程と、酸化性雰囲気に保持してからろう材を凝固させる工程を備えてなる半導体装置の製造方法。A step of supplying a brazing material between the semiconductor element and the substrate, a step of melting the brazing material, a step of maintaining the periphery of the brazing material in an oxidizing atmosphere while the brazing material is molten, A method for manufacturing a semiconductor device, comprising a step of solidifying a brazing material after holding. ろう材を溶融させる工程の前に、基板とベース板の間にろう材を供給する工程を備えていることを特徴とする請求項3記載の半導体装置の製造方法。4. The method according to claim 3, further comprising a step of supplying a brazing material between the substrate and the base plate before the step of melting the brazing material. ろう材を溶融させる工程を、不活性雰囲気または還元性雰囲気で行うことを特徴とする請求項3または4記載の半導体装置の製造方法。5. The method according to claim 3, wherein the step of melting the brazing material is performed in an inert atmosphere or a reducing atmosphere. ろう材の融点は、400℃以下であることを特徴とする請求項3または4記載の半導体装置の製造方法。5. The method according to claim 3, wherein the melting point of the brazing material is 400 [deg.] C. or less. ろう材は、Sn,Pb、Bi、Zn,In、Au,Agの何れか一つの金属を主成分として含むことを特徴とする請求項6記載の半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 6, wherein the brazing material contains any one of Sn, Pb, Bi, Zn, In, Au, and Ag as a main component.
JP2003052553A 2003-02-28 2003-02-28 Semiconductor device and its manufacturing method Pending JP2004265972A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007311526A (en) * 2006-05-18 2007-11-29 Mitsubishi Materials Corp Power module, substrate thereof, and manufacturing method thereof
JP2008078201A (en) * 2006-09-19 2008-04-03 Fujitsu Ltd Semiconductor device and method for manufacturing same
JP2014146644A (en) * 2013-01-28 2014-08-14 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007311526A (en) * 2006-05-18 2007-11-29 Mitsubishi Materials Corp Power module, substrate thereof, and manufacturing method thereof
JP2008078201A (en) * 2006-09-19 2008-04-03 Fujitsu Ltd Semiconductor device and method for manufacturing same
US8513800B2 (en) 2006-09-19 2013-08-20 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same
JP2014146644A (en) * 2013-01-28 2014-08-14 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same

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