JP2011243752A - Semiconductor device manufacturing method, internal semiconductor connection member, and internal semiconductor connection member group - Google Patents

Semiconductor device manufacturing method, internal semiconductor connection member, and internal semiconductor connection member group Download PDF

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Publication number
JP2011243752A
JP2011243752A JP2010114805A JP2010114805A JP2011243752A JP 2011243752 A JP2011243752 A JP 2011243752A JP 2010114805 A JP2010114805 A JP 2010114805A JP 2010114805 A JP2010114805 A JP 2010114805A JP 2011243752 A JP2011243752 A JP 2011243752A
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Japan
Prior art keywords
solder
internal connection
connection member
metal piece
semiconductor
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JP2010114805A
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Japanese (ja)
Inventor
Yoshihiro Tomita
佳宏 冨田
Takahiro Matsuo
隆広 松尾
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Panasonic Corp
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Panasonic Corp
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Priority to JP2010114805A priority Critical patent/JP2011243752A/en
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Abstract

PROBLEM TO BE SOLVED: To achieve easy soldering connection by lead-free solder having a melting point of 260°C or higher.SOLUTION: An internal connection member 70 is disposed to connect lead-free solder films 72a, 72b formed on a metal piece 71 to an electrode pad 21 of a semiconductor chip 10. By fusing the solder films 72a, 72b by heating, the internal connection member 70 and the semiconductor chip 10 are connected by soldering. Each melting point of the solder films 72a, 72b is 260°C or higher.

Description

本発明は、半導体装置の製造方法、半導体内部接続部材および半導体内部接続部材群に関し、特に、鉛フリー半田を使用する半導体装置の製造方法、半導体内部接続部材および半導体内部接続部材群に関する。   The present invention relates to a method for manufacturing a semiconductor device, a semiconductor internal connection member, and a semiconductor internal connection member group, and more particularly to a method for manufacturing a semiconductor device using lead-free solder, a semiconductor internal connection member, and a semiconductor internal connection member group.

従来の半導体パッケージの内部接続として、リードフレームに半導体チップを搭載し固定するダイボンド工程などにおいて、８５％以上の高濃度の鉛を含有する高温鉛半田による接続が用いられている。   As an internal connection of a conventional semiconductor package, a connection using a high-temperature lead solder containing high-concentration lead of 85% or more is used in a die bonding process for mounting and fixing a semiconductor chip on a lead frame.

近年の世界的な環境問題への関心の高まりや法規制などの動きから、鉛を含有しない鉛フリー化への要求が高まっている。そこで、鉛フリー半田材料による半導体内部接続方法の開発が盛んに行われている。   In recent years, there has been an increasing demand for lead-free products that do not contain lead due to the growing interest in global environmental issues and the movement of laws and regulations. Therefore, development of a semiconductor internal connection method using a lead-free solder material has been actively performed.

従来の半導体内部接続方法では、半導体チップを搭載するダイパッドを有するリードフレームを還元雰囲気中で高温に加熱し、ダイパッド上に半田を供給し、溶融した半田上に裏面がメタライズされた半導体チップをマウントする。これにより、半導体チップをダイパッドに固定するとともに電気的接続を取る。   In a conventional semiconductor internal connection method, a lead frame having a die pad on which a semiconductor chip is mounted is heated to a high temperature in a reducing atmosphere, solder is supplied onto the die pad, and a semiconductor chip whose back surface is metallized is mounted on the molten solder. To do. Thereby, the semiconductor chip is fixed to the die pad and is electrically connected.

特許文献１では、半導体チップをダイパッドに搭載する前に応力緩衝板をダイパッドに搭載する。これにより、ダイパッドと半導体チップとの間の熱膨張率差に起因する応力の緩和を図っている。   In Patent Document 1, a stress buffer plate is mounted on a die pad before the semiconductor chip is mounted on the die pad. As a result, the stress caused by the difference in thermal expansion coefficient between the die pad and the semiconductor chip is reduced.

また、特に大電流を扱うパワー半導体素子において、半導体チップの電極パッド側の接続をワイヤーボンドではなく半田で行っているものもある。この場合、当該接続には、高温鉛半田が用いられている。   In some power semiconductor elements that handle particularly large currents, there are some semiconductor chip electrode pad side connections that are made by soldering rather than by wire bonding. In this case, high temperature lead solder is used for the connection.

その接続工法では、以下の処理が行われる。まず、半導体チップの電極パッド上に半田箔や半田ペーストの形で半田材料を供給する。そして、その供給した半田上にリード部材を搭載したものを還元性の雰囲気炉内に配置し、当該半田を加熱溶融する。これにより、電極パッドとリード部材とを半田接続する（例えば、特許文献２参照）。   In the connection method, the following processing is performed. First, a solder material is supplied in the form of solder foil or solder paste onto the electrode pads of the semiconductor chip. Then, a lead member mounted on the supplied solder is placed in a reducing atmosphere furnace, and the solder is heated and melted. Thereby, the electrode pad and the lead member are solder-connected (for example, refer to Patent Document 2).

特開２００６−１９０８５０号公報JP 2006-190850 A 特開昭５８−１２８７４８号公報JP 58-128748 A

従来、半導体パッケージの内部接続として半導体チップ裏面のダイボンドや電極パッドのリード接続に用いられている高温鉛半田は、「糸半田」、「半田箔」、「半田ペースト」の形で供給されて来た。   Conventionally, high-temperature lead solder used for die bonding on the backside of semiconductor chips and lead connection of electrode pads as internal connections in semiconductor packages has been supplied in the form of "thread solder", "solder foil", and "solder paste" It was.

ダイスボンドなど半導体製造装置への連続供給性から、糸半田が最も広く使われており、糸半田の供給が困難な場合に半田箔が用いられている。半田ペーストはプリント基板への部品実装に多く使われている。しかしながら、半田ペーストは、ペースト内の溶剤などの揮発成分やフラックス等の腐食性残渣の問題があり一部の半導体パッケージの使用に留まっている。   Yarn solder is most widely used because of its continuous supply capability to semiconductor manufacturing equipment such as die bonding, and solder foil is used when it is difficult to supply yarn solder. Solder paste is often used for mounting components on printed circuit boards. However, the solder paste has a problem of volatile components such as a solvent in the paste and a corrosive residue such as a flux, so that only some semiconductor packages are used.

一方、半導体内部接続に用いる半田材料としては半導体パッケージの半田付けに耐える必要がある。そのため、耐リフロー性を考慮すると、半導体内部接続に用いる半田材料の融点は２６０℃以上である必要がある。   On the other hand, it is necessary to withstand soldering of a semiconductor package as a solder material used for semiconductor internal connection. Therefore, considering reflow resistance, the melting point of the solder material used for semiconductor internal connection needs to be 260 ° C. or higher.

しかしながら、融点が２６０℃以上の鉛フリー半田を、半導体内部接続等における半田接続に適用するのは困難である。   However, it is difficult to apply lead-free solder having a melting point of 260 ° C. or higher to solder connection in semiconductor internal connection or the like.

本発明は、上述の問題点を解決するためになされたものであって、その目的は、融点が２６０℃以上の鉛フリー半田による容易な半田接続を実現する、半導体装置の製造方法等を提供することである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device, etc., which realizes easy solder connection using lead-free solder having a melting point of 260 ° C. or higher. It is to be.

上述の課題を解決するために、この発明のある局面に従う半導体装置の製造方法は、内部接続部材と半田接続される半導体チップを含む半導体装置の製造方法である。前記半導体チップには、電極が形成されており、前記内部接続部材は、所定形状の金属片と、鉛フリーの半田皮膜とを含み、前記金属片の表面の少なくとも一部には、前記半田皮膜が形成され、前記半田皮膜の融点は、２６０℃以上であり、前記半導体装置の製造方法は、前記金属片に形成される前記半田皮膜と、前記半導体チップの前記電極とが少なくとも接するように前記内部接続部材または前記半導体チップを配置する第１工程と、前記半田皮膜を加熱溶融することにより、前記内部接続部材と前記半導体チップとを半田接続する第２工程とを含む。   In order to solve the above-described problem, a method for manufacturing a semiconductor device according to an aspect of the present invention is a method for manufacturing a semiconductor device including a semiconductor chip solder-connected to an internal connection member. An electrode is formed on the semiconductor chip, and the internal connection member includes a metal piece having a predetermined shape and a lead-free solder film, and at least a part of the surface of the metal piece has the solder film And the melting point of the solder film is 260 ° C. or higher, and the method for manufacturing the semiconductor device is such that the solder film formed on the metal piece and the electrode of the semiconductor chip are at least in contact with each other. A first step of disposing the internal connection member or the semiconductor chip, and a second step of soldering the internal connection member and the semiconductor chip by heating and melting the solder film.

すなわち、融点が２６０℃以上の鉛フリーの半田皮膜が予め形成された金属片を含む内部接続部材を使用して、内部接続部材と半導体チップとが半田接続される。したがって、融点が２６０℃以上の鉛フリー半田による容易な半田接続を実現することができる。   That is, the internal connection member and the semiconductor chip are solder-connected using an internal connection member including a metal piece on which a lead-free solder film having a melting point of 260 ° C. or higher is previously formed. Therefore, it is possible to realize easy solder connection using lead-free solder having a melting point of 260 ° C. or higher.

また、好ましくは、前記半導体装置には、インナーリード部が形成されたリードフレームが使用され、前記金属片の形状は、前記半導体チップの前記電極と、前記リードフレームの前記インナーリード部とを跨ぐ形状であり、前記電極および前記インナーリード部の上方に前記金属片を配置した状態において、前記半田皮膜が形成された前記金属片の表面の一部は、前記金属片のうち、前記電極および前記インナーリード部にそれぞれ対向する第１領域および第２領域であり、前記第１工程では、前記第１領域に形成された半田皮膜および前記第２領域に形成された半田皮膜を、それぞれ、前記電極および前記インナーリード部に接するように前記内部接続部材を配置し、前記第２工程では、前記第１領域に形成された半田皮膜および前記第２領域に形成された半田皮膜を加熱溶融することにより、前記内部接続部材を前記半導体チップおよび前記リードフレームに半田接続する。   Preferably, the semiconductor device uses a lead frame in which an inner lead portion is formed, and the shape of the metal piece straddles the electrode of the semiconductor chip and the inner lead portion of the lead frame. In the state in which the metal piece is disposed above the electrode and the inner lead portion, a part of the surface of the metal piece on which the solder film is formed is, among the metal pieces, the electrode and the A first region and a second region facing the inner lead portion, respectively, and in the first step, the solder film formed in the first region and the solder film formed in the second region are respectively connected to the electrodes. The internal connection member is disposed so as to be in contact with the inner lead portion, and in the second step, the solder film formed on the first region and the first By heating and melting the solder film formed on the region, to the solder connecting the inner connecting member to said semiconductor chip and the lead frame.

また、好ましくは、前記半導体装置には、金属片としてのリードフレームが使用され、
前記リードフレームの少なくとも一部には、前記半田皮膜が形成され、前記半田皮膜が形成された、前記リードフレームの少なくとも一部は、前記内部接続部材であり、前記第２工程では、前記内部接続部材としての前記リードフレームの少なくとも一部と、前記半導体チップとを半田接続する。 Preferably, the semiconductor device uses a lead frame as a metal piece,
At least a part of the lead frame is formed with the solder film, and the solder film is formed. At least a part of the lead frame is the internal connection member, and in the second step, the internal connection is performed. At least a part of the lead frame as a member is solder-connected to the semiconductor chip.

また、好ましくは、前記半導体装置には、ダイパッドが形成されたリードフレームが使用され、前記金属片の形状は、平面形状であり、前記金属片の主面および該主面の反対面に前記半田皮膜が形成された該金属片は、前記内部接続部材であり、前記半導体装置の製造方法は、さらに、前記金属片の反対面に形成された半田皮膜と前記ダイパッドとが接するように、前記内部接続部材を配置する工程を含み、前記第２工程では、前記金属片の反対面に形成された半田皮膜および前記金属片の主面に形成された半田皮膜を過熱溶融することにより、前記内部接続部材と前記ダイパッドとを半田接続し、前記第１工程では、前記ダイパッドに半田接続された前記内部接続部材における前記金属片の主面に形成された溶融した半田皮膜と、前記半導体チップの前記電極とが接するように前記半導体チップを配置し、前記内部接続部材と前記半導体チップとが半田接続される。   Preferably, in the semiconductor device, a lead frame in which a die pad is formed is used, and the shape of the metal piece is a planar shape, and the solder is formed on a main surface of the metal piece and an opposite surface of the main surface. The metal piece on which the film is formed is the internal connection member, and the manufacturing method of the semiconductor device further includes the internal part so that the solder film formed on the opposite surface of the metal piece and the die pad are in contact with each other. Including a step of arranging a connection member, and in the second step, the internal connection is performed by overheating and melting a solder film formed on the opposite surface of the metal piece and a solder film formed on the main surface of the metal piece. A member and the die pad are solder-connected, and in the first step, a molten solder film formed on a main surface of the metal piece in the internal connection member solder-connected to the die pad, and the semiconductor The semiconductor chip is arranged such that the electrode of the chip is in contact, wherein the internal connecting member and the semiconductor chip are soldered.

この発明の他の局面に従う半導体内部接続部材は、半田接続に使用される。前記半導体内部接続部材は、金属片と、鉛フリーの半田皮膜とを含み、前記金属片の表面の少なくとも一部には、前記半田皮膜が形成され、前記半田皮膜の融点は、２６０℃以上である。   A semiconductor internal connection member according to another aspect of the present invention is used for solder connection. The semiconductor internal connection member includes a metal piece and a lead-free solder film, and the solder film is formed on at least a part of the surface of the metal piece, and the melting point of the solder film is 260 ° C. or higher. is there.

すなわち、半導体内部接続部材は、融点が２６０℃以上の鉛フリーの半田皮膜が形成されている金属片を含む。この半導体内部接続部材を使用することにより、融点が２６０℃以上の鉛フリーの半田皮膜を過熱溶融するという簡単な工程で、半田接続対象となる箇所に、半導体内部接続部材を容易に半田接続することができる。つまり、融点が２６０℃以上の鉛フリー半田による容易な半田接続を実現することができる。   That is, the semiconductor internal connection member includes a metal piece on which a lead-free solder film having a melting point of 260 ° C. or higher is formed. By using this semiconductor internal connection member, the semiconductor internal connection member can be easily soldered to a location to be soldered by a simple process of overheating and melting a lead-free solder film having a melting point of 260 ° C. or higher. be able to. That is, it is possible to realize easy solder connection using lead-free solder having a melting point of 260 ° C. or higher.

また、好ましくは、前記金属片の形状は、半田接続の対象となる少なくとも２箇所を繋ぐ形状である。   Preferably, the shape of the metal piece is a shape connecting at least two places to be soldered.

また、好ましくは、前記金属片の熱膨張率は、Ｃｕの熱膨張率とＳｉの熱膨張率との間の値である。   Preferably, the thermal expansion coefficient of the metal piece is a value between the thermal expansion coefficient of Cu and the thermal expansion coefficient of Si.

また、好ましくは、前記金属片の表面粗さＲａは、０．３μｍ以上である。
また、好ましくは、前記金属片は、Ｃｕを主組成とし、前記金属片の形状は、平面形状であり、前記半田皮膜は、Ｂｉを主組成とし、前記金属片の表面には、Ｂｉを主組成とする前記半田皮膜が直接形成される。 Preferably, the metal piece has a surface roughness Ra of 0.3 μm or more.
Preferably, the metal piece has a main composition of Cu, the shape of the metal piece has a planar shape, the solder film has a main composition of Bi, and Bi is mainly formed on the surface of the metal piece. The solder film having the composition is directly formed.

Ｃｕを主組成とする金属片は酸化され易いため、通常半田接合が行われる面にはＮｉやＡｇなどのめっき皮膜が形成される。しかしながら、本態様によればＣｕの上に酸化膜を介さずに直接半田皮膜を形成できる。   Since the metal piece mainly composed of Cu is easily oxidized, a plating film such as Ni or Ag is formed on the surface on which solder bonding is usually performed. However, according to this aspect, a solder film can be formed directly on Cu without using an oxide film.

また、好ましくは、前記半田皮膜の表面には、さらに、ＡｇまたはＡｕ薄膜が形成される。   Preferably, an Ag or Au thin film is further formed on the surface of the solder film.

これにより、半田皮膜の表面酸化を防止し、安定した半田接続を実現できる。
また、好ましくは、前記半田皮膜は、Ｚｎ、Ａｌを主組成とする。 Thereby, the surface oxidation of the solder film can be prevented and stable solder connection can be realized.
Preferably, the solder film is mainly composed of Zn and Al.

また、好ましくは、前記半田皮膜は、２以上の異なる材料の層を少なくとも含む複数の層により構成される。   Preferably, the solder film is composed of a plurality of layers including at least two layers of different materials.

これにより、原料として半田合金化しにくい組成であっても、半田接合時に溶融することにより、所望の組成の合金を形成することができる。   Thereby, even if it is a composition which is hard to make a solder alloy as a raw material, the alloy of a desired composition can be formed by melting at the time of solder joining.

また、好ましくは、前記複数の層のうちの第１層は、融点が２６０℃から４００℃の間の材料を主組成とし、前記第１層に隣接する第２層の材料の融点は、前記第１層の組成の材料の融点より低く、前記第２層は、半田溶融時に、前記第１層の組成を前記第２層に取り込んで合成半田となり、当該合成半田の融点は、２６０℃以上となる。   Preferably, the first layer of the plurality of layers is mainly composed of a material having a melting point between 260 ° C. and 400 ° C., and the melting point of the material of the second layer adjacent to the first layer is The melting point of the material of the first layer is lower than the melting point of the material. When the solder is melted, the composition of the first layer is taken into the second layer and becomes a synthetic solder. It becomes.

また、好ましくは、前記複数の層は、Ｓｎを主組成とする層およびＣｕを主組成とする層を含む。   Preferably, the plurality of layers include a layer mainly composed of Sn and a layer mainly composed of Cu.

また、好ましくは、前記複数の層は、Ｂｉを主組成とする層とＣｕを主組成とする層とを含む。   Preferably, the plurality of layers include a layer mainly composed of Bi and a layer mainly composed of Cu.

また、好ましくは、前記複数の層は、Ｂｉを主組成とする層とＡｇを主組成とする層を含む。   Preferably, the plurality of layers include a layer mainly composed of Bi and a layer mainly composed of Ag.

また、好ましくは、前記複数の層は、Ｂｉを主組成とする層とＮｉを主組成とする層を含む。   Preferably, the plurality of layers include a layer mainly composed of Bi and a layer mainly composed of Ni.

この発明のさらに他の局面に従う半導体内部接続部材群は、前記半導体内部接続部材を複数取得可能である。前記半導体内部接続部材群は、複数の前記半導体内部接続部材と、前記複数の半導体内部接続部材に共通して接続されるフレーム部とを含む。   The semiconductor internal connection member group according to still another aspect of the present invention can acquire a plurality of the semiconductor internal connection members. The semiconductor internal connection member group includes a plurality of semiconductor internal connection members and a frame portion connected in common to the plurality of semiconductor internal connection members.

半導体内部接続部材群から複数の半導体内部接続部材を順次切り離すことにより、内部接続を行う半導体装置に対し、半導体内部接続部材を連続的に供給することが可能となり、半導体装置の生産性が向上する。   By sequentially separating a plurality of semiconductor internal connection members from the semiconductor internal connection member group, it becomes possible to continuously supply the semiconductor internal connection members to the semiconductor device that performs internal connection, thereby improving the productivity of the semiconductor device. .

本発明により、融点が２６０℃以上の鉛フリー半田による容易な半田接続を実現することができる。   According to the present invention, it is possible to realize easy solder connection using lead-free solder having a melting point of 260 ° C. or higher.

第１の実施の形態における半導体装置の構成を示す図である。It is a figure which shows the structure of the semiconductor device in 1st Embodiment. 第１の実施の形態における半導体チップを説明するための図である。It is a figure for demonstrating the semiconductor chip in 1st Embodiment. 第１の実施の形態における一例としてのリードフレームを示す図である。It is a figure which shows the lead frame as an example in 1st Embodiment. 第１の実施の形態における、半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device in 1st Embodiment. 第１の実施の形態における、半導体装置の製造方法の一例を示すフローチャートである。3 is a flowchart illustrating an example of a method for manufacturing a semiconductor device in the first embodiment. 第２の実施の形態で使用される、半導体チップを示す図である。It is a figure which shows the semiconductor chip used by 2nd Embodiment. 第２の実施の形態における一例としてのリードフレームを示す図である。It is a figure which shows the lead frame as an example in 2nd Embodiment. 第２の実施の形態における、半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device in 2nd Embodiment. 第２の実施の形態における、半導体装置の製造方法の一例を示すフローチャートである。9 is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to a second embodiment. 第３の実施の形態で使用される、内部接続部材７０ｂを示す図である。It is a figure which shows the internal connection member 70b used by 3rd Embodiment. 第３の実施の形態における、半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device in 3rd Embodiment. 第３の実施の形態における、半導体装置の製造方法の一例を示すフローチャートである。12 is a flowchart illustrating an example of a method of manufacturing a semiconductor device according to a third embodiment. 内部接続部材の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of an internal connection member. 一例としての内部接続部材を示す図である。It is a figure which shows the internal connection member as an example. 一例としての内部接続部材を示す図である。It is a figure which shows the internal connection member as an example.

以下、図面を参照しつつ、本発明の実施の形態について説明する。以下の説明では、同一の部品には同一の符号を付してある。それらの名称および機能も同じである。したがって、それらについての詳細な説明は繰り返さない。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

なお、以下に説明する構成要素の材料は一例であり、当該構成要素には、当該材料と同様な性質の他の材料が使用されてもよい。   In addition, the material of the component demonstrated below is an example, The other material of the property similar to the said material may be used for the said component.

＜第１の実施の形態＞
以下、第１の実施の形態における半導体装置の製造方法を、図を参照しながら説明する。 <First Embodiment>
The semiconductor device manufacturing method according to the first embodiment will be described below with reference to the drawings.

図１は、第１の実施の形態における半導体装置１００の構成を示す図である。
図１に示されるように、半導体装置１００は、半導体チップ１０を含む。半導体チップ１０は、封止樹脂１１０により封止される。半導体チップ１０は、外部端子１２０と電気的に接続される。 FIG. 1 is a diagram illustrating a configuration of the semiconductor device 100 according to the first embodiment.
As shown in FIG. 1, the semiconductor device 100 includes a semiconductor chip 10. The semiconductor chip 10 is sealed with a sealing resin 110. The semiconductor chip 10 is electrically connected to the external terminal 120.

図２は、第１の実施の形態における半導体チップ１０を説明するための図である。
図２（ａ）は、半導体チップ１０の斜視図である。 FIG. 2 is a diagram for explaining the semiconductor chip 10 according to the first embodiment.
FIG. 2A is a perspective view of the semiconductor chip 10.

半導体チップ１０には、電極２０および電極パッド２１が形成される。電極２０の表面には、半田皮膜３０が形成される。   An electrode 20 and an electrode pad 21 are formed on the semiconductor chip 10. A solder film 30 is formed on the surface of the electrode 20.

電極２０は、Ｔｉ（チタン）−Ｃｕ薄膜と、Ｃｕ（銅）膜とを含む。Ｃｕ膜の厚みは、一例として、３μｍである。   The electrode 20 includes a Ti (titanium) -Cu thin film and a Cu (copper) film. The thickness of the Cu film is 3 μm as an example.

電極２０の形成方法について説明する。まず、スパッタ法により、半導体チップ１０上にＴｉ−Ｃｕ薄膜が成膜される。そして、スパッタ法により、Ｔｉ−Ｃｕ薄膜上にＣｕ膜がめっきとして成膜される。これにより、電極２０が形成される。   A method for forming the electrode 20 will be described. First, a Ti—Cu thin film is formed on the semiconductor chip 10 by sputtering. Then, a Cu film is formed as a plating on the Ti—Cu thin film by sputtering. Thereby, the electrode 20 is formed.

半田皮膜３０は、Ｂｉ（ビスマス）めっきを主組成とする。Ｂｉめっきの表面には、Ａｇめっきが形成される。Ｂｉめっきの厚みは、一例として、２０μｍである。Ａｇめっきの厚みは、一例として、０．５μｍである。半田皮膜３０の融点は、２６０℃以上である。   The solder film 30 is mainly composed of Bi (bismuth) plating. Ag plating is formed on the surface of the Bi plating. The thickness of Bi plating is 20 micrometers as an example. For example, the thickness of the Ag plating is 0.5 μm. The melting point of the solder film 30 is 260 ° C. or higher.

半田皮膜３０の形成方法について説明する。まず、電極２０上に、Ｂｉめっきが成膜される。そして、Ｂｉめっき上にＡｇめっきが形成される。Ｂｉめっき上にＡｇめっきが形成することにより、Ｂｉめっき形成後のＢｉの表面酸化を防止することができる。また、Ｂｉめっき上にＡｇめっきが形成することにより、半田接続時に、Ｂｉめっきを容易に溶解することが可能となるとともに、被接続物への半田の濡れを良好にすることができる。   A method for forming the solder film 30 will be described. First, Bi plating is formed on the electrode 20. Then, Ag plating is formed on the Bi plating. By forming the Ag plating on the Bi plating, it is possible to prevent the surface oxidation of Bi after the Bi plating is formed. Further, by forming the Ag plating on the Bi plating, it is possible to easily dissolve the Bi plating at the time of solder connection, and to improve the wettability of the solder to the connected object.

電極パッド２１は、半導体チップ１０において、電極２０が形成される面と反対側の面に形成される。   The electrode pad 21 is formed on the surface of the semiconductor chip 10 opposite to the surface on which the electrode 20 is formed.

電極パッド２１は、Ｃｕ電極の表面にＡｇ薄膜が成膜されたものである。
電極パッド２１の形成方法について説明する。まず、半導体チップ１０の表面に、Ｃｕ電極が成膜される。そして、Ｃｕ電極の表面にＡｇ薄膜が成膜される。これにより、電極パッド２１が形成される。Ｃｕ電極の表面にＡｇ薄膜が成膜されることにより、Ｃｕ電極の酸化を防ぎ半田の濡れ性を向上させることができる。 The electrode pad 21 is obtained by forming an Ag thin film on the surface of a Cu electrode.
A method for forming the electrode pad 21 will be described. First, a Cu electrode is formed on the surface of the semiconductor chip 10. Then, an Ag thin film is formed on the surface of the Cu electrode. Thereby, the electrode pad 21 is formed. By forming an Ag thin film on the surface of the Cu electrode, it is possible to prevent the Cu electrode from being oxidized and improve the wettability of the solder.

図２（ａ）の半導体チップ１０は、図２（ｂ）のように、上下方向に反転させて、後述するリードフレーム５０に載せられる。この場合、電極２０は、半導体チップ１０に対する裏面電極として機能する。   As shown in FIG. 2B, the semiconductor chip 10 in FIG. 2A is inverted in the vertical direction and placed on a lead frame 50 described later. In this case, the electrode 20 functions as a back electrode for the semiconductor chip 10.

図３は、第１の実施の形態における一例としてのリードフレーム５０を示す図である。
リードフレーム５０を構成する主な材料は、Ｃｕである。なお、リードフレーム５０を構成する主な材料は、Ｃｕ以外の材料であってもよい。 FIG. 3 is a diagram showing a lead frame 50 as an example in the first embodiment.
The main material constituting the lead frame 50 is Cu. The main material constituting the lead frame 50 may be a material other than Cu.

図３に示されるように、リードフレーム５０には、ダイパッド５１およびインナーリード部５２が形成される。ダイパッド５１およびインナーリード部５２は、リードフレーム５０の一部である。   As shown in FIG. 3, a die pad 51 and an inner lead portion 52 are formed on the lead frame 50. The die pad 51 and the inner lead part 52 are part of the lead frame 50.

ダイパッド５１およびインナーリード部５２の各々には、Ａｇめっきが形成される。これにより、Ａｇめっきに覆われる、リードフレーム５０の一部のＣｕの酸化を防ぐことができるとともに、半田の濡れ性を向上させることができる。   Ag plating is formed on each of the die pad 51 and the inner lead portion 52. As a result, it is possible to prevent the oxidation of a part of the lead frame 50 covered with the Ag plating and improve the wettability of the solder.

（半導体装置の製造方法）
次に、半導体装置１００の製造方法について説明する。 (Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 100 will be described.

図４は、第１の実施の形態における、半導体装置１００の製造方法を説明するための図である。   FIG. 4 is a diagram for explaining a method of manufacturing the semiconductor device 100 according to the first embodiment.

図５は、第１の実施の形態における、半導体装置１００の製造方法の一例を示すフローチャートである。   FIG. 5 is a flowchart showing an example of a method for manufacturing the semiconductor device 100 according to the first embodiment.

なお、以下で説明する各工程は周知のプロセス技術を用いて実施できるため、プロセス条件などの詳細な説明は適宜省略する。また、以下で示す材料およびプロセスは１つの典型例であって、本発明の半導体装置およびその製造方法を限定するものではない。適性が知られている他の材料およびプロセスを代用した場合も本発明に含まれる。これらのことは、後述する第２および第３の実施の形態における製造方法についても同様である。   In addition, since each process demonstrated below can be implemented using a well-known process technique, detailed description, such as process conditions, is abbreviate | omitted suitably. The materials and processes described below are merely typical examples, and do not limit the semiconductor device and the manufacturing method thereof of the present invention. Substitutions of other materials and processes of known suitability are also included in the present invention. The same applies to the manufacturing methods in the second and third embodiments described later.

まず、加熱工程が行われる（Ｓ１１０）。加熱工程では、図４（ａ）に示されるリードフレーム５０が、還元雰囲気内で加熱される。ここで、還元雰囲気とは、一例として、水素等が満たされた環境である。   First, a heating process is performed (S110). In the heating process, the lead frame 50 shown in FIG. 4A is heated in a reducing atmosphere. Here, the reducing atmosphere is an environment filled with hydrogen or the like as an example.

次に、半導体チップ配置工程が行われる（Ｓ１２０）。半導体チップ配置工程では、図４（ａ），図４（ｂ）に示されるように、半導体チップ１０に形成される半田皮膜３０と、ダイパッド５１とが接するように、半導体チップ１０が配置される。   Next, a semiconductor chip placement step is performed (S120). In the semiconductor chip arranging step, as shown in FIGS. 4A and 4B, the semiconductor chip 10 is arranged so that the solder film 30 formed on the semiconductor chip 10 and the die pad 51 are in contact with each other. .

これにより、加熱されたリードフレーム５０の一部であるダイパッド５１から伝わる熱により、半田皮膜３０が溶融する。これにより、ダイパッド５１と、半導体チップ１０とが電気的に接続される。すなわち、ダイパッド５１の上部に半導体チップ１０が固定される。   As a result, the solder film 30 is melted by the heat transmitted from the die pad 51 which is a part of the heated lead frame 50. Thereby, the die pad 51 and the semiconductor chip 10 are electrically connected. That is, the semiconductor chip 10 is fixed on the die pad 51.

次に、内部接続工程が行われる（Ｓ１３０）。内部接続工程では、半導体内部接続部材が使用される。半導体内部接続部材は、半田接続に使用される。以下においては、半導体内部接続部材を、単に、内部接続部材ともいう。内部接続工程では、内部接続部材７０が使用される。   Next, an internal connection process is performed (S130). In the internal connection process, a semiconductor internal connection member is used. The semiconductor internal connection member is used for solder connection. Hereinafter, the semiconductor internal connection member is also simply referred to as an internal connection member. In the internal connection process, the internal connection member 70 is used.

ここで、内部接続部材７０について説明する。内部接続部材７０は、図４（ｂ）に示される所定形状の金属片７１と、半田皮膜７２ａ，７２ｂとを含む。   Here, the internal connection member 70 will be described. The internal connection member 70 includes a metal piece 71 having a predetermined shape shown in FIG. 4B and solder films 72a and 72b.

金属片７１の表面の一部には、半田皮膜７２ａ，７２ｂが形成される。金属片７１は、Ｃｕを主組成とする。半田皮膜７２ａ，７２ｂの各々の融点は、２６０℃以上である。半田皮膜７２ａ，７２ｂの各々は、鉛が含有されていない鉛フリーの半田皮膜である。   Solder films 72 a and 72 b are formed on part of the surface of the metal piece 71. The metal piece 71 has Cu as the main composition. The melting point of each of the solder films 72a and 72b is 260 ° C. or higher. Each of the solder films 72a and 72b is a lead-free solder film that does not contain lead.

次に、金属片７１の生成方法について説明する。
まず、板状の金属片の表面粗さＲａが０．３μｍ以上になるように、当該板状の金属片の表面が粗化される。 Next, a method for generating the metal piece 71 will be described.
First, the surface of the plate-like metal piece is roughened so that the surface roughness Ra of the plate-like metal piece is 0.3 μm or more.

そして、酸洗浄により、当該板状の金属片の酸化膜が除去される。そして、電極パッド２１と、インナーリード部５２との二点間を接続するように、当該板状の金属片に曲げ加工等が施される。これにより、金属片７１が生成される。この場合、金属片７１の表面粗さＲａは、０．３μｍ以上である。   And the oxide film of the said plate-shaped metal piece is removed by acid cleaning. Then, the plate-shaped metal piece is subjected to bending processing or the like so as to connect the two points between the electrode pad 21 and the inner lead portion 52. Thereby, the metal piece 71 is produced | generated. In this case, the surface roughness Ra of the metal piece 71 is 0.3 μm or more.

すなわち、金属片７１の形状は、図４（ｃ）に示されるように、半導体チップ１０の電極としての電極パッド２１と、リードフレーム５０のインナーリード部５２とを跨ぐ形状である。つまり、金属片７１の形状は、半導体チップ１０の電極としての電極パッド２１と、リードフレーム５０のインナーリード部５２とを繋ぐアーチ形状である。すなわち、金属片７１の形状は、半田接続の対象となる少なくとも２箇所を繋ぐ形状である。   That is, the shape of the metal piece 71 is a shape that straddles the electrode pad 21 as the electrode of the semiconductor chip 10 and the inner lead portion 52 of the lead frame 50 as shown in FIG. That is, the shape of the metal piece 71 is an arch shape that connects the electrode pad 21 as an electrode of the semiconductor chip 10 and the inner lead portion 52 of the lead frame 50. That is, the shape of the metal piece 71 is a shape that connects at least two places to be soldered.

金属片７１の表面の一部としての第１領域および第２領域には、それぞれ、半田皮膜７２ａ，７２ｂが形成される。電極（電極パッド２１）およびインナーリード部５２の上方に金属片７１を配置した状態において、金属片７１の第１領域および第２領域は、それぞれ、電極（電極パッド２１）およびインナーリード部５２に対向する。   Solder films 72a and 72b are formed in the first region and the second region as a part of the surface of the metal piece 71, respectively. In a state where the metal piece 71 is disposed above the electrode (electrode pad 21) and the inner lead portion 52, the first region and the second region of the metal piece 71 are respectively connected to the electrode (electrode pad 21) and the inner lead portion 52. opposite.

すなわち、電極（電極パッド２１）およびインナーリード部５２の上方に金属片７１を配置した状態において、半田皮膜が形成された金属片７１の表面の一部は、金属片７１のうち、電極（電極パッド２１）およびインナーリード部５２にそれぞれ対向する第１領域および第２領域である。   That is, in a state where the metal piece 71 is disposed above the electrode (electrode pad 21) and the inner lead portion 52, a part of the surface of the metal piece 71 on which the solder film is formed is the electrode (electrode) of the metal piece 71. A first area and a second area facing the pad 21) and the inner lead portion 52, respectively.

次に、半田皮膜７２ａ，７２ｂの形成方法について説明する。なお、半田皮膜７２ａ，７２ｂの各々は、Ｂｉめっきを主組成とする。すなわち、金属片７１に形成される半田皮膜７２ａ，７２ｂの各々は、Ｂｉを主組成とする。Ｂｉめっきの表面には、Ａｇめっきが形成される。すなわち、半田皮膜７２ａ，７２ｂの各々の表面には、Ａｇが形成される。   Next, a method for forming the solder films 72a and 72b will be described. Each of the solder films 72a and 72b has Bi plating as a main composition. That is, each of the solder films 72a and 72b formed on the metal piece 71 has Bi as the main composition. Ag plating is formed on the surface of the Bi plating. That is, Ag is formed on each surface of the solder coatings 72a and 72b.

当該Ｂｉめっきの厚みは、一例として、２０μｍである。当該Ａｇめっきの厚みは、一例として、０．５μｍである。   As an example, the thickness of the Bi plating is 20 μm. For example, the thickness of the Ag plating is 0.5 μm.

まず、金属片７１の第１領域および第２領域の各々に、Ｂｉめっきが成膜される。これにより、第１領域および第２領域に、それぞれ、半田皮膜７２ａ，７２ｂが成膜される。なお、前述したように、金属片７１の表面の酸化膜は除去されている。そのため、金属片７１の表面には、Ｂｉを主組成とする半田皮膜７２ａ，７２ｂが直接形成される。   First, Bi plating is formed on each of the first region and the second region of the metal piece 71. Thereby, the solder films 72a and 72b are formed in the first region and the second region, respectively. As described above, the oxide film on the surface of the metal piece 71 is removed. Therefore, solder films 72 a and 72 b mainly composed of Bi are directly formed on the surface of the metal piece 71.

そして、Ｂｉめっきの表面にＡｇめっきが成膜される。
前述の内部接続工程では、半田皮膜７２ａ，７２ｂが、電極パッド２１およびインナーリード部５２に接するように内部接続部材７０が配置される。 And Ag plating is formed into a film on the surface of Bi plating.
In the internal connection process described above, the internal connection member 70 is disposed so that the solder coatings 72 a and 72 b are in contact with the electrode pad 21 and the inner lead portion 52.

すなわち、内部接続工程は、第１領域に形成された半田皮膜７２ａおよび第２領域に形成された半田皮膜７２ｂを、それぞれ、電極（電極パッド２１）およびインナーリード部５２に接するように内部接続部材７０を配置する工程である。つまり、内部接続工程は、金属片７１に形成される半田皮膜７２ａと、半導体チップ１０の電極（電極パッド２１）とが接するように内部接続部材７０を配置する工程である。   That is, in the internal connection step, the internal connection member is arranged so that the solder film 72a formed in the first region and the solder film 72b formed in the second region are in contact with the electrode (electrode pad 21) and the inner lead portion 52, respectively. 70 is a step of arranging 70. That is, the internal connection process is a process of arranging the internal connection member 70 so that the solder film 72a formed on the metal piece 71 and the electrode (electrode pad 21) of the semiconductor chip 10 are in contact with each other.

次に、溶融工程が行われる（Ｓ１４０）。溶融工程では、図４（ｂ），図４（ｃ）に示されるように、加熱されたリードフレーム５０から内部接続部材７０に対し伝わる熱により、半田皮膜７２ａ，７２ｂが溶融する。   Next, a melting step is performed (S140). In the melting step, as shown in FIGS. 4B and 4C, the solder films 72 a and 72 b are melted by the heat transferred from the heated lead frame 50 to the internal connection member 70.

具体的には、加熱されたリードフレーム５０から内部接続部材７０に対し伝わる熱により、半田皮膜７２ａ，７２ｂの各々に主組成であるＢｉめっきが溶融するとともに、当該ＢｉにＡｇが取り込まれ一体となったＢｉ−Ａｇ組成の合成半田が生成され、当該Ｂｉ−Ａｇ組成の半田が溶融する。   Specifically, by the heat transferred from the heated lead frame 50 to the internal connection member 70, the Bi plating as the main composition is melted in each of the solder coatings 72a and 72b, and Ag is taken into the Bi and integrated. As a result, a synthetic solder having the Bi-Ag composition is generated, and the solder having the Bi-Ag composition is melted.

したがって、半田皮膜７２ａ，７２ｂが溶融する直前まで、Ｂｉ半田表面の酸化を防ぐことができる。また、Ｂｉ−Ａｇ組成の半田が溶融することにより、溶融する半田と、電極パッド２１、インナーリード部５２などの被接合面との半田接合を阻害することなく容易に半田接合ができる。   Therefore, oxidation of the Bi solder surface can be prevented until immediately before the solder coatings 72a and 72b are melted. Further, when the solder having the Bi—Ag composition is melted, the solder can be easily joined without hindering the solder joining between the melted solder and the surfaces to be joined such as the electrode pad 21 and the inner lead portion 52.

これにより、内部接続部材７０が、半導体チップ１０に形成される電極パッド２１と、リードフレーム５０に形成されるインナーリード部５２とに半田接続される。すなわち、内部接続部材７０が、半導体チップ１０およびリードフレーム５０に接続される。したがって、半導体チップ１０と、リードフレーム５０とが、内部接続部材７０を介して電気的に接続される。   As a result, the internal connection member 70 is solder-connected to the electrode pads 21 formed on the semiconductor chip 10 and the inner lead portions 52 formed on the lead frame 50. That is, the internal connection member 70 is connected to the semiconductor chip 10 and the lead frame 50. Therefore, the semiconductor chip 10 and the lead frame 50 are electrically connected via the internal connection member 70.

すなわち、溶融工程は、第１領域に形成された半田皮膜７２ａおよび第２領域に形成された半田皮膜７２ｂを加熱溶融することにより、内部接続部材７０を半導体チップ１０およびリードフレーム５０に半田接続する工程である。つまり、溶融工程は、半田皮膜７２ａを加熱溶融することにより、内部接続部材７０と半導体チップ１０とを半田接続する工程でもある。   That is, in the melting step, the internal connection member 70 is solder-connected to the semiconductor chip 10 and the lead frame 50 by heating and melting the solder film 72a formed in the first region and the solder film 72b formed in the second region. It is a process. That is, the melting step is also a step of solder-connecting the internal connection member 70 and the semiconductor chip 10 by heating and melting the solder film 72a.

次に、図４（ｃ）のリードフレーム５０が冷却された後、封止工程が行われる（Ｓ１５０）。封止工程では、図４（ｃ）の半導体チップ１０および内部接続部材７０等を、図１の封止樹脂１１０で封止する。   Next, after the lead frame 50 of FIG. 4C is cooled, a sealing process is performed (S150). In the sealing step, the semiconductor chip 10 and the internal connection member 70 shown in FIG. 4C are sealed with the sealing resin 110 shown in FIG.

次に、仕上げ工程が行われる（Ｓ１６０）。仕上げ工程では、封止樹脂１１０により封止された半導体チップ１０が、リードフレーム５０の一部から切り離される。この場合、切り離された半導体チップ１０は、インナーリード部５２が形成されたリードフレーム５０の一部と接続される。そして、切り離された半導体チップ１０に接続されるリードフレーム５０の一部を、図１の外部端子１２０に加工する。   Next, a finishing process is performed (S160). In the finishing process, the semiconductor chip 10 sealed with the sealing resin 110 is separated from a part of the lead frame 50. In this case, the separated semiconductor chip 10 is connected to a part of the lead frame 50 in which the inner lead portion 52 is formed. Then, a part of the lead frame 50 connected to the separated semiconductor chip 10 is processed into the external terminal 120 in FIG.

以上の工程により、図１の半導体装置１００が製造される。
すなわち、半導体装置１００の製造には、リードフレーム５０が使用される。 Through the above steps, the semiconductor device 100 of FIG. 1 is manufactured.
That is, the lead frame 50 is used for manufacturing the semiconductor device 100.

以上説明したように、本実施の形態では、融点が２６０℃以上の鉛フリーの半田皮膜が形成された金属片７１を、内部接続部材７０として使用し、当該半田皮膜を加熱溶融することにより、内部接続部材７０を半導体チップ１０およびリードフレーム５０に容易に半田接続することができる。   As described above, in the present embodiment, the metal piece 71 on which the lead-free solder film having a melting point of 260 ° C. or higher is used as the internal connection member 70, and the solder film is heated and melted. The internal connection member 70 can be easily soldered to the semiconductor chip 10 and the lead frame 50.

すなわち、融点が２６０℃以上の鉛フリー半田による容易な半田接続を実現することができる。その結果、高い接続品質、信頼性を有する半田接続を実現することができる。   That is, it is possible to realize easy solder connection using lead-free solder having a melting point of 260 ° C. or higher. As a result, solder connection having high connection quality and reliability can be realized.

また、鉛フリーの半田皮膜が形成された金属片７１を、内部接続部材７０として使用することにより、糸半田や半田箔などの形態での供給が困難であった融点が２６０℃以上の鉛フリー半田の供給を容易に実現できる。   Further, by using the metal piece 71 on which the lead-free solder film is formed as the internal connection member 70, a lead-free melting point of 260 ° C. or higher, which was difficult to be supplied in the form of thread solder or solder foil, etc. Solder can be easily supplied.

また、金属片７１の表面にめっきや蒸着・スパッタなどの手法で半田皮膜を形成する工程の直前に、ウェットエッチングやプラズマ洗浄などの手法で金属片７１の表面の酸化膜を除去してから半田皮膜の形成が可能である。   Further, immediately before the step of forming the solder film on the surface of the metal piece 71 by plating, vapor deposition, sputtering, or the like, the solder film is removed after the oxide film on the surface of the metal piece 71 is removed by a technique such as wet etching or plasma cleaning. A film can be formed.

そのため、金属片７１と半田皮膜（７２ａ，７２ｂ）との界面においては酸化皮膜なく形成でき、従来のように半田接続の際に被半田接続面の酸化膜除去や半田材料の酸化膜除去を強固に行わなくても容易に半田接続ができる。   Therefore, it can be formed without an oxide film at the interface between the metal piece 71 and the solder film (72a, 72b), and the removal of the oxide film on the solder connection surface and the removal of the oxide film of the solder material are firmly performed at the time of solder connection as in the prior art. Even if it does not carry out to soldering, a solder connection can be performed easily.

特に、従来の粒状半田や半田ペーストにおいては、比表面積が大きいために半田の酸化皮膜除去が大きな課題であったが、本発明の半田皮膜が外気に触れる面積は半田皮膜の片面だけである。   In particular, conventional granular solders and solder pastes have a large specific surface area, so that the removal of the oxide film of the solder has been a big problem. However, the area where the solder film of the present invention comes into contact with the outside air is only on one side of the solder film.

そのため、糸半田、半田箔、粒状半田、半田ペーストなどの従来の形態に比べて、最も比表面積が小さく、酸化膜の残留が少なく良好な半田接続を実現できる。また、容易に加熱還元ガス中で還元し表面酸化膜を除去できることから、半田ペーストの様なフラックスが不要で、接合界面のボイドも低減でき腐食性残渣の残留もなく、高い信頼性の半田接続を実現できる。すなわち、酸化皮膜や残渣によるボイドや腐食などによる劣化を抑えた半田接続を実現できる。   Therefore, compared with conventional forms such as thread solder, solder foil, granular solder, solder paste, etc., the specific surface area is the smallest and there is little residual oxide film, and good solder connection can be realized. In addition, since the surface oxide film can be easily removed by reduction in heated reducing gas, no flux like solder paste is required, voids at the bonding interface can be reduced, no corrosive residue remains, and highly reliable solder connection Can be realized. That is, it is possible to realize a solder connection that suppresses deterioration due to voids or corrosion caused by oxide films or residues.

また、本実施の形態によれば、より大電流を流せる半導体装置を実現でき、特にパワー半導体に好適である。   Further, according to the present embodiment, a semiconductor device capable of flowing a larger current can be realized, and is particularly suitable for a power semiconductor.

半導体パッケージの封止樹脂との密着性を向上させるため、リードフレーム等の部材の表面粗さを大きくする手法がある。一方で部材の表面粗さを増すと部材の表面積が増加するために表面酸化されやすくなる。その結果、酸化膜が半田接合やワイヤーボンディングなどを阻害するというトレードオフがある。   There is a technique for increasing the surface roughness of a member such as a lead frame in order to improve the adhesion of the semiconductor package to the sealing resin. On the other hand, when the surface roughness of the member is increased, the surface area of the member is increased, so that the surface is easily oxidized. As a result, there is a trade-off that the oxide film hinders solder bonding, wire bonding, and the like.

本実施の形態では、金属片の表面に、予め半田皮膜を形成しておく。そのため、半田接合時の酸化皮膜除去を気にする必要がない。また、さらに、金属片の表面を粗くすることにより、半田皮膜との接触面積やアンカー効果が増し、より良好な金属片と半田皮膜との接合をより良好に行うことができる。したがって、封止樹脂との密着向上と良好な半田接合を両立でき、高い信頼性を得ることができる。   In the present embodiment, a solder film is formed in advance on the surface of the metal piece. Therefore, there is no need to worry about the removal of the oxide film during solder bonding. Furthermore, by roughening the surface of the metal piece, the contact area with the solder film and the anchor effect are increased, and a better metal piece and the solder film can be joined better. Therefore, it is possible to achieve both improved adhesion to the sealing resin and good solder bonding, and high reliability can be obtained.

なお、本実施の形態では、半田皮膜の表面にＡｇめっきを施しているが、半田接合の際に十分な還元雰囲気を準備できる場合は、Ａｇめっきが無くても同様に本発明の効果が得られる。   In this embodiment, Ag plating is applied to the surface of the solder film. However, if a sufficient reducing atmosphere can be prepared at the time of soldering, the effects of the present invention can be obtained even without Ag plating. It is done.

＜第２の実施の形態＞
以下、第２の実施の形態における半導体装置の製造方法を、図を参照しながら説明する。本実施の形態で製造する半導体装置は、図１の半導体装置１００である。 <Second Embodiment>
Hereinafter, a method of manufacturing a semiconductor device according to the second embodiment will be described with reference to the drawings. The semiconductor device manufactured in this embodiment is the semiconductor device 100 of FIG.

図６は、第２の実施の形態で使用される、半導体チップ１０を示す図である。
半導体チップ１０の一方の面には、スパッタ法により、Ｔｉ−Ｃｕ−Ａｇ薄膜を成膜することにより電極２０ａが形成される。すなわち、電極２０ａは、一例として、Ｔｉ−Ｃｕ−Ａｇ薄膜により構成される。電極２０ａは、半導体チップ１０に対する裏面電極として機能する。 FIG. 6 is a diagram showing the semiconductor chip 10 used in the second embodiment.
An electrode 20a is formed on one surface of the semiconductor chip 10 by forming a Ti—Cu—Ag thin film by sputtering. That is, the electrode 20a is constituted by a Ti—Cu—Ag thin film as an example. The electrode 20 a functions as a back electrode for the semiconductor chip 10.

また、半導体チップ１０の他方の面には、電極パッド２１ａが形成される。電極パッド２１ａの主な材料は、Ａｌ（アルミニウム）である。   Further, an electrode pad 21 a is formed on the other surface of the semiconductor chip 10. The main material of the electrode pad 21a is Al (aluminum).

図７は、第２の実施の形態における一例としてのリードフレーム５０ａを示す図である。   FIG. 7 is a diagram showing a lead frame 50a as an example in the second embodiment.

本実施の形態では、リードフレーム５０ａの少なくとも一部または全体が、内部接続部材として使用される。すなわち、リードフレーム５０ａの少なくとも一部または全体が、内部接続部材の機能を兼ねる。   In the present embodiment, at least a part or the whole of the lead frame 50a is used as an internal connection member. That is, at least a part or the whole of the lead frame 50a also functions as an internal connection member.

リードフレーム５０ａを構成する主な材料は、Ｃｕである。なお、リードフレーム５０ａを構成する主な材料は、Ｃｕ以外の材料であってもよい。   The main material constituting the lead frame 50a is Cu. The main material constituting the lead frame 50a may be a material other than Cu.

図７に示されるように、リードフレーム５０ａには、ダイパッド５１ａおよびインナーリード部５２ａが形成される。ダイパッド５１ａおよびインナーリード部５２ａは、リードフレーム５０ａの一部である。リードフレーム５０ａは、金属片である。すなわち、ダイパッド５１ａは、金属片である。   As shown in FIG. 7, a die pad 51a and an inner lead portion 52a are formed on the lead frame 50a. The die pad 51a and the inner lead part 52a are part of the lead frame 50a. The lead frame 50a is a metal piece. That is, the die pad 51a is a metal piece.

リードフレーム５０ａの一部としてのダイパッド５１ａの表面には、半田皮膜７２ｃが形成される。すなわち、リードフレーム５０ａの少なくとも一部には、半田皮膜７２ｃが形成される。   A solder film 72c is formed on the surface of the die pad 51a as a part of the lead frame 50a. That is, the solder film 72c is formed on at least a part of the lead frame 50a.

半田皮膜７２ｃの融点は、２６０℃以上である。半田皮膜７２ｃは、鉛が含有されていない鉛フリーの半田皮膜である。半田皮膜７２ｃは、Ｂｉめっきを主組成とする。Ｂｉめっきの表面には、Ａｇめっきが形成される。すなわち、金属片としてのダイパッド５１ａに形成される半田皮膜７２ｃは、Ｂｉを主組成とする。当該Ｂｉめっきの厚みは、一例として、２０μｍである。また、当該Ａｇめっきの厚みは、一例として、０．５μｍである。   The melting point of the solder coating 72c is 260 ° C. or higher. The solder film 72c is a lead-free solder film that does not contain lead. The solder coating 72c is mainly composed of Bi plating. Ag plating is formed on the surface of the Bi plating. That is, the solder film 72c formed on the die pad 51a as a metal piece has Bi as the main composition. As an example, the thickness of the Bi plating is 20 μm. Moreover, the thickness of the Ag plating is 0.5 μm as an example.

半田皮膜７２ｃの形成方法について説明する。まず、ダイパッド５１ａの表面にＢｉめっきが成膜される。すなわち、金属片としてのダイパッド５１ａの表面には、Ｂｉを主組成とする半田皮膜７２ｃが直接形成される。そして、Ｂｉめっきの表面にＡｇめっきが成膜される。これにより、ダイパッド５１ａの表面に半田皮膜７２ｃが形成される。   A method for forming the solder film 72c will be described. First, Bi plating is formed on the surface of the die pad 51a. That is, the solder film 72c having Bi as the main composition is directly formed on the surface of the die pad 51a as a metal piece. And Ag plating is formed into a film on the surface of Bi plating. As a result, a solder film 72c is formed on the surface of the die pad 51a.

インナーリード部５２ａには、Ｎｉめっきが形成される。
内部接続部材７０ａは、金属片してのダイパッド５１ａと、半田皮膜７２ｃとを含む。ダイパッド５１ａの表面の少なくとも一部には、半田皮膜７２ｃが形成される。すなわち、半田皮膜７２ｃが形成された、リードフレーム５０ａの少なくとも一部（ダイパッド５１ａ）は、内部接続部材７０ａである。 Ni plating is formed on the inner lead portion 52a.
The internal connection member 70a includes a die pad 51a as a metal piece and a solder film 72c. A solder film 72c is formed on at least a part of the surface of the die pad 51a. That is, at least a part (die pad 51a) of the lead frame 50a on which the solder film 72c is formed is the internal connection member 70a.

（半導体装置の製造方法）
次に、半導体装置１００の製造方法について説明する。 (Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 100 will be described.

図８は、第２の実施の形態における、半導体装置１００の製造方法を説明するための図である。   FIG. 8 is a diagram for explaining a method of manufacturing the semiconductor device 100 according to the second embodiment.

図９は、第２の実施の形態における、半導体装置１００の製造方法の一例を示すフローチャートである。図９において、図５のステップ番号と同じステップ番号の処理は、第１の実施の形態で説明した処理と同様な処理が行われるので詳細な説明は繰り返さない。   FIG. 9 is a flowchart illustrating an example of a manufacturing method of the semiconductor device 100 according to the second embodiment. In FIG. 9, the process with the same step number as the step number of FIG. 5 is performed in the same way as the process described in the first embodiment, and therefore detailed description will not be repeated.

まず、第１の実施の形態と同様に、加熱工程が行われる（Ｓ１１０）。加熱工程では、図８（ａ）に示されるリードフレーム５０ａが、還元雰囲気内で加熱される。   First, as in the first embodiment, a heating step is performed (S110). In the heating step, the lead frame 50a shown in FIG. 8A is heated in a reducing atmosphere.

次に、半導体チップ配置工程Ａが行われる（Ｓ１２０Ａ）。半導体チップ配置工程Ａでは、図８（ａ），図８（ｂ）に示されるように、金属片してのダイパッド５１ａに形成される半田皮膜７２ｃと、半導体チップ１０に形成される電極２０ａとが接するように、半導体チップ１０が配置される。すなわち、半導体チップ１０は、ダイパッド５１ａの上部に配置される。   Next, a semiconductor chip placement step A is performed (S120A). In the semiconductor chip placement step A, as shown in FIGS. 8A and 8B, a solder film 72c formed on the die pad 51a as a metal piece, and an electrode 20a formed on the semiconductor chip 10 The semiconductor chip 10 is arranged so as to be in contact with each other. That is, the semiconductor chip 10 is disposed on the upper part of the die pad 51a.

次に、溶融工程Ａが行われる（Ｓ１４０Ａ）。溶融工程Ａでは、図８（ｂ）に示されるように、加熱されたリードフレーム５０ａの一部であるダイパッド５１ａから伝わる熱により、半田皮膜７２ｃが溶融する。これにより、ダイパッド５１ａと、半導体チップ１０とが電気的に接続される。すなわち、半田皮膜７２ｃが形成されるダイパッド５１ａと、半導体チップ１０とが半田接続される。これにより、ダイパッド５１ａの上部に半導体チップ１０が固定される。   Next, the melting step A is performed (S140A). In the melting step A, as shown in FIG. 8B, the solder film 72c is melted by heat transmitted from the die pad 51a which is a part of the heated lead frame 50a. Thereby, the die pad 51a and the semiconductor chip 10 are electrically connected. That is, the die pad 51a on which the solder film 72c is formed and the semiconductor chip 10 are soldered. Thereby, the semiconductor chip 10 is fixed to the upper part of the die pad 51a.

すなわち、溶融工程Ａは、内部接続部材７０ａとしてのリードフレーム５０ａの少なくとも一部（ダイパッド５１ａ）と、半導体チップ１０とを半田接続する工程である。つまり、溶融工程Ａは、半田皮膜７２ｃを加熱溶融することにより、内部接続部材７０ａと半導体チップ１０とを半田接続する工程でもある。   That is, the melting step A is a step of solder-connecting at least part of the lead frame 50a (die pad 51a) as the internal connection member 70a and the semiconductor chip 10. That is, the melting step A is also a step of solder-connecting the internal connection member 70a and the semiconductor chip 10 by heating and melting the solder film 72c.

次に、図８（ｂ）のリードフレーム５０ａが冷却された後、図８（ｃ）のように、内部接続工程Ａが行われる（Ｓ１４１Ａ）。内部接続工程Ａでは、半導体チップ１０に形成される電極パッド２１ａと、インナーリード部５２ａとが、アルミワイヤー８０により、ワイヤーボンディングされる。   Next, after the lead frame 50a of FIG. 8B is cooled, the internal connection process A is performed as shown in FIG. 8C (S141A). In the internal connection process A, the electrode pad 21 a formed on the semiconductor chip 10 and the inner lead portion 52 a are wire bonded by the aluminum wire 80.

そして、第１の実施の形態と同様に、封止工程（Ｓ１５０）、仕上げ工程（Ｓ１６０）が行われる。以上の工程により、図１の半導体装置１００が製造される。   And a sealing process (S150) and a finishing process (S160) are performed similarly to 1st Embodiment. Through the above steps, the semiconductor device 100 of FIG. 1 is manufactured.

すなわち、半導体装置１００の製造には、金属片としてのリードフレーム５０ａが使用される。   That is, in manufacturing the semiconductor device 100, the lead frame 50a as a metal piece is used.

以上説明したように、本実施の形態では、リードフレーム５０ａの少なくとも一部または全体が、内部接続部材の機能を兼ねる構成としても、第１の実施の形態と同様な効果が得られる。すなわち、融点が２６０℃以上の鉛フリー半田による容易な半田接続を実現することができる。その結果、高い接続品質、信頼性を有する半田接続を実現することができる。   As described above, in the present embodiment, the same effect as in the first embodiment can be obtained even if at least a part or the whole of the lead frame 50a also functions as an internal connection member. That is, it is possible to realize easy solder connection using lead-free solder having a melting point of 260 ° C. or higher. As a result, solder connection having high connection quality and reliability can be realized.

すなわち、リードフレーム５０ａの少なくとも一部または全体が内部接続部材の機能を兼ね備えることによって、内部の半田接続点数を減らすことができ、信頼性の高い半導体パッケージを実現することができる。   That is, since at least a part or the whole of the lead frame 50a also has the function of an internal connection member, the number of internal solder connection points can be reduced, and a highly reliable semiconductor package can be realized.

＜第３の実施の形態＞
以下、第３の実施の形態における半導体装置の製造方法を、図を参照しながら説明する。本実施の形態で製造する半導体装置は、図１の半導体装置１００である。 <Third Embodiment>
Hereinafter, a method of manufacturing a semiconductor device according to the third embodiment will be described with reference to the drawings. The semiconductor device manufactured in this embodiment is the semiconductor device 100 of FIG.

本実施の形態で使用される半導体チップ１０の表面は、Ｓｉ（シリコン）で覆われているとする。   It is assumed that the surface of the semiconductor chip 10 used in the present embodiment is covered with Si (silicon).

図１０は、第３の実施の形態で使用される、内部接続部材７０ｂを示す図である。
内部接続部材７０ｂは、金属片７１ｂと、半田皮膜７２ｄ，７２ｅとを含む。半田皮膜７２ｄ，７２ｅの各々の融点は、２６０℃以上である。半田皮膜７２ｄ，７２ｅの各々は、鉛が含有されていない鉛フリーの半田皮膜である。 FIG. 10 is a diagram showing the internal connection member 70b used in the third embodiment.
The internal connection member 70b includes a metal piece 71b and solder films 72d and 72e. The melting points of the solder films 72d and 72e are 260 ° C. or higher. Each of the solder films 72d and 72e is a lead-free solder film that does not contain lead.

金属片７１ｂの形状は、平面形状である。金属片７１ｂの主面には半田皮膜７２ｄが直接形成される。金属片７１ｂの主面の反対側の反対面に半田皮膜７２ｅが直接形成される。すなわち、金属片７１ｂの主面に半田皮膜７２ｄが形成され、かつ、該主面の反対側の反対面に半田皮膜７２ｅが形成された金属片７１ｂは、内部接続部材７０ｂである。つまり、金属片７１ｂの表面（主面および反対面）には、Ｂｉを主組成とする半田皮膜が直接形成される。   The shape of the metal piece 71b is a planar shape. A solder film 72d is directly formed on the main surface of the metal piece 71b. A solder film 72e is directly formed on the opposite surface of the metal piece 71b opposite to the main surface. That is, the metal piece 71b in which the solder film 72d is formed on the main surface of the metal piece 71b and the solder film 72e is formed on the opposite surface opposite to the main surface is the internal connection member 70b. That is, a solder film having Bi as the main composition is directly formed on the surface (main surface and opposite surface) of the metal piece 71b.

金属片７１ｂを構成する主な材料は、一例として、ＣｕＷ合金である。当該ＣｕＷ合金の熱膨張率は、Ｃｕ（銅）の熱膨張率と、Ｓｉ（シリコン）の熱膨張率との間の値である。すなわち、金属片７１ｂの熱膨張率は、銅の熱膨張率とシリコンの熱膨張率との間の値である。   The main material which comprises the metal piece 71b is a CuW alloy as an example. The thermal expansion coefficient of the CuW alloy is a value between the thermal expansion coefficient of Cu (copper) and the thermal expansion coefficient of Si (silicon). That is, the thermal expansion coefficient of the metal piece 71b is a value between the thermal expansion coefficient of copper and the thermal expansion coefficient of silicon.

当該ＣｕＷ合金の熱膨張率は、一例として、８ｐｐｍ／Ｋである。半田皮膜７２ｄ，７２ｅの各々の材料および厚みは、半田皮膜７２ａと同様であるので詳細な説明は繰り返さない。すなわち、半田皮膜７２ｄ，７２ｅの各々は、Ｂｉめっきを主組成とする。Ｂｉめっきの表面には、Ａｇめっきが形成される。   As an example, the coefficient of thermal expansion of the CuW alloy is 8 ppm / K. Since the material and thickness of each of solder films 72d and 72e are the same as those of solder film 72a, detailed description will not be repeated. That is, each of the solder films 72d and 72e has Bi plating as a main composition. Ag plating is formed on the surface of the Bi plating.

なお、本実施の形態で使用される半導体チップは、図６の半導体チップ１０である。
また、本実施の形態で使用されるリードフレームは、図３のリードフレーム５０である。本実施の形態で使用されるリードフレーム５０のダイパッド５１およびインナーリード部５２には、それぞれ、ＡｇめっきおよびＮｉめっきが形成される。 Note that the semiconductor chip used in the present embodiment is the semiconductor chip 10 of FIG.
The lead frame used in the present embodiment is the lead frame 50 in FIG. Ag plating and Ni plating are formed on the die pad 51 and the inner lead portion 52 of the lead frame 50 used in the present embodiment, respectively.

（半導体装置の製造方法）
次に、半導体装置１００の製造方法について説明する。 (Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 100 will be described.

図１１は、第３の実施の形態における、半導体装置１００の製造方法を説明するための図である。   FIG. 11 is a diagram for explaining a method of manufacturing the semiconductor device 100 according to the third embodiment.

図１２は、第３の実施の形態における、半導体装置１００の製造方法の一例を示すフローチャートである。図１２において、図５のステップ番号と同じステップ番号の処理は、第１の実施の形態で説明した処理と同様な処理が行われるので詳細な説明は繰り返さない。   FIG. 12 is a flowchart illustrating an example of a manufacturing method of the semiconductor device 100 according to the third embodiment. In FIG. 12, the process with the same step number as the step number of FIG. 5 is performed in the same way as the process described in the first embodiment, and therefore detailed description will not be repeated.

まず、第１の実施の形態と同様に、加熱工程が行われる（Ｓ１１０）。加熱工程では、図１１（ａ）に示されるリードフレーム５０が、還元雰囲気内で加熱される。   First, as in the first embodiment, a heating step is performed (S110). In the heating process, the lead frame 50 shown in FIG. 11A is heated in a reducing atmosphere.

次に、接続部材配置工程が行われる（Ｓ１２０Ｂ）。接続部材配置工程では、半田皮膜７２ｅとダイパッド５１とが接するように、内部接続部材７０ｂが配置される。すなわち、接続部材配置工程は、金属片７１ｂの反対面に形成された半田皮膜７２ｅとダイパッド５１とが接するように、内部接続部材７０ｂを配置する工程である。   Next, a connecting member arrangement step is performed (S120B). In the connecting member arranging step, the internal connecting member 70b is arranged so that the solder film 72e and the die pad 51 are in contact with each other. That is, the connecting member arranging step is a step of arranging the internal connecting member 70b so that the solder film 72e formed on the opposite surface of the metal piece 71b and the die pad 51 are in contact with each other.

次に、溶融工程Ｂが行われる（Ｓ１４０Ｂ）。溶融工程Ｂでは、図１１（ａ），図１１（ｂ）に示されるように、加熱されたリードフレーム５０から内部接続部材７０ｂに対し伝わる熱により、半田皮膜７２ｄ，７２ｅが溶融する。   Next, the melting step B is performed (S140B). In the melting step B, as shown in FIGS. 11A and 11B, the solder films 72d and 72e are melted by the heat transferred from the heated lead frame 50 to the internal connection member 70b.

これにより、ダイパッド５１と、内部接続部材７０ｂとが半田接続される。すなわち、ダイパッド５１と、内部接続部材７０ｂとが電気的に接続される。すなわち、半田皮膜７２ｅが形成される内部接続部材７０ｂと、ダイパッド５１とが半田接続される。これにより、ダイパッド５１の上部に内部接続部材７０ｂが固定される。   Thereby, the die pad 51 and the internal connection member 70b are solder-connected. That is, the die pad 51 and the internal connection member 70b are electrically connected. That is, the internal connection member 70b on which the solder film 72e is formed and the die pad 51 are soldered. Thereby, the internal connection member 70 b is fixed to the upper part of the die pad 51.

すなわち、溶融工程Ｂは、金属片７１ｂの反対面に形成された半田皮膜７２ｅおよび金属片７１ｂの主面に形成された半田皮膜７２ｅを過熱溶融することにより、内部接続部材７０ｂとダイパッド５１とを半田接続する工程である。   That is, in the melting step B, the solder film 72e formed on the opposite surface of the metal piece 71b and the solder film 72e formed on the main surface of the metal piece 71b are overheated to melt the internal connection member 70b and the die pad 51. This is a step of soldering.

次に、内部接続工程Ｂが行われる（Ｓ１４１Ｂ）。内部接続工程Ｂでは、図１１（ｂ）、図１１（ｃ）に示されるように、溶融した半田皮膜７２ｄと、半導体チップ１０の電極２０とが接するように半導体チップ１０が配置される。すなわち、内部接続工程Ｂは、ダイパッド５１に半田接続された内部接続部材７０ｂにおける金属片７１ｂの主面に形成された溶融した半田皮膜７２ｄと、半導体チップ１０の電極２０とが接するように半導体チップ１０を配置する工程である。   Next, the internal connection process B is performed (S141B). In the internal connection process B, as shown in FIGS. 11B and 11C, the semiconductor chip 10 is disposed so that the melted solder film 72d and the electrode 20 of the semiconductor chip 10 are in contact with each other. That is, in the internal connection step B, the semiconductor chip is so formed that the molten solder film 72d formed on the main surface of the metal piece 71b in the internal connection member 70b solder-connected to the die pad 51 and the electrode 20 of the semiconductor chip 10 are in contact with each other. 10 is a step of arranging 10.

これにより、溶融した半田皮膜７２ｄが形成される内部接続部材７０ｂと、半導体チップ１０とが半田接続される。   Thereby, the internal connection member 70b on which the melted solder film 72d is formed and the semiconductor chip 10 are solder-connected.

次に、図１１（ｃ）のリードフレーム５０が冷却された後、図１１（ｃ）のように、接続工程Ｂが行われる（Ｓ１４２Ｂ）。内部接続工程Ｂでは、半導体チップ１０に形成される電極パッド２１と、インナーリード部５２とが、アルミワイヤー８０により、ワイヤーボンディングされる。   Next, after the lead frame 50 of FIG. 11C is cooled, a connection process B is performed as shown in FIG. 11C (S142B). In the internal connection process B, the electrode pad 21 formed on the semiconductor chip 10 and the inner lead portion 52 are wire-bonded by the aluminum wire 80.

そして、第１の実施の形態と同様に、封止工程（Ｓ１５０）、仕上げ工程（Ｓ１６０）が行われる。以上の工程により、図１の半導体装置１００が製造される。   And a sealing process (S150) and a finishing process (S160) are performed similarly to 1st Embodiment. Through the above steps, the semiconductor device 100 of FIG. 1 is manufactured.

すなわち、半導体装置１００の製造には、ダイパッド５１が形成されたリードフレーム５０が使用される。   That is, the lead frame 50 in which the die pad 51 is formed is used for manufacturing the semiconductor device 100.

以上説明したように、本実施の形態では、ダイパッド５１に接続された内部接続部材７０ｂを利用する構成としても、第１の実施の形態と同様な効果が得られる。すなわち、融点が２６０℃以上の鉛フリー半田による容易な半田接続を実現することができる。その結果、高い接続品質、信頼性を有する半田接続を実現することができる。   As described above, in the present embodiment, even when the internal connection member 70b connected to the die pad 51 is used, the same effects as in the first embodiment can be obtained. That is, it is possible to realize easy solder connection using lead-free solder having a melting point of 260 ° C. or higher. As a result, solder connection having high connection quality and reliability can be realized.

また、上記構成によれば、融点２６０℃以上の鉛フリー半田としての半田皮膜７２ｄ，７２ｅを利用した半導体チップ１０の接続（ダイボンド）が行われた半導体装置１００を製造することができる。   Further, according to the above configuration, it is possible to manufacture the semiconductor device 100 in which the semiconductor chip 10 is connected (die-bonded) using the solder films 72d and 72e as lead-free solder having a melting point of 260 ° C. or higher.

さらに、金属片を半導体チップとダイパッド間のヒートスプレッダとして機能させることも可能で、特に発熱密度の高いパワー半導体チップにおいて半導体パッケージの熱抵抗を下げ、有効に放熱を行うことができる。   Furthermore, the metal piece can function as a heat spreader between the semiconductor chip and the die pad, and the heat resistance of the semiconductor package can be lowered particularly in a power semiconductor chip having a high heat generation density, so that heat can be effectively radiated.

なお、従来では、ＣｕへＳｉチップを直接半田でダイボンドした際には熱膨張率差による熱ストレスに起因する半田クラックやチップクラックが発生するという問題があった。   Conventionally, when a Si chip is directly die-bonded to Cu with solder, there is a problem that a solder crack or a chip crack due to a thermal stress due to a difference in thermal expansion coefficient occurs.

しかしながら、本実施の形態では、リードフレーム５０のＣｕと半導体チップ１０の表面のＳｉとの中間の熱膨張率を有するＣｕＷを主な構成材料とする金属片７１ｂを利用した内部接続部材７０ｂを、半田接続に用いる。   However, in the present embodiment, the internal connection member 70b using the metal piece 71b whose main constituent material is CuW having a thermal expansion coefficient intermediate between Cu of the lead frame 50 and Si of the surface of the semiconductor chip 10 is Used for solder connection.

これにより、リードフレーム５０のＣｕの熱膨張率と半導体チップ１０のＳｉの熱膨張率と差（熱膨張率差）による熱ストレス（熱応力）を低減できるとともに、クラック等の不具合を抑制でき、高い信頼性を得ることができる。   Thereby, while being able to reduce the thermal stress (thermal stress) by the difference (thermal expansion coefficient difference) between the thermal expansion coefficient of Cu of the lead frame 50 and the thermal expansion coefficient of Si of the semiconductor chip 10, it is possible to suppress defects such as cracks, High reliability can be obtained.

なお、第１〜第３の実施の形態では、リードフレームから伝わる熱により、内部接続部材７０，７０ａ，７０ｂの各々に形成される半田皮膜を溶融していたが、これに限定されない。例えば、ヒートツール等を使用して、内部接続部材の半田皮膜に対し直接、熱を与えることにより、半田皮膜を加熱溶融するようにしてもよい。   In the first to third embodiments, the heat transmitted from the lead frame melts the solder film formed on each of the internal connection members 70, 70a, and 70b. However, the present invention is not limited to this. For example, the solder film may be heated and melted by applying heat directly to the solder film of the internal connection member using a heat tool or the like.

すなわち、図５の溶融工程（Ｓ１４０）、図９の溶融工程Ａ（Ｓ１４０Ａ）、図１２の溶融工程Ｂ（Ｓ１４０Ｂ）の各々では、ヒートツール等を使用して、内部接続部材の半田皮膜に対し直接、熱を与えることにより、半田皮膜を加熱溶融するようにしてもよい。   That is, in each of the melting step (S140) in FIG. 5, the melting step A (S140A) in FIG. 9, and the melting step B (S140B) in FIG. The solder film may be heated and melted by directly applying heat.

＜第４の実施の形態＞
本実施の形態では、図１の半導体装置１００の製造において用いられる内部接続部材の製造方法について説明する。本実施の形態では、一例として、第１の実施の形態で使用される内部接続部材７０を製造する方法について説明する。 <Fourth embodiment>
In the present embodiment, a method for manufacturing an internal connection member used in manufacturing the semiconductor device 100 of FIG. 1 will be described. In the present embodiment, as an example, a method for manufacturing the internal connection member 70 used in the first embodiment will be described.

図１３は、内部接続部材７０の製造方法を説明するための図である。
内部接続部材７０の製造には、図１３（ａ）の金属片７１ｎが使用される。金属片７１ｎは、Ｃｕを主組成とする。金属片７１ｎの形状は、薄板状である。金属片７１ｎは、フープ状の連続したＣｕ材から構成される。 FIG. 13 is a diagram for explaining a method of manufacturing the internal connection member 70.
For the manufacture of the internal connection member 70, the metal piece 71n shown in FIG. The metal piece 71n has Cu as the main composition. The shape of the metal piece 71n is a thin plate. The metal piece 71n is made of a hoop-like continuous Cu material.

次に、内部接続部材７０の製造方法について説明する。
まず、金属片７１ｎの表面粗さＲａが、０．３μｍ以上になるように、金属片７１ｎの表面が粗化される。 Next, a method for manufacturing the internal connection member 70 will be described.
First, the surface of the metal piece 71n is roughened so that the surface roughness Ra of the metal piece 71n is 0.3 μm or more.

次に、図１３（ａ）のように、金属片７１ｎの表面に、半田皮膜７２ａ，７２ｂが形成される。半田皮膜７２ａ，７２ｂの各々は、Ｂｉめっきを主組成とする。   Next, as shown in FIG. 13A, solder films 72a and 72b are formed on the surface of the metal piece 71n. Each of the solder films 72a and 72b has Bi plating as a main composition.

次に、半田皮膜７２ａ，７２ｂが形成された図１３（ａ）の金属片７１ｎの形状が所定の形状になるように、金属片７１ｎに対し型抜きおよび曲げ加工を行う。   Next, die cutting and bending are performed on the metal piece 71n so that the shape of the metal piece 71n in FIG. 13A on which the solder films 72a and 72b are formed becomes a predetermined shape.

この際に、金属片７１ｎの一部は長手方向に延在するフレーム部７１ｆとして成型される。また、上記型抜きおよび曲げ加工により、図１３（ｂ）のように、金属片７１の表面の一部に半田皮膜７２ａ，７２ｂが形成された内部接続部材７０が複数生成される。これにより、図１３（ｂ）のように、複数の内部接続部材７０の各々は、支持部７１ｃにより、フレーム部７１ｆと繋がった内部接続部材群７００が生成される。すなわち、フレーム部７１ｆには、複数の内部接続部材７０が連続的に繋がっている。   At this time, a part of the metal piece 71n is molded as a frame portion 71f extending in the longitudinal direction. Further, by the above die cutting and bending process, a plurality of internal connection members 70 in which solder films 72a and 72b are formed on a part of the surface of the metal piece 71 are generated as shown in FIG. 13B. As a result, as shown in FIG. 13B, each of the plurality of internal connection members 70 generates the internal connection member group 700 connected to the frame portion 71f by the support portion 71c. That is, a plurality of internal connection members 70 are continuously connected to the frame portion 71f.

すなわち、内部接続部材群７００は、複数の内部接続部材７０と、当該複数の内部接続部材７０に共通して接続されるフレーム部７１ｆとを含む。   That is, the internal connection member group 700 includes a plurality of internal connection members 70 and a frame portion 71 f that is commonly connected to the plurality of internal connection members 70.

この内部接続部材群７００により、半導体装置の組立て装置に対し、内部接続部材７０を連続的に供給することが可能となる。すなわち、半田接続直前に、複数の内部接続部材７０の各々に接続される支持部７１ｃを切断することにより、複数の内部接続部材７０を、連続的に供給（生成）することが可能となる（図１３（ｃ）参照）。   With this internal connection member group 700, the internal connection member 70 can be continuously supplied to the semiconductor device assembly apparatus. That is, by cutting the support portion 71c connected to each of the plurality of internal connection members 70 immediately before the solder connection, the plurality of internal connection members 70 can be continuously supplied (generated) ( (Refer FIG.13 (c)).

すなわち、内部接続部材群７００は、内部接続部材を複数取得可能な半導体内部接続部材群である。   That is, the internal connection member group 700 is a semiconductor internal connection member group that can acquire a plurality of internal connection members.

以上説明した内部接続部材群７００を用いて、複数の内部接続部材を順次切り離すことにより、内部接続を行う半導体装置に対し、内部接続部材を連続的に供給することが可能となり、半導体装置の生産性が向上する。   By sequentially separating a plurality of internal connection members using the internal connection member group 700 described above, it becomes possible to continuously supply the internal connection members to the semiconductor device that performs internal connection, and the production of the semiconductor device Improves.

（内部接続部材について）
本発明で使用される内部接続部材は、第１〜第４の実施の形態で説明した内部接続部材７０，７０ａ，７０ｂに限定されない。以下に、第１〜第４の実施の形態で使用可能なＺｎ−Ａｌ系内部接続部材および多層半田形成内部接続部材について説明する。 (About internal connection members)
The internal connection member used in the present invention is not limited to the internal connection members 70, 70a, and 70b described in the first to fourth embodiments. Below, the Zn-Al type internal connection member and multilayer solder formation internal connection member which can be used by the 1st-4th embodiment are demonstrated.

Ｚｎ−Ａｌ系内部接続部材および多層半田形成内部接続部材の各々の構成は、内部接続部材７０，７０ａ，７０ｂの構成とは異なる。   The configurations of the Zn—Al-based internal connection member and the multilayer solder-formed internal connection member are different from the configurations of the internal connection members 70, 70a, and 70b.

本発明では、内部接続部材７０，７０ａ，７０ｂの各々代わりに、Ｚｎ−Ａｌ系内部接続部材および多層半田形成内部接続部材のいずれが使用されてもよい。   In the present invention, instead of each of the internal connection members 70, 70a, 70b, either a Zn—Al internal connection member or a multilayer solder-formed internal connection member may be used.

（Ｚｎ−Ａｌ系内部接続部材）
まず、Ｚｎ−Ａｌ系内部接続部材について説明する。Ｚｎ−Ａｌ系内部接続部材は、図１４の内部接続部材１７０であるとする。 (Zn-Al internal connection member)
First, the Zn—Al based internal connection member will be described. The Zn—Al-based internal connection member is assumed to be the internal connection member 170 of FIG.

図１４は、一例としての内部接続部材１７０を示す図である。
内部接続部材１７０は、金属片１７１と、半田皮膜１７２とを含む。金属片１７１の表面には、半田皮膜１７２が形成される。 FIG. 14 is a diagram showing an internal connection member 170 as an example.
The internal connection member 170 includes a metal piece 171 and a solder film 172. A solder film 172 is formed on the surface of the metal piece 171.

金属片１７１は、Ｃｕを主組成とする。半田皮膜１７２の融点は、２６０℃以上である。半田皮膜１７２は、鉛が含有されていない鉛フリーの半田皮膜である。半田皮膜１７２は、Ｚｎ−Ａｌ合金を主組成とする。すなわち、半田皮膜１７２は、Ｚｎ、Ａｌを主組成とする。半田皮膜１７２の厚みは、一例として、４０μｍである。   The metal piece 171 has Cu as the main composition. The melting point of the solder film 172 is 260 ° C. or higher. The solder film 172 is a lead-free solder film that does not contain lead. The solder film 172 has a Zn—Al alloy as a main composition. That is, the solder film 172 has Zn and Al as the main composition. As an example, the thickness of the solder film 172 is 40 μm.

なお、金属片１７１は、前述した金属片７１，金属片としてのダイパッド５１ａおよび金属片７１ｂのいずれかに相当する。また、半田皮膜１７２は、前述した、半田皮膜７２ａ，７２ｂ、７２ｃ，７２ｄ，７２ｅのいずれかに相当する。   The metal piece 171 corresponds to any one of the metal piece 71, the die pad 51a as the metal piece, and the metal piece 71b described above. The solder film 172 corresponds to one of the solder films 72a, 72b, 72c, 72d, and 72e described above.

半田皮膜１７２の表面には、薄膜１７３が形成される。薄膜１７３は、一例として、Ａｕ薄膜である。すなわち、半田皮膜１７２の表面には、Ａｕ薄膜が形成される。薄膜１７３の厚みは、一例として、０．０５μｍである。   A thin film 173 is formed on the surface of the solder film 172. The thin film 173 is an Au thin film as an example. That is, an Au thin film is formed on the surface of the solder film 172. The thickness of the thin film 173 is, for example, 0.05 μm.

次に、Ｚｎ−Ａｌ系内部接続部材としての内部接続部材１７０の製造方法について説明する。   Next, the manufacturing method of the internal connection member 170 as a Zn-Al type internal connection member is demonstrated.

まず、スパッタ装置が、金属片１７１の表面の酸化膜を、逆スパッタによって除去する。次に、スパッタ法によって、金属片１７１の表面に半田皮膜１７２が成膜される。ここで、上記スパッタ法は、Ｚｎ、Ａｌなど所望の組成からなる多元ターゲットを用いたスパッタ法である。   First, the sputtering apparatus removes the oxide film on the surface of the metal piece 171 by reverse sputtering. Next, a solder film 172 is formed on the surface of the metal piece 171 by sputtering. Here, the sputtering method is a sputtering method using a multi-target having a desired composition such as Zn or Al.

そして、半田皮膜１７２の表面に薄膜１７３が成膜される。
以上により、Ｚｎ−Ａｌ系内部接続部材としての内部接続部材１７０が製造される。 Then, a thin film 173 is formed on the surface of the solder film 172.
As described above, the internal connection member 170 as the Zn—Al-based internal connection member is manufactured.

Ｚｎ−Ａｌ合金の融点は、３００℃以上である。そのため、Ｚｎ−Ａｌ合金は、より高温に耐える半田材料として期待される。ＺｎおよびＡｌは、Ｂｉなどに比べて酸化され易い金属である。そのため、より酸化を抑える必要があり、最表面にＡｕ膜を成膜して半田皮膜の表面酸化を防止している。   The melting point of the Zn—Al alloy is 300 ° C. or higher. Therefore, a Zn-Al alloy is expected as a solder material that can withstand higher temperatures. Zn and Al are metals that are more easily oxidized than Bi and the like. Therefore, it is necessary to further suppress oxidation, and an Au film is formed on the outermost surface to prevent the surface oxidation of the solder film.

半田皮膜１７２は、Ｚｎ、Ａｌを主組成とすることにより、より融点が高温となり耐熱性の高い半導体装置を実現できる。   By using Zn and Al as the main composition, the solder film 172 has a higher melting point and can realize a semiconductor device with high heat resistance.

（多層半田形成内部接続部材）
次に、多層半田形成内部接続部材について説明する。多層半田形成内部接続部材は、金属片の表面に多層半田皮膜が形成されたものである。多層半田形成内部接続部材は、図１５の内部接続部材１７０ａであるとする。 (Multilayer solder forming internal connection member)
Next, the multilayer solder forming internal connection member will be described. The multilayer solder-formed internal connection member has a multilayer solder film formed on the surface of a metal piece. The multilayer solder forming internal connection member is assumed to be the internal connection member 170a of FIG.

図１５は、一例としての内部接続部材１７０ａを示す図である。
内部接続部材１７０ａは、金属片１７１と、半田皮膜１７２ｎとを含む。金属片１７１の表面には、半田皮膜１７２ｎが形成される。 FIG. 15 is a diagram illustrating an internal connection member 170a as an example.
The internal connection member 170a includes a metal piece 171 and a solder film 172n. A solder coating 172n is formed on the surface of the metal piece 171.

金属片１７１は、Ｃｕを主組成とする。半田皮膜１７２ｎの融点は、２６０℃以上である。半田皮膜１７２ｎは、鉛が含有されていない鉛フリーの半田皮膜である。   The metal piece 171 has Cu as the main composition. The melting point of the solder film 172n is 260 ° C. or higher. The solder film 172n is a lead-free solder film that does not contain lead.

半田皮膜１７２ｎは、層１７２ａ，１７２ｂ，１７２ｃから構成される。層１７２ａ，１７２ｂ，１７２ｃのうちの少なくとも２つの層は、異なる材料の層である。半田皮膜１７２ｎは、前述した、半田皮膜７２ａ，７２ｂ、７２ｃ，７２ｄ，７２ｅのいずれかに相当する。   The solder film 172n is composed of layers 172a, 172b, and 172c. At least two of the layers 172a, 172b, 172c are layers of different materials. The solder film 172n corresponds to any of the solder films 72a, 72b, 72c, 72d, and 72e described above.

すなわち、半田皮膜１７２ｎは、２以上の異なる材料の層を少なくとも含む複数の層により構成される。   That is, the solder film 172n is composed of a plurality of layers including at least two layers of different materials.

層１７２ａは、Ｂｉを主組成とする層（Ｂｉ薄膜）である。層１７２ａの厚みは、一例として、１０μｍである。層１７２ｂは、Ｃｕを主組成とする層（Ｃｕ薄膜）である。層１７２ｂの厚みは、一例として、０．１μｍである。層１７２ｃは、Ｂｉを主組成とする層（Ｂｉ薄膜）である。層１７２ｃの厚みは、一例として、１０μｍである。   The layer 172a is a layer (Bi thin film) whose main composition is Bi. As an example, the thickness of the layer 172a is 10 μm. The layer 172b is a layer (Cu thin film) whose main composition is Cu. As an example, the thickness of the layer 172b is 0.1 μm. The layer 172c is a layer (Bi thin film) whose main composition is Bi. The thickness of the layer 172c is 10 μm as an example.

すなわち、半田皮膜１７２ｎを構成する複数の層は、Ｂｉを主組成とする層とＣｕを主組成とする層とを含む。   That is, the plurality of layers constituting the solder film 172n include a layer mainly composed of Bi and a layer mainly composed of Cu.

また、Ｂｉの融点は２７１．５℃である。すなわち、半田皮膜１７２ｎを構成する複数の層のうちの第１層としての層１７２ａ（層１７２ｃ）は、融点が２６０℃から４００℃の間の材料Ｂｉを主組成とする。   Bi has a melting point of 271.5 ° C. That is, the layer 172a (layer 172c) as the first layer among the plurality of layers constituting the solder film 172n has a main composition of the material Bi having a melting point between 260 ° C. and 400 ° C.

なお、第１層としての層１７２ａ（層１７２ｃ）に隣接する第２層としての層１７２ｂの材料Ｃｕの融点は、第１層の組成の材料Ｂｉの融点より低い。   Note that the melting point of the material Cu of the layer 172b as the second layer adjacent to the layer 172a (layer 172c) as the first layer is lower than the melting point of the material Bi of the composition of the first layer.

次に、多層半田形成内部接続部材としての内部接続部材１７０ａの製造方法について説明する。   Next, the manufacturing method of the internal connection member 170a as a multilayer solder formation internal connection member is demonstrated.

まず、金属片１７１の表面に層１７２ａが成膜される。次に、層１７２ａの表面に層１７２ｂが成膜される。次に、層１７２ｂの表面に層１７２ｃが成膜される。   First, the layer 172a is formed on the surface of the metal piece 171. Next, a layer 172b is formed on the surface of the layer 172a. Next, a layer 172c is formed on the surface of the layer 172b.

以上により、多層半田形成内部接続部材としての内部接続部材１７０ａが製造される。
この様に、半田皮膜を複数の組成からなる層とすることで、半田接続時の加熱で、まずＢｉが溶融し、溶融したＢｉにＣｕが溶解できる。これにより、Ｃｕ薄膜が溶出しＢｉ−Ｃｕ組成の合成半田が生成される。Ｂｉ−Ｃｕ組成の合成半田の融点は、２６０℃以上である。 As described above, the internal connection member 170a as the multilayer solder formation internal connection member is manufactured.
Thus, by making the solder film into a layer having a plurality of compositions, Bi is first melted by heating at the time of solder connection, and Cu can be dissolved in the melted Bi. Thereby, Cu thin film elutes and the synthetic solder of a Bi-Cu composition is produced | generated. The melting point of the synthetic solder having the Bi—Cu composition is 260 ° C. or higher.

すなわち、加熱により半田皮膜１７２ｎが溶融される場合、つまり、半田溶融時に、第２層としての層１７２ｂは、第１層（層１７２ａまたは層１７２ｃ）の組成を第２層に取り込んで合成半田となり、当該合成半田の融点は、２６０℃以上となる。   That is, when the solder film 172n is melted by heating, that is, when the solder is melted, the layer 172b as the second layer takes the composition of the first layer (the layer 172a or the layer 172c) into the second layer and becomes a synthetic solder. The melting point of the synthetic solder is 260 ° C. or higher.

層１７２ａ，１７２ｃの主組成であるＢｉ単体の融点は２７１．５℃であり、限界温度に極めて近い。ここで、限界温度とは、半導体装置を基板に実装する際にリフローなどで再溶融が懸念される温度である。   The melting point of Bi alone, which is the main composition of the layers 172a and 172c, is 271.5 ° C., which is very close to the limit temperature. Here, the limit temperature is a temperature at which remelting is a concern due to reflow or the like when the semiconductor device is mounted on the substrate.

しかしながら、半田接続時において、Ｂｉ中のＣｕ組成比が増えることにより、Ｂｉ−Ｃｕ組成の半田の融点が上昇し、より高温に耐える半導体装置を実現できる。すなわち、Ｂｉが溶融した際に、ＢｉにＣｕが取り込まれ、より高温での使用が可能となる。   However, when the Cu composition ratio in Bi increases at the time of solder connection, the melting point of the Bi—Cu composition solder rises, and a semiconductor device that can withstand higher temperatures can be realized. That is, when Bi is melted, Cu is taken into Bi and can be used at a higher temperature.

なお、層１７２ｂは、Ｃｕの代わりにＡｇを主組成とする層（Ａｇ薄膜）であってもよい。この場合、半田皮膜１７２ｎを構成する複数の層は、Ｂｉを主組成とする層とＡｇを主組成とする層を含む。   The layer 172b may be a layer (Ag thin film) containing Ag as a main composition instead of Cu. In this case, the plurality of layers constituting the solder film 172n include a layer mainly composed of Bi and a layer mainly composed of Ag.

この場合、半田皮膜１７２ｎが溶融される場合、Ｂｉ−Ａｇ合金が生成される。Ａｇの場合、Ｂｉとの共晶点で一旦融点が下がるが、Ａｇ膜の厚さを共晶点よりもＡｇ濃度が濃くなるように選択する。これにより、Ｂｉ−Ａｇ合金の融点を、Ｂｉ単体の融点よりも上昇させることができる。すなわち、Ｂｉが溶融した際に、当該ＢｉにＡｇが取り込まれより高温での使用が可能となる。   In this case, when the solder film 172n is melted, a Bi—Ag alloy is generated. In the case of Ag, the melting point once falls at the eutectic point with Bi, but the thickness of the Ag film is selected so that the Ag concentration is higher than the eutectic point. Thereby, melting | fusing point of Bi-Ag alloy can be raised rather than melting | fusing point of Bi single-piece | unit. That is, when Bi is melted, Ag is taken into the Bi and can be used at a higher temperature.

また、層１７２ｂは、Ｃｕの代わりにＮｉ（ニッケル）を主組成とする層（Ｎｉ薄膜）であってもよい。すなわち、半田皮膜１７２ｎを構成する複数の層は、Ｂｉを主組成とする層とＮｉを主組成とする層を含む。   Further, the layer 172b may be a layer (Ni thin film) whose main composition is Ni (nickel) instead of Cu. That is, the plurality of layers constituting the solder coating 172n include a layer mainly composed of Bi and a layer mainly composed of Ni.

この場合、高温で半田接合を行うことにより、半田皮膜１７２ｎが溶融される際、融点の高いＢｉ３Ｎｉ合金層が形成されて半田接続が行われる。これにより、半田接続による接合部の耐熱を格段に向上させることができる。   In this case, by performing solder bonding at a high temperature, when the solder film 172n is melted, a Bi3Ni alloy layer having a high melting point is formed and solder connection is performed. Thereby, the heat resistance of the joint part by solder connection can be remarkably improved.

つまり、Ｂｉが溶融した際にＮｉが取り込まれ、より高温での使用が可能となる。
また、層１７２ａ，１７２ｃは、Ｂｉの代わりにＳｎを主組成とする低融点層（Ｓｎ薄膜）であってもよい。Ｓｎの融点は、２３２℃である。つまり、半田皮膜１７２ｎを構成する複数の層には、低融点層としてＳｎ皮膜と、高融点層としてＣｕ皮膜とが用いられてもよい。すなわち、半田皮膜１７２ｎを構成する複数の層は、Ｓｎを主組成とする層およびＣｕを主組成とする層を含む。 That is, Ni is taken in when Bi is melted, and can be used at a higher temperature.
Further, the layers 172a and 172c may be low melting point layers (Sn thin film) having Sn as a main composition instead of Bi. The melting point of Sn is 232 ° C. That is, for the plurality of layers constituting the solder coating 172n, an Sn coating as the low melting point layer and a Cu coating as the high melting point layer may be used. That is, the plurality of layers constituting the solder film 172n includes a layer mainly composed of Sn and a layer mainly composed of Cu.

Ｓｎの融点は２３２℃であり、２６０℃に比べて極めて低い。しかしながら、半田皮膜１７２ｎが溶融される際、Ｓｎが溶融しＣｕ皮膜の組成を取り込むことで、Ｃｕ６Ｓｎ５などの融点の高い金属間化合物層が形成される。これにより、実質的な融点を上昇させることができる。   The melting point of Sn is 232 ° C., which is very low compared to 260 ° C. However, when the solder film 172n is melted, Sn melts and the composition of the Cu film is taken in, so that an intermetallic compound layer having a high melting point such as Cu6Sn5 is formed. Thereby, substantial melting | fusing point can be raised.

つまり、２６０℃以下のＳｎを主組成とした半田を用いながらも、Ｓｎを溶融することにより、Ｃｕ組成を取り込み融点が上昇し、２６０℃以上の高温半田として使用が可能となる。   That is, while using a solder whose main composition is Sn at 260 ° C. or lower, melting the Sn increases the melting point by melting Sn, and can be used as a high-temperature solder at 260 ° C. or higher.

なお、複数の組成の多層皮膜で半田皮膜を構成した場合、半田接合の際の温度が高いほど低融点の組成の層が他の高融点の層の組成をより取り込み、融点の上昇が期待できる。しかしながら、半導体製造装置の多くは４００℃以下で正常動作するよう設計されている。そのため、汎用性を考慮すると、多層皮膜の低融点層は４００℃以下で溶融できることが望ましい。   In addition, when the solder film is composed of a multilayer film having a plurality of compositions, the higher the temperature at the time of soldering, the lower the melting point of the layer, the more the composition of the other high melting point layer is taken in, and an increase in the melting point can be expected. . However, many semiconductor manufacturing apparatuses are designed to operate normally at 400 ° C. or lower. Therefore, considering versatility, it is desirable that the low melting point layer of the multilayer coating can be melted at 400 ° C. or lower.

今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

本発明は、大電流を扱うパワー半導体における半田接続に有用である。   The present invention is useful for solder connection in a power semiconductor that handles a large current.

１０ 半導体チップ
２０，２０ａ 電極
２１，２１ａ 電極パッド
３０，７２ａ，７２ｂ，７２ｃ、７２ｄ，７２ｅ，１７２，１７２ｎ 半田皮膜
５０，５０ａ リードフレーム
５１，５１ａ ダイパッド
５２，５２ａ インナーリード部
７０，７０ａ，７０ｂ，１７０，１７０ａ 内部接続部材
７１，７１ｂ，７１ｎ，１７１ 金属片
７１ｃ 支持部
７１ｆ フレーム部
８０ アルミワイヤー
１００ 半導体装置
１１０ 封止樹脂
１２０ 外部端子
１７２ａ，１７２ｂ，１７２ｃ 層
１７３ 薄膜
７００ 内部接続部材群 10 Semiconductor chip 20, 20a Electrodes 21, 21a Electrode pads 30, 72a, 72b, 72c, 72d, 72e, 172, 172n Solder coating 50, 50a Lead frames 51, 51a Die pads 52, 52a Inner lead portions 70, 70a, 70b, 170, 170a Internal connection members 71, 71b, 71n, 171 Metal piece 71c Support portion 71f Frame portion 80 Aluminum wire 100 Semiconductor device 110 Sealing resin 120 External terminals 172a, 172b, 172c Layer 173 Thin film 700 Internal connection member group

Claims (18)

内部接続部材と半田接続される半導体チップを含む半導体装置の製造方法であって、
前記半導体チップには、電極が形成されており、
前記内部接続部材は、所定形状の金属片と、鉛フリーの半田皮膜とを含み、
前記金属片の表面の少なくとも一部には、前記半田皮膜が形成され、
前記半田皮膜の融点は、２６０℃以上であり、
前記半導体装置の製造方法は、
前記金属片に形成される前記半田皮膜と、前記半導体チップの前記電極とが少なくとも接するように前記内部接続部材または前記半導体チップを配置する第１工程と、
前記半田皮膜を加熱溶融することにより、前記内部接続部材と前記半導体チップとを半田接続する第２工程とを含む
半導体装置の製造方法。 A method of manufacturing a semiconductor device including a semiconductor chip solder-connected to an internal connection member,
An electrode is formed on the semiconductor chip,
The internal connection member includes a predetermined-shaped metal piece and a lead-free solder film,
The solder film is formed on at least a part of the surface of the metal piece,
The melting point of the solder film is 260 ° C. or higher,
The method for manufacturing the semiconductor device includes:
A first step of arranging the internal connection member or the semiconductor chip so that the solder film formed on the metal piece and at least the electrode of the semiconductor chip are in contact with each other;
A method of manufacturing a semiconductor device, comprising: a second step of solder-connecting the internal connection member and the semiconductor chip by heating and melting the solder film. 前記半導体装置には、インナーリード部が形成されたリードフレームが使用され、
前記金属片の形状は、前記半導体チップの前記電極と、前記リードフレームの前記インナーリード部とを跨ぐ形状であり、
前記電極および前記インナーリード部の上方に前記金属片を配置した状態において、前記半田皮膜が形成された前記金属片の表面の一部は、前記金属片のうち、前記電極および前記インナーリード部にそれぞれ対向する第１領域および第２領域であり、
前記第１工程では、前記第１領域に形成された半田皮膜および前記第２領域に形成された半田皮膜を、それぞれ、前記電極および前記インナーリード部に接するように前記内部接続部材を配置し、
前記第２工程では、前記第１領域に形成された半田皮膜および前記第２領域に形成された半田皮膜を加熱溶融することにより、前記内部接続部材を前記半導体チップおよび前記リードフレームに半田接続する
請求項１に記載の半導体装置の製造方法。 The semiconductor device uses a lead frame in which an inner lead portion is formed,
The shape of the metal piece is a shape straddling the electrode of the semiconductor chip and the inner lead portion of the lead frame,
In a state where the metal piece is disposed above the electrode and the inner lead portion, a part of the surface of the metal piece on which the solder film is formed is formed on the electrode and the inner lead portion of the metal piece. A first region and a second region facing each other,
In the first step, the internal connection member is disposed so that the solder film formed in the first region and the solder film formed in the second region are in contact with the electrode and the inner lead part, respectively.
In the second step, the internal connection member is solder-connected to the semiconductor chip and the lead frame by heating and melting the solder film formed in the first region and the solder film formed in the second region. A method for manufacturing a semiconductor device according to claim 1. 前記半導体装置には、金属片としてのリードフレームが使用され、
前記リードフレームの少なくとも一部には、前記半田皮膜が形成され、
前記半田皮膜が形成された、前記リードフレームの少なくとも一部は、前記内部接続部材であり、
前記第２工程では、前記内部接続部材としての前記リードフレームの少なくとも一部と、前記半導体チップとを半田接続する、
請求項１に記載の半導体装置の製造方法。 In the semiconductor device, a lead frame as a metal piece is used,
The solder film is formed on at least a part of the lead frame,
The solder film is formed, at least a part of the lead frame is the internal connection member,
In the second step, at least a part of the lead frame as the internal connection member and the semiconductor chip are solder-connected,
A method for manufacturing a semiconductor device according to claim 1. 前記半導体装置には、ダイパッドが形成されたリードフレームが使用され、
前記金属片の形状は、平面形状であり、
前記金属片の主面および該主面の反対面に前記半田皮膜が形成された該金属片は、前記内部接続部材であり、
前記半導体装置の製造方法は、さらに、
前記金属片の反対面に形成された半田皮膜と前記ダイパッドとが接するように、前記内部接続部材を配置する工程を含み、
前記第２工程では、前記金属片の反対面に形成された半田皮膜および前記金属片の主面に形成された半田皮膜を過熱溶融することにより、前記内部接続部材と前記ダイパッドとを半田接続し、
前記第１工程では、前記ダイパッドに半田接続された前記内部接続部材における前記金属片の主面に形成された溶融した半田皮膜と、前記半導体チップの前記電極とが接するように前記半導体チップを配置し、
前記内部接続部材と前記半導体チップとが半田接続される
請求項１に記載の半導体装置の製造方法。 The semiconductor device uses a lead frame in which a die pad is formed,
The shape of the metal piece is a planar shape,
The metal piece in which the solder film is formed on the main surface of the metal piece and the opposite surface of the main surface is the internal connection member,
The method for manufacturing the semiconductor device further includes:
Including the step of arranging the internal connection member so that the solder film formed on the opposite surface of the metal piece and the die pad are in contact with each other;
In the second step, the internal connection member and the die pad are solder-connected by overheating and melting the solder film formed on the opposite surface of the metal piece and the solder film formed on the main surface of the metal piece. ,
In the first step, the semiconductor chip is disposed so that the molten solder film formed on the main surface of the metal piece in the internal connection member solder-connected to the die pad and the electrode of the semiconductor chip are in contact with each other. And
The method for manufacturing a semiconductor device according to claim 1, wherein the internal connection member and the semiconductor chip are solder-connected. 半田接続に使用される半導体内部接続部材であって、
前記半導体内部接続部材は、金属片と、鉛フリーの半田皮膜とを含み、
前記金属片の表面の少なくとも一部には、前記半田皮膜が形成され、
前記半田皮膜の融点は、２６０℃以上である
半導体内部接続部材。 A semiconductor internal connection member used for solder connection,
The semiconductor internal connection member includes a metal piece and a lead-free solder film,
The solder film is formed on at least a part of the surface of the metal piece,
The melting point of the solder film is 260 ° C. or more. Semiconductor internal connection member. 前記金属片の形状は、半田接続の対象となる少なくとも２箇所を繋ぐ形状である
請求項５に記載の半導体内部接続部材。 The semiconductor internal connection member according to claim 5, wherein the shape of the metal piece is a shape connecting at least two places to be soldered. 前記金属片の熱膨張率は、Ｃｕの熱膨張率とＳｉの熱膨張率との間の値である
請求項５に記載の半導体内部接続部材。 The semiconductor internal connection member according to claim 5, wherein a thermal expansion coefficient of the metal piece is a value between a thermal expansion coefficient of Cu and a thermal expansion coefficient of Si. 前記金属片の表面粗さＲａは、０．３μｍ以上である
請求項５に記載の半導体内部接続部材。 The semiconductor internal connection member according to claim 5, wherein a surface roughness Ra of the metal piece is 0.3 μm or more. 前記金属片は、Ｃｕを主組成とし、
前記金属片の形状は、平面形状であり、
前記半田皮膜は、Ｂｉを主組成とし、
前記金属片の表面には、Ｂｉを主組成とする前記半田皮膜が直接形成される
請求項５に記載の半導体内部接続部材。 The metal piece is mainly composed of Cu,
The shape of the metal piece is a planar shape,
The solder film is mainly composed of Bi,
The semiconductor internal connection member according to claim 5, wherein the solder film mainly containing Bi is directly formed on a surface of the metal piece. 前記半田皮膜の表面には、さらに、ＡｇまたはＡｕ薄膜が形成される
請求項５に記載の半導体内部接続部材。 The semiconductor internal connection member according to claim 5, wherein an Ag or Au thin film is further formed on the surface of the solder film. 前記半田皮膜は、Ｚｎ、Ａｌを主組成とする
請求項５に記載の半導体内部接続部材。 The semiconductor internal connection member according to claim 5, wherein the solder film has a main composition of Zn and Al. 前記半田皮膜は、２以上の異なる材料の層を少なくとも含む複数の層により構成される
請求項５に記載の半導体内部接続部材。 The semiconductor internal connection member according to claim 5, wherein the solder film includes a plurality of layers including at least two layers of different materials. 前記複数の層のうちの第１層は、融点が２６０℃から４００℃の間の材料を主組成とし、
前記第１層に隣接する第２層の材料の融点は、前記第１層の組成の材料の融点より低く、
前記第２層は、半田溶融時に、前記第１層の組成を前記第２層に取り込んで合成半田となり、当該合成半田の融点は、２６０℃以上となる、
請求項１２に記載の半導体内部接続部材。 The first layer of the plurality of layers is mainly composed of a material having a melting point between 260 ° C. and 400 ° C.
The melting point of the material of the second layer adjacent to the first layer is lower than the melting point of the material of the composition of the first layer,
The second layer, when the solder is melted, takes the composition of the first layer into the second layer to become a synthetic solder, and the melting point of the synthetic solder is 260 ° C. or higher.
The semiconductor internal connection member according to claim 12. 前記複数の層は、Ｓｎを主組成とする層およびＣｕを主組成とする層を含む、
請求項１３に記載の半導体内部接続部材。 The plurality of layers include a layer mainly composed of Sn and a layer mainly composed of Cu.
The semiconductor internal connection member according to claim 13. 前記複数の層は、Ｂｉを主組成とする層とＣｕを主組成とする層とを含む
請求項１３に記載の半導体内部接続部材。 The semiconductor internal connection member according to claim 13, wherein the plurality of layers include a layer mainly composed of Bi and a layer mainly composed of Cu. 前記複数の層は、Ｂｉを主組成とする層とＡｇを主組成とする層を含む
請求項１３に記載の半導体内部接続部材。 The semiconductor internal connection member according to claim 13, wherein the plurality of layers include a layer mainly composed of Bi and a layer mainly composed of Ag. 前記複数の層は、Ｂｉを主組成とする層とＮｉを主組成とする層を含む
請求項１３に記載の半導体内部接続部材。 The semiconductor internal connection member according to claim 13, wherein the plurality of layers include a layer mainly composed of Bi and a layer mainly composed of Ni. 請求項５に記載の半導体内部接続部材を複数取得可能な半導体内部接続部材群であって、
前記半導体内部接続部材群は、
複数の前記半導体内部接続部材と、
前記複数の半導体内部接続部材に共通して接続されるフレーム部とを含む、
半導体内部接続部材群。 A semiconductor internal connection member group capable of acquiring a plurality of semiconductor internal connection members according to claim 5,
The semiconductor internal connection member group includes:
A plurality of the semiconductor internal connection members;
A frame portion connected in common to the plurality of semiconductor internal connection members,
Semiconductor internal connection member group.
JP2010114805A 2010-05-18 2010-05-18 Semiconductor device manufacturing method, internal semiconductor connection member, and internal semiconductor connection member group Pending JP2011243752A (en)

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