JP2004264461A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To greatly reduce the number of interfaces with respect to gradation voltage in particular, among power source systems supplied from the main control board to the source control board in a TFT liquid crystal display device. <P>SOLUTION: The gradation voltage in a plurality of steps is formed as staircase waveforms in the first gradation voltage forming circuit 42 on the side of the main control board 40 and transmitted to the source control board 20 connected to a TFT array board 10 time sequentially. The staircase waveforms are then sorted by a gradation voltage selecting circuit on the side of the source control substrate 20 and imparted to each input terminal of the second gradation voltage forming circuit on the side of the source control board. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a liquid crystal display device including a TFT array substrate, and more particularly, to a technique for reducing the number of control lines for gradation display.
[0002]
[Prior art]
In a TFT type liquid crystal display device, a predetermined display can be obtained by controlling each voltage of a gate electrode and a source electrode of a TFT (thin film transistor) provided for each pixel of a TFT array substrate.
[0003]
As a control system therefor, a source control substrate and a gate control substrate each having a driver composed of an IC chip are connected to the source line side terminal portion and the gate line side terminal portion of the TFT array substrate, respectively. It is connected to a main control board having a power supply circuit, a timing controller, a gradation voltage generation circuit, and the like via a relay board.
[0004]
As described above, in the specification in which the main control board is separated via the relay board, the connection between the main control board and the source control board requires, for example, a signal system alone in an 8-bit interface, requiring 48 lines. This includes a control signal line (5 lines for a start pulse, a latch pulse, a clock, etc.), a gradation voltage line (18 lines), and a power supply (for example, 3.3 V, 10 V, and 3 lines for GND), for a total of 74 lines. A book interface is needed.
[0005]
In order to reduce this number, in the signal system, the number of 48 signal lines is reduced by a signal multiplexing technique. As the signal multiplexing method, for example, RSDS of National Semiconductor (NS), MiniLVDS of Texas Instruments (TI), and CMADS of NEC (NEC) are known.
[0006]
[Problems to be solved by the invention]
On the other hand, in a power supply system including a gray scale voltage, the number of interfaces tends to increase as the number of gray scales increases, but a practical method for reducing the number of interfaces in the power supply system has been proposed so far. Not done. Therefore, an object of the present invention is to reduce the number of interfaces for a power supply system, particularly for a grayscale voltage.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a liquid crystal display panel including a TFT array substrate to which a gate control substrate and a source control substrate are connected, and a main control substrate connected to each of the control substrates. In a liquid crystal display device that applies a gate drive voltage from the substrate to the gate control substrate, applies a grayscale signal to the source control substrate, and drives the liquid crystal display panel, the main control substrate controls a predetermined period of a horizontal synchronization signal. A timing controller that outputs a voltage generation control pulse a plurality of times in each cycle at a fraction of the integer, and a step-like gradation voltage including a voltage of a predetermined number of steps in response to the voltage generation control pulse. A first grayscale voltage generation circuit for generating the voltage generation control signal from the main control board to the source control board. And the source control board is provided with a voltage input terminal equal to the number of steps of the staircase grayscale voltage, and a predetermined number of grayscales is obtained from the input voltage. A second grayscale voltage generation circuit for generating a voltage and outputting the voltage to the source electrode of the TFT array substrate; and selecting each voltage included in the staircase grayscale voltage by the voltage generation control pulse to input the voltage. And a gradation voltage selection circuit for distributing to a terminal.
[0008]
For example, assuming that the gradation voltage generated on the main control board side has ten steps, conventionally, the voltage of these ten steps is transmitted to the source control board through ten interfaces. By using the staircase waveform of the step, one interface can be used. Actually, another interface is required for transmitting the voltage generation control pulse, so that the total number is two.
[0009]
According to the present invention, the voltages distributed by the gradation voltage selection circuit are intermittently input to the respective voltage input terminals of the second gradation voltage generation circuit on the source control substrate side. It is preferable to connect a voltage holding circuit that holds a voltage until the next voltage is input to a gradation voltage input line of the circuit. The voltage holding circuit may be a capacitor.
[0010]
The gradation voltage selection circuit is composed of, for example, a multiplexer, and sequentially switches the output cyclically by a voltage generation control pulse transmitted from the main control board. The generation interval of the voltage generation control pulse depends on the period (frame length) of the horizontal synchronization signal. When a capacitor is used as the voltage holding circuit, the capacitor may have a charging / discharging time constant, and may not be fully charged if the charging time is too short. In order to avoid such a state, a plurality of periods of the horizontal synchronizing signal may be included in one cycle.
[0011]
Further, when the number of voltages included in the staircase waveform generated by the first gradation voltage generation circuit increases, the generation interval of the voltage generation control pulse also decreases, and the capacitor is charged as described above. It may not be possible. As another method for avoiding this, the first gradation voltage generation circuit divides the step-like gradation voltages into, for example, two and generates them at the same time, and correspondingly, the source control substrate has the same number (two). May be provided.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.
[0013]
First, referring to FIG. 1, this liquid crystal display device includes a TFT array substrate 10. On the TFT array substrate 10, source lines and gate lines are wired in a matrix, for example, and a transparent electrode and a TFT as a switching element are formed for each pixel surrounded by each line. May be publicly known, so that detailed description and illustration thereof are omitted here.
[0014]
A source control substrate 20 is connected to a source line side terminal of the TFT array substrate 10 via a flexible substrate 22 having a source driver 21 formed of an IC chip, and a gate line side terminal is also formed of an IC chip. The gate control board 30 is connected via a flexible board 32 having a gate driver 31.
[0015]
Note that COF (chip on film), TCP (tape carrier package), or the like is used for the flexible substrates 22 and 32, and these flexible substrates 22 and 32 are conceptually included in the respective control substrates 20 and 30. Shall be
[0016]
The source control board 20 is connected to the main control board 40 via a relay board 23 made of, for example, a flexible board, and the gate control board 30 is also connected to the main control board 40 via a relay board 33.
[0017]
On the main control board 40, a DC / DC circuit 41 as a power supply circuit, a first gradation voltage generation circuit 42, and a timing controller 43 are mounted. The DC / DC circuit 41 generates an on / off voltage (for example, + 18V, -5V) for gate driving from a single power supply of, for example, 3V supplied from the external system side via the input connector 401, and generates a gate control board. In addition, a source driving voltage (for example, +10 V) is generated and supplied to the first gradation voltage generation circuit 42.
[0018]
On the other hand, a second gradation voltage generation circuit 211 having a resistance ladder circuit 212 as shown in FIG. 2 is provided in the source driver 21 on the source control substrate 20 side.
[0019]
In this example, the second gradation voltage generation circuit 211 includes ten voltage input terminals T0 to T9, and from each of the gradation input voltages V0 'to V9', the gradation voltages V0 to 64 of the higher voltage side 64 gradations. V63 and gradation voltages V63 to V0 of 64 gradations on the low voltage side are generated and output to the source electrode of the TFT (not shown) of the TFT array substrate 10. For reference, FIG. 3 shows a correlation graph in which the vertical axis represents the input voltage and the horizontal axis represents the gradation level.
[0020]
The first gradation voltage generation circuit 42 on the side of the main control board 40 has a resistance ladder circuit 421 as shown in FIG. 4 and divides a voltage of, for example, +10 V supplied from the DC / DC circuit 41 to obtain 10 levels. Are generated and supplied to the second gradation voltage generation circuit 211. At this time, the voltage generation control pulse from the timing controller 43 is received, and the gradation input voltages V0 ′ to V9 ′ are received. V9 ′ is output as a step waveform (step-like gradation voltage). This will be described with reference to the block diagram of FIG. 5 and the timing chart of FIG.
[0021]
The timing controller 43 includes a reference clock shown in FIG. 6A and a horizontal synchronization (Hsync) signal shown in FIG. 6B among various signals supplied from the external system via the input connector 401. 6C, a voltage generation control pulse Cp shown in FIG. 6C is generated and given to the first gradation voltage generation circuit 42 at each time when one horizontal period (one frame) of the horizontal synchronization signal is divided by an integer. .
[0022]
For example, in the case of an XGA model (1024 × 768 pixels), the horizontal synchronization signal is about 20 μS. Therefore, if the first gradation voltage generation circuit 42 outputs ten gradation voltages, the timing controller 43 A voltage generation control pulse Cp is generated every 2 μS.
[0023]
The first gradation voltage generation circuit 42 has a waveform generation circuit 422 on the output side of the resistance ladder circuit 421, and changes the voltage dividing ratio of the resistance ladder circuit 421 every time the voltage generation control pulse Cp is input. Generate a staircase waveform that gradually increases or decreases. In this example, as shown in FIG. 6 (d), the gradation input is gradually increased in the order of V9 ′, V8 ′,..., V0 ′, and is a 10-step gradation input consisting of a step waveform selected at the pulse interval of the voltage generation control pulse Cp. A step-like gradation voltage Sv including the voltages V0 'to V9' is generated.
[0024]
Regarding the gray scale voltage, the main control board 40 transmits the staircase gray scale voltage Sv to the source control board 20 together with the voltage generation control pulse Cp. This power supply system may have two interfaces, one for the step-like gradation voltage Sv and one for the voltage generation control pulse Cp.
[0025]
Correspondingly, in the source driver 21 on the source control substrate 20 side, a gray scale voltage selection circuit 213 is provided in a stage preceding the second gray scale voltage generation circuit 211. For example, a multiplexer can be used for the gradation voltage selection circuit 213.
[0026]
Each time the grayscale voltage selection circuit 213 receives the voltage generation control pulse Cp, it sequentially switches its output side cyclically. As a result, the grayscale input voltages V0 ′ to V9 ′ included in the staircase grayscale voltage Sv are distributed to the corresponding voltage input terminals T0 to T9 of the second grayscale voltage generation circuit 211, respectively.
[0027]
By the way, as described above, when distributing each of the gradation input voltages V0 ′ to V9 ′ by the gradation voltage selection circuit 213, according to this example, the gradation input voltage is input to each voltage input terminal every 20 μS. Therefore, it is necessary to hold the gradation input voltage until the next gradation input voltage is input.
[0028]
Therefore, in this example, as shown in FIG. 8, a capacitor C for holding a voltage is connected between each input line from the gradation voltage selection circuit 213 to the voltage input terminals T0 to T9 and the ground. .
[0029]
When connecting a capacitor C to each input line, it is necessary to consider the charging / discharging time constant. As described above, assuming that the number of gradation input voltages to be generated is ten, in the case of the XGA model, one cycle (one period) of the voltage generation control pulse Cp is about 2 μS, but the resolution is higher than this. In the case of SXGA (1280 × 1024 pixels) or QXGA (2048 × 1534 pixels), one cycle of the voltage generation control pulse Cp may be about 0.5 μS.
[0030]
Taking the voltage input terminal T0 of the second gradation voltage generation circuit 211 as an example, the gradation input voltage output from the gradation voltage selection circuit 213 to the voltage input terminal T0 is V0 ′, and the voltage generation control pulse Cp is 1 Assuming that the period is t, the capacitance of the capacitor C is C1, and the switch resistance of the gradation voltage selection circuit 213 is R, the voltage Vx appearing at the voltage input terminal T0 is obtained by the following equation.
Vx = V0 '× (1-Exp- ^{t / RC1} )
[0031]
Here, assuming that t is 0.5 μS, V0 ′ is 9 V, C1 is 20 pF, and R is 5 KΩ, the above equation gives Vx = 8.94 V, and the capacitor C may not be able to be charged at 0.5 μS. There is. In addition, since the current supplied from the capacitor C is also consumed by the resistance ladder circuit 212 of the second gradation voltage generation circuit 211 and a final-stage amplifier (not shown), a sufficient charging time is required for the capacitor C. .
[0032]
Therefore, the present invention proposes that a plurality of periods (a plurality of periods) of the horizontal synchronization signal be one cycle in order to lengthen one cycle of the voltage generation control pulse Cp. FIG. 9 shows, as an example, a timing chart in a case where three cycles of the horizontal synchronizing signal Hsync are one cycle and the voltage generation control pulse Cp is generated ten times during this cycle. According to this, for example, if one cycle of the horizontal synchronization signal Hsync is 20 μS, one cycle of the voltage generation control pulse Cp can be 6 μS.
[0033]
Next, the above example corresponds to 6 bits, and the grayscale input voltage to the second grayscale voltage generation circuit 211 is set to 10 levels. However, when the 8-bit specification is used, the number of grayscale input voltages is increased from 10 levels. It is necessary to increase the number of stages to eighteen, and it is required to reduce one cycle of the voltage generation control pulse Cp to 1 / 1.8 from 6 bits.
[0034]
As described above, since the voltage holding capacitor C requires a sufficient charging time, for example, in the case of 8-bit specification, it is preferable to divide the grayscale input voltage into two systems and perform parallel processing.
[0035]
That is, when the grayscale input voltages generated by the first grayscale voltage generation circuit 42 are 18 stages of V0 ′ to V17 ′, the grayscale input voltages are divided into two groups, as shown in FIG. The first step waveform Sv1 includes the grayscale input voltages V0 'to V8', the second step waveform Sv2 includes the grayscale input voltages V9 'to V17', and the same timing as the voltage generation control pulse Cp. To the source control board 20. In this case, three power supply system interfaces are required.
[0036]
In response to this, the source driver 21 on the source control board 20 side is provided with two gradation voltage selection circuits 213a and 213b for the first step waveform and the second step waveform as shown in FIG. According to this, even in the case of the 8-bit specification, the period of the 6-bit time can be ensured for the voltage generation control pulse Cp.
[0037]
【The invention's effect】
As described above, according to the present invention, a plurality of gradation voltages are applied to the source control substrate connected to the TFT array substrate by the first gradation voltage generation circuit on the main control substrate side in a stepwise waveform. And the signals are transmitted in chronological order, and the staircase waveform is distributed by the gradation voltage selection circuit on the source control board side, and is applied to each input terminal of the second gradation voltage generation circuit on the source control board side. Accordingly, the number of interfaces for the power supply system, particularly for the gradation voltage, can be significantly reduced.
[0038]
Further, since the wiring on the source control substrate side is simplified, for example, a conventional six-layer substrate can be replaced with a four-layer substrate. Can be dealt with with a margin in design.
[Brief description of the drawings]
FIG. 1 is a schematic view showing components of a liquid crystal display device according to the present invention.
FIG. 2 is a circuit diagram showing a configuration of a second gradation voltage generation circuit on a source control substrate side.
FIG. 3 is a graph showing a relationship between an input voltage of the second gradation voltage generation circuit and a gradation level.
FIG. 4 is a circuit diagram showing a configuration of a first gradation voltage generation circuit on a main control board side.
FIG. 5 is a block diagram showing a timing controller and a first gradation voltage generation circuit on the main control board side.
FIG. 6 is a timing chart for explaining the operation of the present invention.
FIG. 7 is a block diagram showing a gradation voltage selection circuit provided on the source control substrate side.
FIG. 8 is a schematic diagram showing a voltage holding circuit provided on an input line of the second gradation voltage generation circuit.
FIG. 9 is a timing chart for explaining a method for extending one cycle of a voltage generation control pulse.
FIG. 10 is a staircase waveform diagram for explaining a preferred embodiment of the present invention corresponding to multi-bit operation.
FIG. 11 is a block diagram showing an example in which two gray scale voltage selection circuits are provided on the source control substrate side in response to the increase in the number of bits.
[Explanation of symbols]
Reference Signs List 10 TFT array substrate 20 Source control substrate 21 Source driver 211 Second gradation voltage generation circuit 213 Gradation voltage selection circuits 23, 33 Relay substrate 30 Gate control substrate 40 Main control substrate 41 DC / DC circuit 42 First gradation voltage generation Circuit 422 Waveform generation circuit 43 Timing controller

Claims (4)

A liquid crystal display panel including a TFT array substrate to which a gate control substrate and a source control substrate are connected; and a main control substrate connected to each of the control substrates. A gate drive voltage is supplied from the main control substrate to the gate control substrate. In the liquid crystal display device for driving the liquid crystal display panel by applying a gradation signal to the source control substrate,
The main control board includes a timing controller that outputs a voltage generation control pulse a plurality of times in each cycle of the predetermined period of the horizontal synchronization signal as one cycle, and outputs the voltage generation control pulse at a timing that is a fraction of the integer. A first gradation voltage generation circuit for generating a step-like gradation voltage including a voltage of a predetermined number of steps, wherein the main control board sends the step-like gradation voltage together with the voltage generation control pulse to the source control board. The regulated voltages are transmitted in chronological order,
The source control substrate includes a voltage input terminal equal to the number of steps of the step-like gradation voltage, and generates a predetermined number of gradation voltages from the input voltage and outputs the gradation voltage to the source electrode of the TFT array substrate. A two-gradation voltage generation circuit, and a gradation voltage selection circuit that selects each voltage included in the step-like gradation voltage by the voltage generation control pulse and distributes the voltage to the voltage input terminal. Characteristic liquid crystal display device. 2. The liquid crystal display device according to claim 1, wherein a voltage holding circuit including a capacitor is connected to a gradation voltage input line of the second gradation voltage generation circuit. 3. The liquid crystal display device according to claim 1, wherein the one cycle includes a plurality of periods of the horizontal synchronization signal. 4. The method according to claim 1, wherein the first grayscale voltage generation circuit generates a plurality of the stepwise grayscale voltages simultaneously, and the source control substrate includes a corresponding number of the grayscale voltage selection circuits. Or the liquid crystal display device according to 3.

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