JP2004260105A - Tape carrier for semiconductor device - Google Patents

Tape carrier for semiconductor device Download PDF

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Publication number
JP2004260105A
JP2004260105A JP2003051689A JP2003051689A JP2004260105A JP 2004260105 A JP2004260105 A JP 2004260105A JP 2003051689 A JP2003051689 A JP 2003051689A JP 2003051689 A JP2003051689 A JP 2003051689A JP 2004260105 A JP2004260105 A JP 2004260105A
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Prior art keywords
tape
thickness
tab tape
copper foil
insulating resin
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JP2003051689A
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Japanese (ja)
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JP3903931B2 (en
Inventor
Norihiro Ashizuka
紀尋 芦塚
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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Priority to JP2003051689A priority Critical patent/JP3903931B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a tape carrier for semiconductor devices with which a TAB tape can be easily bent while maintaining proper strength and whose package reliability is enhanced to contribute to miniaturization of the package with the reduced manufacturing cost. <P>SOLUTION: The TAB tape 10 is used by bending after a semiconductor chip 6 is loaded on a TAB tape 10 having two layers consisting of a polyimide tape 1 and a copper foil 3, or a TAB tape 10 having three layers consisting of a polyimide tape 1, an adhesive 2, and a copper foil 3. The tape carrier for semiconductor devices is constituted such that the thickness of an insulating resin 7 (solder resist) on the copper foil 3 positioned at an bending section 1A of the TAB tape 10 is formed thinner than the insulating resin 7 positioned at a non-bending section 1B to provide flexibility for easy bending, and the total rigidity of the polyimide tape 1 and the insulating resin 7 (solder resist) positioned at the bending section 1A is reduced to make bending easy. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップを実装するＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）テープ、特にポリイミドテープと銅箔を有する２層構成のＴＡＢテープ、あるいはポリイミドテープ、接着剤、および銅箔を有する３層構成のＴＡＢテープに、半導体チップを実装してＴＡＢテープを折り曲げ、ＴＡＢテープの底面に接続用のはんだボールを備えるＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型の半導体パッケージに仕上げる半導体装置用テープキャリアに関するものである。
【０００２】
【従来の技術】
最近、パソコン、高速デジタル・データ処理機器に使用される半導体装置とそのテープキャリアは、特に小型化、薄型化が要望されている。
【０００３】
図１０は、従来の技術により３層のＴＡＢテープ１０に半導体チップ６を実装した横断面を示している。
図１０において、３層のＴＡＢテープ１０は、ポリイミドテープ１の上に接着剤２を介して銅箔３を貼り付けて構成される。例えば通常は、ポリイミドテープ厚さは３０〜７５μｍ、接着剤厚さは１２〜２０μｍ、銅箔厚さは１５〜４０μｍの構成のものが使用されている。
ＴＡＢテープ１０に搭載する半導体チップ６を電気的に接続するために、銅箔３には、感光剤（ソルダーレジスト）を応用したホトリソグラフィ技術によって所定の電気配線（配線パターン）が形成される。
銅箔３の上には、電気配線（配線パターン）のために厚さ０．２〜１．５μｍのＡｕ／Ｎｉのめっき層４を有する。ＴＡＢテープ１０に搭載される半導体チップ６と銅箔３（配線パターン）の電気的な接続は、Ａｇペーストあるいははんだペースト等の導電性ペ一スト５を、１５０℃以上の高温で１０〜３０秒以上加熱することにより行われる。
銅箔３上には、電気的な絶縁を保持し、導電性ペースト５の流れを防止するために印刷等による絶縁樹脂７が設けられる。銅箔３の上に設ける絶縁樹脂７（ソルダーレジスト）の厚さは５〜５０μｍである。
３層のＴＡＢテープ１０は、ポリイミドテープ１の折り曲げない部分１Ｂにバイアホール１１と、ＴＡＢテープ１０の折り曲げる部分１Ａを折り曲げ易くするために開けたスリット穴１２を有する。
【０００４】
図１１は、図１０に示す従来の技術による半導体チップ６を実装したＴＡＢテープ１０を折り曲げた横断面を示している。
図１１において、半導体チップ６を実装するＴＡＢテープ１０は、少ないスペースに数多くの半導体チップ６を搭載して実装密度を向上させるために、一つの半導体パッケージ内に２個以上の半導体チップ６を搭載し、ＴＡＢテープ１０のほぼ真ん中を折り曲げて使用される。
ＴＡＢテープ１０は、２個以上の半導体チップ６を実装したのち、ＴＡＢテープ１０の真ん中を折り曲げて、モールド樹脂８により半導体パッケージの形状とし、バイアホール１１に外部接続用のはんだボール９を載せて半導体パッケージを完成させる。
ポリイミドテープ１を折り曲げ易くするため折り曲げる部分１Ａに開けたスリット穴１２には、ポリイミドテープ１のスリット穴１２の機械強度を確保するために、ポリイミドテープ１を折り曲げた後のスリット穴１２に埋め込み樹脂１３が塗布される。
【０００５】
従来の技術に関連する特許文献としては、つぎのものがある。
１）フレキシブル絶縁基板の導体パターンと交又する方向に切り欠き部を設け、切り欠き部から露出する導体パターンに保護用樹脂を塗布した折り曲げ部を有するフレキシブル絶縁基板がある（特許文献１参照）。
２）折り曲げ部分の絶縁ベース材の厚さを薄く形成したＴＡＢ用フィルムキャリアがある（特許文献２参照）。
３）絶縁基材上に設ける導体の孔位置に対応する部分に絶縁性薄膜合成樹脂を塗布したＴＡＢ用フィルムキャリアがある（特許文献３参照）。
４）銅を導体パターンとし、折り曲げ部のベースフイルムがスリットされているＴＡＢにおいて、折り曲げ部の外面または内面に樹脂を被覆するＴＡＢテープがある（特許文献４参照）。
５）絶縁フィルムに銅リードパターンを形成したＴＡＢ用テープキャリアにおいて、絶縁フィルムと銅リードに折り曲げ用のスリット穴を設け、スリット穴上の銅リードに絶縁フィルムより厚みが薄い可撓性樹脂保護被膜を形成したＴＡＢ用テープキャリアがある（特許文献５参照）。
６）ベースフィルムに折り曲げ用のスリット穴を設け、フィルム上の銅リード表面にＳｎめっきと可撓性樹脂被膜を施し、折り曲げ部の銅リード表面は可撓性樹脂被膜を設けてめっきを施さないＴＡＢ用テープキャリアがある（特許文献６参照）。
７）導体と接着剤と絶縁基材を有するフィルムキャリアにおいて、絶縁基材にあけたスリット孔位置に対応する部分の導体と接着剤を残して構成したＴＡＢ用テープキャリアがある（特許文献７参照）。
８）絶縁テープに導電パターンを形成したＴＡＢテープの折り曲げ予定部に溝を形成したＴＡＢ式電子部品がある（特許文献８参照）。
９）絶縁フィルムに形成された折り曲げ用の複数のスリットの内部に、各スリットの曲げ角度に応じた膜厚の保護樹脂を塗布したＴＡＢ用テープキャリアがある（特許文献９参照）。
１０）フレキシブル絶縁基板の折り曲げ部に切り欠き部を設け、切り欠き部から露出する導体パターンに保護用樹脂を形成したフレキシブル絶縁基板がある（特許文献１０参照）。
１１）支持フィルム上に導電性材料の配線と絶縁保護塗膜が施された配線板の屈曲部に、スリット状開口部がフィルムに形成され、スリット状開口部を横切る配線に、保護塗膜が被覆された柔軟性配線板がある（特許文献１１参照）。
１２）銅リード配線パターンが形成された絶縁フィルムに厚み調整用スリットを形成し、厚み調整用スリット近傍のソルダーレジスト層の層厚を薄くした電子部品実装用フィルムキャリアテープがある（特許文献１２参照）。
１３）フレキシブル絶縁基板の折り曲げ部に切り欠き部を設け、切り欠き部から露出する導体パターンに保護用樹脂を形成したフレキシブル絶縁基板がある（特許文献１３参照）。
１４）ストレス緩和用スリットの中央部に反りを抑制するための架橋手段を備えた可撓性フィルム接続基板がある（特許文献１４参照）。
【０００６】
【特許文献１】特開平２−１３２４１８号公報（第１−２頁、第１図）
【特許文献２】特開平４−９１４５０号公報（第１−２頁、第１図）
【特許文献３】特開平４−１６２５４２号公報（第１−２頁、第１図）
【特許文献４】特開平５−３２２８号公報（第１−２頁、第３図）
【特許文献５】特開平５−３１５４０３号公報（第１−２頁、第１図）
【特許文献６】特開平５−３２６６４３号公報（第２−３頁、第１図）
【特許文献７】特開平６−５６６１号公報（第１−２頁、第１図）
【特許文献８】特開平６−１４０４７４号公報（第３頁、第１図）
【特許文献９】特開平７−２９７２３５号公報（第３−４頁、第１図）
【特許文献１０】特開平９−２７４４４６号公報（第１−２頁、第１図）
【特許文献１１】特開平１１−２２０２４８号公報（第１−２頁、第１図）
【特許文献１２】特開２０００−１９５９０８号公報（第２−５頁、第２図）
【特許文献１３】特開２０００−２６１１３８号公報（第３−４頁、第１図）
【特許文献１４】特開２００１−２３７２８０号公報（第３−５頁、第１図）
【０００７】
【発明が解決しようとする課題】
しかし、従来のＴＡＢテープあるいは半導体装置用テープキャリアを用いた半導体装置によると、ＴＡＢテープに折り曲げ用のスリット穴を形成しているために、テープの製造コストが高くなるとともに、製造途中にＴＡＢテープのスリット穴の部分の銅箔が切れてしまい、半導体パッケージの組立て作業効率が低いという問題があった。
また、ＴＡＢテープに折り曲げ用のスリット穴が設けられているにも拘わらず、ＴＡＢテープを構成しているポリイミドテープ、接着剤、銅箔、銅箔上のソルダーレジスト（感光剤）、めっき層等の材料の剛性が大きいために、ＴＡＢテープの折り曲げ工程においてテープが折り曲げにくいという問題、あるいは無理に折り曲げるとテープが割れてしまうという現象が起きることがあった。
特に、銅箔と比べて、折り曲げ部分に位置する電気配線上のめっき層が比較的硬いために、ＴＡＢテープの折り曲げ時にめっき層が割れて、半導体パッケージの外観異常が発生し、信頼性が低下するという課題が残されていた。
【０００８】
それ故、本発明の目的は、ＴＡＢテープの折り曲げが容易で適正な強度を維持しつつ、半導体パッケージの信頼性を向上させて小型化に寄与し、しかも製造コストの廉価な半導体装置用テープキャリアを提供することにある。
【０００９】
【課題を解決するための手段】
本発明は、上記の目的を達成するため、ポリイミドテープと銅箔を有する２層のＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）テープ、あるいはポリイミドテープ、接着剤、および銅箔を有する３層のＴＡＢテープを、テープ長さ方向に折り曲げて用いる構成の半導体装置用テープキャリアにおいて、
前記２層あるいは３層のＴＡＢテープは、前記ＴＡＢテープの折り曲げる部分に位置する前記銅箔上の絶縁樹脂（ソルダーレジスト）の厚さを、前記ＴＡＢテープの折り曲げない部分に位置する前記銅箔上の絶縁樹脂の厚さよりも薄く形成して、前記ＴＡＢテープの折り曲げる部分に位置する前記絶縁樹脂に折り曲げ容易な柔軟性を付与するとともに、
前記ＴＡＢテープの折り曲げる部分に位置する前記ポリイミドテープと前記絶縁樹脂で合成される複合剛性を低減させることにより、
前記２層あるいは３層のＴＡＢテープの折り曲げを容易に構成したことを特徴とする半導体装置用テープキャリアを提供する。
【００１０】
また、本発明は、上記の目的を達成するために、前記２層あるいは３層のＴＡＢテープは、前記ポリイミドテープの折り曲げる部分に位置する前記銅箔上の絶縁樹脂の厚さを１〜１０μｍに形成し、前記ＴＡＢテープの折り曲げる部分にめっき層を有しない構成の半導体装置用テープキャリアを提供する。
【００１１】
また、本発明は、上記の目的を達成するために、前記２層あるいは３層のＴＡＢテープは、前記ＴＡＢテープの折り曲げる部分に位置する前記ポリイミドテープの樹脂厚さが５〜４０μｍ（好ましくは５〜３０μｍ）、前記接着剤厚さが３〜２０μｍ（好ましくは５〜１８μｍ）、前記銅箔厚さが５〜３０μｍ（好ましくは８〜２０μｍ）、前記銅箔上の絶縁樹脂の厚さが１〜１０μｍ（好ましくは３〜１０μｍ）に形成したことを特徴とする半導体装置用テープキャリアを提供する。
【００１２】
また、本発明は、上記の目的を達成するために、前記２層あるいは３層のＴＡＢテープは、前記ＴＡＢテープの折り曲げない部分に位置する前記ポリイミドテープの樹脂厚さが５〜５０μｍ（好ましくは１０〜４０μｍ）、前記接着剤厚さが３〜２０μｍ（好ましくは５〜１８μｍ）、前記銅箔厚さが５〜３０μｍ（好ましくは８〜２０μｍ）、前記銅箔上の絶縁樹脂の厚さが５〜５０μｍ（好ましくは５〜３０μｍ）に形成したことを特徴とする半導体装置用テープキャリアを提供する。
【００１３】
【発明の実施の形態】
図１は、本発明の第１の実施の形態による２層のＴＡＢテープ１０に半導体チップ６を実装した半導体装置用テープキャリアの横断面を示している。
図１において、ポリイミドテープ１と銅箔３を有する２層のＴＡＢテープ１０は、バイアホール１１を有し、ＴＡＢテープ１０の折り曲げる部分１Ａに位置する銅箔３（導体パターン）上の絶縁樹脂７（ソルダーレジスト）の厚さを、ＴＡＢテープ１０の折り曲げない部分１Ｂに位置する銅箔３（導体パターン）上の絶縁樹脂７（ソルダーレジスト）の厚さよりも薄く形成して、ＴＡＢテープ１０の折り曲げる部分１Ａに位置する絶縁樹脂７（ソルダーレジスト）に折り曲げ容易な柔軟性を付与するとともに、ＴＡＢテープ１０の折り曲げる部分１Ａに位置するポリイミドテープ１と絶縁樹脂７（ソルダーレジスト）で合成される複合剛性を低減させて、折り曲げ容易な２層のＴＡＢテープ１０を構成している。
【００１４】
図１に示したＴＡＢテープ１０の場合、ポリイミドテープ１の厚さが５〜５０μｍ（好ましくは１０〜４０μｍ）、銅箔３の厚さが５〜３０μｍ（好ましくは８〜２０μｍ）、折り曲げる部分１Ａに位置する絶縁樹脂７の厚さが１〜１０μｍ（好ましくは３〜１０μｍ）、折り曲げない部分１Ｂに位置する絶縁樹脂７の厚さは、特に制限されないが厚さが５〜５０μｍ（好ましくは５〜３０μｍ）に形成される。
【００１５】
図１のＴＡＢテープ１０には、半導体チップ６が搭載される。ＴＡＢテープ１０に搭載する半導体チップ６を電気的に接続するために、銅箔３には、感光剤（ソルダーレジスト）を応用したホトリソグラフィ技術によって所定の電気配線（配線パターン）が形成される。
ＴＡＢテープ１０に搭載される半導体チップ６と銅箔３（配線パターン）の電気的な接続は、Ａｇペーストあるいははんだペースト等の導電性ペースト５を１５０℃以上の高温で１０〜３０秒以上加熱することにより行われる。銅箔３上の絶縁樹脂７は、電気的な絶縁を保持し、導電性ペースト５の流れを防止するために印刷等により設けられる。
【００１６】
図２は、本発明の第１の実施の形態による２層のＴＡＢテープ１０に半導体チップ６を実装した半導体装置用テープキャリアを折り曲げた横断面を示している。
図２において、半導体チップ６を実装するＴＡＢテープ１０は、少ないスペースに数多くの半導体チップ６を搭載して実装密度を向上させるために、一つの半導体パッケージ内に２個以上の半導体チップ６を搭載し、ＴＡＢテープ１０のほぼ真ん中を折り曲げて使用される。
図２のＴＡＢテープ１０は、折り曲げる部分１Ａに位置する銅箔３上に形成される絶縁樹脂７（ソルダーレジスト）の厚さが、折り曲げない部分１Ｂに位置する銅箔３上の絶縁樹脂７（ソルダーレジスト）の厚さよりも薄く形成されて、折り曲げる部分１Ａに位置する絶縁樹脂７（ソルダーレジスト）に折り曲げ容易な柔軟性が付与されており、この結果、ポリイミドテープ１と絶縁樹脂７（ソルダーレジスト）の複合剛性が低減され、ＴＡＢテープ１０の折り曲げが容易に行える。
ＴＡＢテープ１０は、２個以上の半導体チップ６を実装したのち、ＴＡＢテープ１０の真ん中を折り曲げて、モールド樹脂８により半導体パッケージの形状とし、バイアホール１１に外部接続用のはんだボール９を載せて半導体パッケージが完成される。
【００１７】
図３は、本発明の第２の実施の形態による３層のＴＡＢテープ１０に半導体チップ６を実装した半導体装置用テープキャリアの横断面を示している。
図３において、ポリイミドテープ１、接着剤２、銅箔３を有する３層のＴＡＢテープ１０は、バイアホール１１を有し、ＴＡＢテープ１０の折り曲げる部分１Ａに位置する銅箔３（導体パターン）上の絶縁樹脂７（ソルダーレジスト）の厚さを、ＴＡＢテープ１０の折り曲げない部分１Ｂに位置する銅箔３（導体パターン）上の絶縁樹脂７（ソルダーレジスト）の厚さよりも薄く形成して、ＴＡＢテープ１０の折り曲げる部分１Ａに位置する絶縁樹脂７（ソルダーレジスト）に折り曲げ容易な柔軟性を付与するとともに、ＴＡＢテープ１０の折り曲げる部分１Ａに位置するポリイミドテープ１、接着剤２、絶縁樹脂７（ソルダーレジスト）で合成される複合剛性を低減させて、折り曲げ容易な３層のＴＡＢテープ１０を構成している。
【００１８】
図３に示したＴＡＢテープ１０の場合、ポリイミドテープ１の厚さが５〜５０μｍ（好ましくは１０〜４０μｍ）、接着剤２の厚さが３〜２０μｍ（好ましくは５〜１８μｍ）、銅箔３の厚さが５〜３０μｍ（好ましくは８〜２０μｍ）、折り曲げる部分１Ａに位置する絶縁樹脂７の厚さが１〜１０μｍ（好ましくは３〜１０μｍ）、折り曲げない部分１Ｂに位置する絶縁樹脂７の厚さは、特に制限されないが厚さが５〜５０μｍ（好ましくは５〜３０μｍ）に形成される。
【００１９】
図３のＴＡＢテープ１０には、半導体チップ６が搭載される。ＴＡＢテープ１０に搭載する半導体チップ６を電気的に接続するために、銅箔３には、感光剤（ソルダーレジスト）を応用したホトリソグラフィ技術によって所定の電気配線（配線パターン）が形成される。
ＴＡＢテープ１０に搭載される半導体チップ６と銅箔３（配線パターン）の電気的な接続は、Ａｇペーストあるいははんだペースト等の導電性ペースト５を１５０℃以上の高温で１０〜３０秒以上加熱することにより行われる。銅箔３上の絶縁樹脂７は、電気的な絶縁を保持し、導電性ペースト５の流れを防止するために印刷等により設けられる。
【００２０】
図４は、本発明の第２の実施の形態による３層のＴＡＢテープ１０に半導体チップ６を実装した半導体装置用テープキャリアを折り曲げた横断面を示している。
図４において、半導体チップ６を実装するＴＡＢテープ１０は、少ないスペースに数多くの半導体チップ６を搭載して実装密度を向上させるために、一つの半導体パッケージ内に２個以上の半導体チップ６を搭載し、ＴＡＢテープ１０のほぼ真ん中を折り曲げて使用される。
図４のＴＡＢテープ１０は、また、折り曲げる部分１Ａに位置する銅箔３上に形成される絶縁樹脂７（ソルダーレジスト）の厚さが、折り曲げない部分１Ｂに位置する銅箔３上の絶縁樹脂７（ソルダーレジスト）の厚さよりも薄く形成されて、折り曲げる部分１Ａに位置する絶縁樹脂７（ソルダーレジスト）に折り曲げ容易な柔軟性が付与されており、この結果、ポリイミドテープ１と接着剤２と絶縁樹脂７（ソルダーレジスト）の複合剛性が低減され、ＴＡＢテープ１０の折り曲げが容易に行える。
ＴＡＢテープ１０は、２個以上の半導体チップ６を実装したのち、ＴＡＢテープ１０の真ん中を折り曲げて、モールド樹脂８により半導体パッケージの形状とし、バイアホール１１に外部接続用のはんだボール９を載せて半導体パッケージが完成される。
【００２１】
図５は、本発明の第３の実施の形態による２層のＴＡＢテープ１０に半導体チップ６を実装した半導体装置用テープキャリアの横断面を示している。
図５において、ポリイミドテープ１と銅箔３から構成される２層のＴＡＢテープ１０は、バイアホール１１を有する。ＴＡＢテープ１０は、ＴＡＢテープ１０の折り曲げる部分１Ａに位置するポリイミドテープ１の厚さを、ＴＡＢテープ１０の折り曲げない部分１Ｂに位置するポリイミドテープ１の厚さよりも薄く形成して、折り曲げる部分１Ａに位置するポリイミドテープ１を折り曲げ易く構成している。
【００２２】
図５のＴＡＢテープ１０は、さらにＴＡＢテープ１０の折り曲げる部分１Ａに位置する銅箔３（導体パターン）上の絶縁樹脂７（ソルダーレジスト）の厚さを、ＴＡＢテープ１０の折り曲げない部分１Ｂに位置する銅箔３（導体パターン）上の絶縁樹脂７（ソルダーレジスト）の厚さよりも薄く形成して、ＴＡＢテープ１０の折り曲げる部分１Ａに位置する絶縁樹脂７（ソルダーレジスト）に折り曲げ容易な柔軟性を付与するとともに、ＴＡＢテープ１０の折り曲げる部分１Ａに位置するポリイミドテープ１と絶縁樹脂７（ソルダーレジスト）で合成される複合剛性を低減させて、折り曲げ容易なＴＡＢテープ１０を構成している。
【００２３】
図５に示したＴＡＢテープ１０の場合、折り曲げる部分１Ａのポリイミドテープ１の厚さが５〜４０μｍ（好ましくは５〜３０μｍ）、銅箔３の厚さが５〜３０μｍ（好ましくは８〜２０μｍ）であり、折り曲げない部分１Ｂのポリイミドテープ１の厚さが５〜５０μｍ（好ましくは１０〜４０μｍ）、銅箔３の厚さが５〜３０μｍ（好ましくは８〜２０μｍ）に形成される。
また、ＴＡＢテープ１０の折り曲げる部分１Ａに位置する銅箔３上に形成する絶縁樹脂７（ソルダーレジスト）の厚さ１〜１０μｍ（好ましくは３〜１０μｍ）は、ＴＡＢテープ１０の折り曲げない部分１Ｂに位置する銅箔３上の絶縁樹脂７（ソルダーレジスト）の厚さ５〜５０μｍ（好ましくは５〜３０μｍ）よりも薄く構成することにより、ＴＡＢテープ１０の折り曲げる部分１Ａに位置するポリイミドテープ１と絶縁樹脂７（ソルダーレジスト）の複合剛性を低減させて、ＴＡＢテープ１０に折り曲げ容易な柔軟性を付与させている。
【００２４】
図５のＴＡＢテープ１０には、半導体チップ６が搭載される。ＴＡＢテープ１０に搭載する半導体チップ６を電気的に接続するために、銅箔３には、感光剤（ソルダーレジスト）を応用したホトリソグラフィ技術によって所定の電気配線（配線パターン）が形成される。
ＴＡＢテープ１０に搭載される半導体チップ６と銅箔３（配線パターン）の電気的な接続は、Ａｇペーストあるいははんだペースト等の導電性ペースト５を１５０℃以上の高温で１０〜３０秒以上加熱することにより行われる。銅箔３上の絶縁樹脂７は、電気的な絶縁を保持し、導電性ペースト５の流れを防止するために印刷等の方法により設けられる。
【００２５】
図６は、本発明の第３の実施の形態による２層のＴＡＢテープ１０に半導体チップ６を実装した半導体装置用テープキャリアを折り曲げた横断面を示している。
図６において、半導体チップ６を実装するＴＡＢテープ１０は、少ないスペースに数多くの半導体チップ６を搭載して実装密度を向上させるために、一つの半導体パッケージ内に２個以上の半導体チップ６を搭載し、ＴＡＢテープ１０のほぼ真ん中を折り曲げて使用される。
図６のＴＡＢテープ１０は、折り曲げる部分１Ａに位置するポリイミドテープ１の厚さが、折り曲げない部分１Ｂの厚さよりも薄く形成されてポリイミドテープ１が折り曲げ易くなっている。また、折り曲げる部分１Ａに位置する銅箔３上に形成される絶縁樹脂７（ソルダーレジスト）の厚さが、折り曲げない部分１Ｂに位置する銅箔３上の絶縁樹脂７（ソルダーレジスト）の厚さよりも薄く形成されて、折り曲げる部分１Ａに位置する絶縁樹脂７（ソルダーレジスト）に折り曲げ容易な柔軟性が付与されており、この結果、ポリイミドテープ１と絶縁樹脂７（ソルダーレジスト）の複合剛性が低減され、ＴＡＢテープ１０の折り曲げが容易に行える。
ＴＡＢテープ１０は、２個以上の半導体チップ６を実装したのち、ＴＡＢテープ１０の真ん中を折り曲げて、モールド樹脂８により半導体パッケージの形状とし、バイアホール１１に外部接続用のはんだボール９を載せて半導体パッケージが完成される。
【００２６】
図７は、本発明の第４の実施の形態による３層のＴＡＢテープ１０に半導体チップ６を実装した半導体装置用テープキャリアの横断面を示している。
図７において、ポリイミドテープ１の上に、銅箔３を接着剤２により貼り付けて３層のＴＡＢテープ１０が構成される。ＴＡＢテープ１０は、バイアホール１１を有し、ＴＡＢテープ１０の折り曲げる部分１Ａに位置するポリイミドテープ１の厚さ、および銅箔３上に形成する絶縁樹脂７（ソルダーレジスト）の厚さを、ＴＡＢテープ１０の折り曲げない部分１Ｂに位置するポリイミドテープ１の厚さ、および銅箔３上に形成する絶縁樹脂７（ソルダーレジスト）の厚さよりも薄く形成して、折り曲げる部分１Ａに位置するポリイミドテープ１および銅箔３上に形成する絶縁樹脂７（ソルダーレジスト）を折り曲げ易く構成している。
【００２７】
図７に示したＴＡＢテープ１０の場合、折り曲げる部分１Ａのポリイミドテープ１の厚さが５〜４０μｍ（好ましくは５〜３０μｍ）、接着剤２の厚さが３〜２０μｍ（好ましくは５〜１８μｍ）、銅箔３の厚さが５〜３０μｍ（好ましくは８〜２０μｍ）であり、折り曲げない部分１Ｂのポリイミドテープ１の厚さが５〜５０μｍ（好ましくは１０〜４０μｍ）、接着剤２の厚さが３〜２０μｍ（好ましくは５〜１８μｍ）、銅箔３の厚さが５〜３０μｍ（好ましくは８〜２０μｍ）に形成される。
また、ＴＡＢテープ１０の折り曲げる部分１Ａに位置する銅箔３上に形成する絶縁樹脂７（ソルダーレジスト）の厚さ１〜１０μｍ（好ましくは３〜１０μｍ）は、ＴＡＢテープ１０の折り曲げない部分１Ｂに位置する銅箔３上の絶縁樹脂７（ソルダーレジスト）の厚さ５〜５０μｍ（好ましくは５〜３０μｍ）よりも薄く構成することにより、ＴＡＢテープ１０の折り曲げる部分１Ａに位置するポリイミドテープ１、接着剤２、絶縁樹脂７（ソルダーレジスト）で合成される複合剛性を低減させて、ＴＡＢテープ１０に折り曲げ容易な柔軟性を付与させている。
【００２８】
図７のＴＡＢテープ１０には、半導体チップ６が搭載される。ＴＡＢテープ１０に搭載する半導体チップ６を電気的に接続するために、銅箔３には、感光剤（ソルダーレジスト）を応用したホトリソグラフィ技術によって所定の電気配線（配線パターン）が形成される。
ＴＡＢテープ１０に搭載した半導体チップ６と銅箔３（配線パターン）の電気的な接続は、Ａｇペーストあるいははんだペースト等の導電性ペースト５を１５０℃以上の高温で１０〜３０秒以上加熱することにより行われる。銅箔３上の絶縁樹脂７は、電気的な絶縁を保持し、導電性ペースト５の流れを防止するために印刷等の方法により設けられる。
【００２９】
図８は、本発明の第４の実施の形態による３層のＴＡＢテープ１０に半導体チップ６を実装した半導体装置用テープキャリアを折り曲げた横断面を示している。
図８において、半導体チップ６を実装するＴＡＢテープ１０は、少ないスペースに数多くの半導体チップ６を搭載して実装密度を向上させるために、一つの半導体パッケージ内に２個以上の半導体チップ６を搭載し、ＴＡＢテープ１０のほぼ真ん中を折り曲げて使用される。
図８のＴＡＢテープ１０は、折り曲げる部分１Ａに位置するポリイミドテープ１の厚さが、折り曲げない部分１Ｂの厚さよりも薄く形成されてポリイミドテープ１が折り曲げ易くなっている。また、折り曲げる部分１Ａに位置する銅箔３上に形成される絶縁樹脂７（ソルダーレジスト）の厚さが、折り曲げない部分１Ｂに位置する銅箔３上の絶縁樹脂７（ソルダーレジスト）の厚さよりも薄く形成されて、折り曲げる部分１Ａに位置する絶縁樹脂７（ソルダーレジスト）に折り曲げ容易な柔軟性が付与されており、この結果、ポリイミドテープ１と接着剤２と絶縁樹脂７（ソルダーレジスト）の複合剛性が低減され、ＴＡＢテープ１０の折り曲げが容易に行える。
ＴＡＢテープ１０は、２個以上の半導体チップ６を実装したのち、ＴＡＢテープ１０の真ん中を折り曲げて、モールド樹脂８により半導体パッケージの形状とし、バイアホール１１に外部接続用のはんだボール９を載せて半導体パッケージが完成される。
【００３０】
図１，図３，図５，図７に示した本発明の実施の形態のＴＡＢテープ１０においては、ＴＡＢテープ１０の折り曲げない部分１Ｂの銅箔３による電気配線（配線パターン）に、電気接続に必要なＡｕまたはＡｕ／Ｎｉ等のめっき層（図示省略）が、めっき液に浸して０．２〜１．５μｍの厚さで設けられ、一方、ＴＡＢテープ１０の折り曲げる部分１Ａには、めっき層が形成されないように構成されている。
銅箔３への電気配線（配線パターン）の形成に当たり、ＴＡＢテープ１０の折り曲げる部分１Ａの銅箔３（配線パターン）上にめっき層が施されないようにするため、めっき工程前に、折り曲げる部分１Ａの銅箔３に柔軟性の薄い樹脂（図示省略）を印刷または塗布して、柔軟な樹脂の下面の銅箔３（配線パターン）をめっき液から保護することにより、配線パターンにめっき層を施さないようにするとともに、柔軟な樹脂に折り曲げる部分１Ａの機械的な強度を補う役割を担わせている。なお、柔軟性の薄い樹脂は、折り曲げる部分１Ａの片面（ポリイミドテープ１の表面）だけでなく、折り曲げる部分１Ａの背面（ポリイミドテープ１の裏面）にも、印刷または塗布して設けることにより、ポリイミドテープ１の両面に柔軟性の薄い樹脂を設けることができる。
【００３１】
図９は、本発明の実施の形態による半導体装置用テープキャリアの構成材厚さと曲げ形状合格率の関係を示す特性図である。
図９のテープキャリアの構成は、図１に示したテープキャリア（折り曲げる部分１Ａに位置するポリイミドテープ１の厚さ５〜５０μｍ、銅箔３の厚さ５〜３０μｍ、絶縁樹脂７の厚さ１〜１０μｍに形成したＴＡＢテープ）において、ソルダーレジスト（絶縁樹脂７）の厚さとして、折り曲げない部分１Ｂのソルダーレジストの厚さを５〜５０μｍに形成し、折り曲げる部分１Ａのソルダーレジストの厚さを、各々、５μｍ、１０μｍ、２０μｍ、３０μｍ、４０μｍに形成した試料（試料数ｎは、各々４個、合計ｎ＝２０個のテープキャリア）を用いて測定したものであり、各々の試料を規定の製造ラインで１回だけ折り曲げて、試料が折り曲げられた試料を合格とし、折り曲げられない試料を不合格として判定した。
【００３２】
図９によると、曲げ形状合格率（％）は、ソルダーレジスト厚さ５μｍと１０μｍの試料は１００％合格、ソルダーレジスト厚さ２０μｍの試料は４０％合格であるのに対して、ソルダーレジスト厚さ３０μｍと４０μｍの試料は、合格率がほぼ０％であることが分かる。
また、ソルダーレジスト厚さ５μｍと１０μｍの試料における折り曲げる部分の樹脂の割れ不良、欠け不良は見られなかった。
図９の特性図から明らかなように、本発明の実施の形態のテープキャリアの折り曲げ部に位置する銅箔３（導体パターン）上のソルダーレジスト厚さは、１〜１５μｍ、望ましくは５〜１０μｍが最適であることが解明された。
【００３３】
図９に示した特性図を補う試料の測定のために、図７に示した実施の形態のテープキャリアとして、
折り曲げない部分１Ｂのポリイミドテープ１の厚さ２０〜４０μｍよりも、折り曲げる部分１Ａに位置するポリイミドテープ１の厚さを１０〜３０μｍと薄く形成し、また、銅箔３に形成された配線パターン上の折り曲げない部分１Ｂに位置する絶縁樹脂７（ソルダーレジスト）の厚さ２０〜３０μｍよりも、折り曲げる部分１Ａに位置する銅箔３に形成された配線パターン上の絶縁樹脂７（ソルダーレジスト）の厚さを５〜１０μｍと薄く形成するテープキャリアにおいて、ソルダーレジスト（絶縁樹脂７）の厚さとして、図９に示した５種類（ソルダーレジスト厚さ、５μｍ、１０μｍ、２０μｍ、３０μｍ、４０μｍの試料）の場合の各試料のテープキャリアについて、その特性を測定した。
その結果、折り曲げる部分１Ａのポリイミドテープ１の厚さ、絶縁樹脂７（ソルダーレジスト）の厚さを薄く形成した場合の曲げ形状合格率（％）は、図９の特性図とほぼ同様の特性を示すことが分かった。
【００３４】
【発明の効果】
本発明の半導体装置用テープキャリアによると、２層あるいは３層のＴＡＢテープの折り曲げる部分に位置する銅箔上の絶縁樹脂の厚さを、折り曲げない部分に位置する絶縁樹脂の厚さよりも薄く形成して折り曲げ容易な柔軟性を付与するとともに、折り曲げる部分に位置するポリイミドテープと絶縁樹脂により合成される複合剛性を低減させているから、三者の相乗作用により極めて折り曲げ易い２層あるいは３層のＴＡＢテープ構成の半導体装置用テープキャリアを提供することができる。
【００３５】
本発明の２層あるいは３層のＴＡＢテープの半導体装置用テープキャリアによると、ＴＡＢテープに折り曲げ用のスリット穴を形成していないので、製造途中にＴＡＢテープの銅箔がスリット穴の部分から切れてしまうという問題は起こらないから、半導体パッケージの組立て作業効率を高めることができる。
しかも、折り曲げ部分に位置する電気配線上にめっき層を形成することなく、折り曲げる部分のＴＡＢテープを構成しているポリイミドテープ、接着剤、銅箔、銅箔上の絶縁樹脂などによる複合剛性を低めに保持してＴＡＢテープの適正な強度を維持しているから、ＴＡＢテープの１８０度の折り曲げが容易になり、ＴＡＢテープの斜めの折り曲げなど、自由な角度の曲げと、折り畳みが可能であるとともに、折り曲げ時のめっき層の割れによる半導体パッケージの外観異常発生の問題は全く一掃され、高密度の半導体パッケージに仕上げることが実現して半導体装置の高密度実装に著しく寄与することができる。
【００３６】
このように本発明の半導体装置用テープキャリアは、ＴＡＢテープの折り曲げが容易で、製造コストの廉価な半導体装置用テープキャリアを提供でき、この結果、小型化、薄型化が要望されているパソコン、高速デジタル・データ処理機器に使用される半導体パッケージの信頼性の向上と小型化に貢献できるという効果が得れらる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態による２層のＴＡＢテープに半導体チップを実装した半導体装置用テープキャリアの横断面を示す説明図である。
【図２】本発明の第１の実施の形態による２層のＴＡＢテープに半導体チップを実装した半導体装置用テープキャリアを折り曲げた横断面を示す説明図である。
【図３】本発明の第２の実施の形態による３層のＴＡＢテープに半導体チップを実装した半導体装置用テープキャリアの横断面を示す説明図である。
【図４】本発明の第２の実施の形態による３層のＴＡＢテープに半導体チップを実装した半導体装置用テープキャリアを折り曲げた横断面を示す説明図である。
【図５】本発明の第３の実施の形態による２層のＴＡＢテープに半導体チップを実装した半導体装置用テープキャリアの横断面を示す説明図である。
【図６】本発明の第３の実施の形態による２層のＴＡＢテープに半導体チップを実装した半導体装置用テープキャリアを折り曲げた横断面を示す説明図である。
【図７】本発明の第４の実施の形態による３層のＴＡＢテープに半導体チップを実装した半導体装置用テープキャリアの横断面を示す説明図である。
【図８】本発明の第４の実施の形態による３層のＴＡＢテープに半導体チップを実装した半導体装置用テープキャリアを折り曲げた横断面を示す説明図である。
【図９】本発明の実施の形態による半導体装置用テープキャリアの構成材厚さと曲げ形状合格率の関係を示す特性図である。
【図１０】従来の技術により３層のＴＡＢテープに半導体チップを実装した横断面を示す説明図である。
【図１１】従来の技術による半導体チップを実装した３層のＴＡＢテープを折り曲げた横断面を示す説明図である。
【符号の説明】
１ ポリイミドテープ
１Ａ 折り曲げる部分
１Ｂ 折り曲げない部分
２ 接着剤
３ 銅箔（導体パターン）
４ めっき層
５ 導電性ペ一スト
６ 半導体チップ
７ 絶縁樹脂（ソルダーレジスト）
８ モールド樹脂
９ はんだボール
１０ ＴＡＢテープ
１１ バイアホール
１２ スリット穴
１３ 埋め込み樹脂[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a TAB (Tape Automated Bonding) tape for mounting a semiconductor chip, in particular, a two-layer TAB tape having a polyimide tape and a copper foil, or a three-layer TAB tape having a polyimide tape, an adhesive, and a copper foil. The present invention relates to a tape carrier for a semiconductor device for mounting a semiconductor chip, bending a TAB tape, and finishing a BGA (Ball Grid Array) type semiconductor package having solder balls for connection on the bottom surface of the TAB tape.
[0002]
[Prior art]
Recently, semiconductor devices used in personal computers and high-speed digital data processing equipment and their tape carriers are required to be particularly small and thin.
[0003]
FIG. 10 shows a cross section in which a semiconductor chip 6 is mounted on a three-layer TAB tape 10 by a conventional technique.
In FIG. 10, a three-layer TAB tape 10 is configured by attaching a copper foil 3 on a polyimide tape 1 via an adhesive 2. For example, usually, a polyimide tape having a thickness of 30 to 75 μm, an adhesive thickness of 12 to 20 μm, and a copper foil thickness of 15 to 40 μm is used.
In order to electrically connect the semiconductor chips 6 mounted on the TAB tape 10, predetermined electric wiring (wiring pattern) is formed on the copper foil 3 by a photolithography technique using a photosensitive agent (solder resist).
An Au / Ni plating layer 4 having a thickness of 0.2 to 1.5 μm is provided on the copper foil 3 for electric wiring (wiring pattern). Electrical connection between the semiconductor chip 6 mounted on the TAB tape 10 and the copper foil 3 (wiring pattern) is performed by applying a conductive paste 5 such as an Ag paste or a solder paste at a high temperature of 150 ° C. or more for 10 to 30 seconds. The above is performed by heating.
An insulating resin 7 is provided on the copper foil 3 by printing or the like to maintain electrical insulation and prevent the flow of the conductive paste 5. The thickness of the insulating resin 7 (solder resist) provided on the copper foil 3 is 5 to 50 μm.
The three-layer TAB tape 10 has a via hole 11 in a non-bending portion 1B of the polyimide tape 1 and a slit hole 12 formed to make the bending portion 1A of the TAB tape 10 easier to bend.
[0004]
FIG. 11 shows a cross section obtained by bending the TAB tape 10 on which the semiconductor chip 6 according to the conventional technique shown in FIG. 10 is mounted.
In FIG. 11, the TAB tape 10 on which the semiconductor chips 6 are mounted has two or more semiconductor chips 6 mounted in one semiconductor package in order to increase the mounting density by mounting many semiconductor chips 6 in a small space. Then, the middle of the TAB tape 10 is bent and used.
After mounting two or more semiconductor chips 6 on the TAB tape 10, the center of the TAB tape 10 is bent to form a semiconductor package with the mold resin 8, and the solder balls 9 for external connection are placed in the via holes 11. Complete the semiconductor package.
In order to ensure the mechanical strength of the slit hole 12 of the polyimide tape 1, a resin embedded in the slit hole 12 after bending the polyimide tape 1 is inserted into a slit hole 12 formed in the bent portion 1 </ b> A to make the polyimide tape 1 easier to bend. 13 is applied.
[0005]
Patent documents related to the prior art include the following.
1) There is a flexible insulating substrate having a cutout portion provided in a direction intersecting with the conductor pattern of the flexible insulating substrate, and having a bent portion obtained by applying a protective resin to the conductor pattern exposed from the cutout portion (see Patent Document 1). .
2) There is a film carrier for TAB in which the thickness of the insulating base material at the bent portion is reduced (see Patent Document 2).
3) There is a TAB film carrier in which an insulating thin film synthetic resin is applied to a portion corresponding to a hole position of a conductor provided on an insulating base material (see Patent Document 3).
4) In a TAB in which copper is used as a conductive pattern and a base film of a bent portion is slit, there is a TAB tape that coats a resin on an outer surface or an inner surface of the bent portion (see Patent Document 4).
5) In a TAB tape carrier in which a copper lead pattern is formed on an insulating film, a slit hole for bending is formed in the insulating film and the copper lead, and the copper lead on the slit hole has a thinner flexible resin protective coating than the insulating film. (See Patent Document 5).
6) A slit hole for bending is provided in the base film, Sn plating and a flexible resin film are applied to the surface of the copper lead on the film, and the copper lead surface of the bent portion is provided with a flexible resin film and is not plated. There is a TAB tape carrier (see Patent Document 6).
7) In a film carrier having a conductor, an adhesive, and an insulating base material, there is a TAB tape carrier configured to leave a portion of the conductor and the adhesive corresponding to the position of the slit hole formed in the insulating base material (see Patent Document 7). ).
8) There is a TAB-type electronic component in which a groove is formed in a portion to be bent of a TAB tape in which a conductive pattern is formed on an insulating tape (see Patent Document 8).
9) There is a TAB tape carrier in which a protective resin having a film thickness corresponding to the bending angle of each slit is applied inside a plurality of bending slits formed in the insulating film (see Patent Document 9).
10) There is a flexible insulating substrate in which a notch is provided in a bent portion of a flexible insulating substrate and a protective resin is formed on a conductor pattern exposed from the notch (see Patent Document 10).
11) A slit-shaped opening is formed in the film at the bent portion of the wiring board in which the wiring of the conductive material and the insulating protective coating are applied on the support film, and the protective coating is formed on the wiring crossing the slit-shaped opening. There is a coated flexible wiring board (see Patent Document 11).
12) There is a film carrier tape for mounting electronic components in which a slit for adjusting thickness is formed in an insulating film on which a copper lead wiring pattern is formed, and a layer thickness of a solder resist layer in the vicinity of the slit for adjusting thickness is reduced. ).
13) There is a flexible insulating substrate in which a notch is provided in a bent portion of a flexible insulating substrate and a protective resin is formed on a conductor pattern exposed from the notch (see Patent Document 13).
14) There is a flexible film connection substrate provided with a bridging means for suppressing warpage at the center of the stress relaxation slit (see Patent Document 14).
[0006]
[Patent Document 1] Japanese Patent Application Laid-Open No. 2-132418 (Page 1-2, FIG. 1)
[Patent Document 2] JP-A-4-91450 (page 1-2, FIG. 1)
[Patent Document 3] Japanese Patent Application Laid-Open No. 4-162542 (page 1-2, FIG. 1)
[Patent Document 4] JP-A-5-3228 (page 1-2, FIG. 3)
[Patent Document 5] JP-A-5-315403 (Page 1-2, FIG. 1)
[Patent Document 6] Japanese Patent Application Laid-Open No. 5-326543 (page 2-3, FIG. 1)
[Patent Document 7] JP-A-6-5661 (page 1-2, FIG. 1)
[Patent Document 8] JP-A-6-140474 (page 3, FIG. 1)
[Patent Document 9] JP-A-7-297235 (page 3-4, FIG. 1)
[Patent Document 10] Japanese Patent Application Laid-Open No. 9-274446 (page 1-2, FIG. 1)
[Patent Document 11] JP-A-11-220248 (page 1-2, FIG. 1)
[Patent Document 12] Japanese Patent Application Laid-Open No. 2000-195908 (Pages 2-5, FIG. 2)
[Patent Document 13] Japanese Patent Application Laid-Open No. 2000-261138 (Page 3-4, FIG. 1)
[Patent Document 14] Japanese Patent Application Laid-Open No. 2001-237280 (Page 3-5, FIG. 1)
[0007]
[Problems to be solved by the invention]
However, according to a conventional TAB tape or a semiconductor device using a tape carrier for a semiconductor device, since a slit hole for bending is formed in the TAB tape, the manufacturing cost of the tape increases, and the TAB tape is in the middle of manufacturing. In this case, the copper foil in the slit hole portion is cut off, and there is a problem that the efficiency of assembling the semiconductor package is low.
In addition, despite the fact that the TAB tape has slit holes for bending, a polyimide tape, an adhesive, a copper foil, a solder resist (photosensitive agent) on the copper foil, a plating layer, etc., which constitute the TAB tape. Due to the high rigidity of the material, the TAB tape may be difficult to bend in the bending step, or the tape may be broken if it is forcibly bent.
In particular, since the plating layer on the electrical wiring located at the bent portion is relatively harder than the copper foil, the plating layer breaks when the TAB tape is bent, causing an abnormal appearance of the semiconductor package and lowering reliability. The task of doing so remained.
[0008]
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to improve the reliability of a semiconductor package by contributing to miniaturization while maintaining the appropriate strength by easily bending a TAB tape, and to reduce the manufacturing cost of a tape carrier for a semiconductor device. Is to provide.
[0009]
[Means for Solving the Problems]
To achieve the above object, the present invention provides a two-layer TAB (Tape Automated Bonding) tape having a polyimide tape and a copper foil, or a three-layer TAB tape having a polyimide tape, an adhesive, and a copper foil. In a semiconductor device tape carrier configured to be used by being bent in the length direction,
The thickness of the insulating resin (solder resist) on the copper foil positioned at the bent portion of the TAB tape is adjusted by changing the thickness of the insulating resin (solder resist) on the copper foil positioned at the bent portion of the TAB tape. Formed thinner than the thickness of the insulating resin to impart bending flexibility to the insulating resin located at the bending portion of the TAB tape,
By reducing the composite rigidity synthesized by the polyimide resin and the insulating resin located at the bent portion of the TAB tape,
A tape carrier for a semiconductor device, characterized in that the two-layer or three-layer TAB tape is easily bent.
[0010]
According to the present invention, in order to achieve the above object, the two-layer or three-layer TAB tape has a thickness of the insulating resin on the copper foil located at a bending portion of the polyimide tape of 1 to 10 μm. The present invention provides a tape carrier for a semiconductor device which is formed and has no plating layer in a bent portion of the TAB tape.
[0011]
According to the present invention, in order to achieve the above object, the two-layer or three-layer TAB tape has a resin thickness of 5 to 40 μm (preferably 5 to 40 μm) at a position where the TAB tape is bent. -30 μm), the adhesive thickness is 3-20 μm (preferably 5-18 μm), the copper foil thickness is 5-30 μm (preferably 8-20 μm), and the thickness of the insulating resin on the copper foil is 1 Provided is a tape carrier for a semiconductor device, wherein the tape carrier is formed to have a thickness of 10 to 10 μm (preferably 3 to 10 μm).
[0012]
According to the present invention, in order to achieve the above object, the two-layer or three-layer TAB tape has a resin thickness of 5 to 50 μm (preferably, a resin thickness of the polyimide tape located at a non-bending portion of the TAB tape). 10 to 40 μm), the thickness of the adhesive is 3 to 20 μm (preferably 5 to 18 μm), the thickness of the copper foil is 5 to 30 μm (preferably 8 to 20 μm), and the thickness of the insulating resin on the copper foil is Provided is a tape carrier for a semiconductor device, which is formed to have a thickness of 5 to 50 μm (preferably 5 to 30 μm).
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a cross section of a semiconductor device tape carrier in which a semiconductor chip 6 is mounted on a two-layer TAB tape 10 according to a first embodiment of the present invention.
In FIG. 1, a two-layer TAB tape 10 having a polyimide tape 1 and a copper foil 3 has a via hole 11, and an insulating resin 7 on the copper foil 3 (conductor pattern) located at a bent portion 1 </ b> A of the TAB tape 10. The thickness of the (solder resist) is formed thinner than the thickness of the insulating resin 7 (solder resist) on the copper foil 3 (conductor pattern) located in the unbent portion 1B of the TAB tape 10, and the TAB tape 10 is bent. In addition to imparting easy bending flexibility to the insulating resin 7 (solder resist) located at the portion 1A, the composite rigidity synthesized by the polyimide tape 1 and the insulating resin 7 (solder resist) located at the bending portion 1A of the TAB tape 10 Is reduced, and the two-layer TAB tape 10 that is easy to bend is configured.
[0014]
In the case of the TAB tape 10 shown in FIG. 1, the thickness of the polyimide tape 1 is 5 to 50 μm (preferably 10 to 40 μm), the thickness of the copper foil 3 is 5 to 30 μm (preferably 8 to 20 μm), and the bent portion 1A The thickness of the insulating resin 7 located in the unfolded portion 1B is not particularly limited, but is 5 to 50 μm (preferably 5 to 10 μm). ３０30 μm).
[0015]
The semiconductor chip 6 is mounted on the TAB tape 10 of FIG. In order to electrically connect the semiconductor chips 6 mounted on the TAB tape 10, predetermined electric wiring (wiring pattern) is formed on the copper foil 3 by a photolithography technique using a photosensitive agent (solder resist).
The electrical connection between the semiconductor chip 6 mounted on the TAB tape 10 and the copper foil 3 (wiring pattern) is performed by heating the conductive paste 5 such as an Ag paste or a solder paste at a high temperature of 150 ° C. or more for 10 to 30 seconds or more. It is done by doing. The insulating resin 7 on the copper foil 3 is provided by printing or the like in order to maintain electrical insulation and prevent the flow of the conductive paste 5.
[0016]
FIG. 2 shows a cross section of a semiconductor device tape carrier in which a semiconductor chip 6 is mounted on a two-layer TAB tape 10 according to the first embodiment of the present invention.
In FIG. 2, the TAB tape 10 on which the semiconductor chips 6 are mounted has two or more semiconductor chips 6 mounted in one semiconductor package in order to improve the mounting density by mounting many semiconductor chips 6 in a small space. Then, the middle of the TAB tape 10 is bent and used.
In the TAB tape 10 shown in FIG. 2, the thickness of the insulating resin 7 (solder resist) formed on the copper foil 3 located on the bent portion 1A is such that the insulating resin 7 on the copper foil 3 located on the unfolded portion 1B ( The thickness is smaller than the thickness of the solder resist, so that the insulating resin 7 (solder resist) located at the bent portion 1A has flexibility to be easily bent. As a result, the polyimide tape 1 and the insulating resin 7 (solder resist) 2), the composite rigidity is reduced, and the TAB tape 10 can be easily bent.
After mounting two or more semiconductor chips 6 on the TAB tape 10, the center of the TAB tape 10 is bent to form a semiconductor package with the mold resin 8, and the solder balls 9 for external connection are placed in the via holes 11. The semiconductor package is completed.
[0017]
FIG. 3 shows a cross section of a semiconductor device tape carrier in which a semiconductor chip 6 is mounted on a three-layer TAB tape 10 according to a second embodiment of the present invention.
In FIG. 3, a three-layer TAB tape 10 having a polyimide tape 1, an adhesive 2, and a copper foil 3 has a via hole 11 on a copper foil 3 (conductor pattern) located at a bent portion 1 </ b> A of the TAB tape 10. The thickness of the insulating resin 7 (solder resist) is smaller than the thickness of the insulating resin 7 (solder resist) on the copper foil 3 (conductor pattern) located at the unbent portion 1B of the TAB tape 10 and the TAB The insulating resin 7 (solder resist) located at the bending portion 1A of the tape 10 is given flexibility to be easily bent, and the polyimide tape 1, the adhesive 2, and the insulating resin 7 (solder) located at the bending portion 1A of the TAB tape 10 are provided. A three-layer TAB tape 10 that is easy to bend by reducing the composite rigidity synthesized by the resist is formed.
[0018]
In the case of the TAB tape 10 shown in FIG. 3, the thickness of the polyimide tape 1 is 5 to 50 μm (preferably 10 to 40 μm), the thickness of the adhesive 2 is 3 to 20 μm (preferably 5 to 18 μm), Is 5 to 30 μm (preferably 8 to 20 μm), the thickness of the insulating resin 7 located at the bent portion 1A is 1 to 10 μm (preferably 3 to 10 μm), and the thickness of the insulating resin 7 located at the unfolded portion 1B is Although the thickness is not particularly limited, the thickness is formed to 5 to 50 μm (preferably 5 to 30 μm).
[0019]
The semiconductor chip 6 is mounted on the TAB tape 10 shown in FIG. In order to electrically connect the semiconductor chips 6 mounted on the TAB tape 10, predetermined electric wiring (wiring pattern) is formed on the copper foil 3 by a photolithography technique using a photosensitive agent (solder resist).
The electrical connection between the semiconductor chip 6 mounted on the TAB tape 10 and the copper foil 3 (wiring pattern) is performed by heating the conductive paste 5 such as an Ag paste or a solder paste at a high temperature of 150 ° C. or more for 10 to 30 seconds or more. It is done by doing. The insulating resin 7 on the copper foil 3 is provided by printing or the like in order to maintain electrical insulation and prevent the flow of the conductive paste 5.
[0020]
FIG. 4 shows a cross section of a semiconductor device tape carrier in which a semiconductor chip 6 is mounted on a three-layer TAB tape 10 according to a second embodiment of the present invention.
In FIG. 4, the TAB tape 10 on which the semiconductor chips 6 are mounted has two or more semiconductor chips 6 mounted in one semiconductor package in order to increase the mounting density by mounting a large number of semiconductor chips 6 in a small space. Then, the middle of the TAB tape 10 is bent and used.
The TAB tape 10 shown in FIG. 4 has a thickness of the insulating resin 7 (solder resist) formed on the copper foil 3 located on the bent portion 1A, and the insulating resin on the copper foil 3 located on the unfolded portion 1B. 7 (solder resist), the insulating resin 7 (solder resist) located at the portion 1A to be bent is provided with easy bending flexibility. As a result, the polyimide tape 1, the adhesive 2, The composite rigidity of the insulating resin 7 (solder resist) is reduced, and the TAB tape 10 can be easily bent.
After mounting two or more semiconductor chips 6 on the TAB tape 10, the center of the TAB tape 10 is bent to form a semiconductor package with the mold resin 8, and the solder balls 9 for external connection are placed in the via holes 11. The semiconductor package is completed.
[0021]
FIG. 5 shows a cross section of a semiconductor device tape carrier in which a semiconductor chip 6 is mounted on a two-layer TAB tape 10 according to a third embodiment of the present invention.
In FIG. 5, a two-layer TAB tape 10 composed of a polyimide tape 1 and a copper foil 3 has a via hole 11. The TAB tape 10 is formed such that the thickness of the polyimide tape 1 located at the bendable portion 1A of the TAB tape 10 is smaller than the thickness of the polyimide tape 1 located at the non-bendable portion 1B of the TAB tape 10, and The polyimide tape 1 located is configured to be easily bent.
[0022]
In the TAB tape 10 of FIG. 5, the thickness of the insulating resin 7 (solder resist) on the copper foil 3 (conductor pattern) located at the bent portion 1A of the TAB tape 10 is further positioned at the unbent portion 1B of the TAB tape 10. The thickness of the insulating resin 7 (solder resist) on the copper foil 3 (conductor pattern) to be formed is smaller than the thickness of the insulating resin 7 (solder resist) located on the bending portion 1A of the TAB tape 10 so that the insulating resin 7 (solder resist) can be easily bent. In addition to this, the composite rigidity synthesized by the polyimide tape 1 and the insulating resin 7 (solder resist) located at the bent portion 1A of the TAB tape 10 is reduced to form the TAB tape 10 which can be easily bent.
[0023]
In the case of the TAB tape 10 shown in FIG. 5, the thickness of the polyimide tape 1 in the bent portion 1A is 5 to 40 μm (preferably 5 to 30 μm), and the thickness of the copper foil 3 is 5 to 30 μm (preferably 8 to 20 μm). The thickness of the polyimide tape 1 in the unbent portion 1B is 5 to 50 μm (preferably 10 to 40 μm), and the thickness of the copper foil 3 is 5 to 30 μm (preferably 8 to 20 μm).
In addition, the thickness 1 to 10 μm (preferably 3 to 10 μm) of the insulating resin 7 (solder resist) formed on the copper foil 3 located at the bent portion 1A of the TAB tape 10 is applied to the unbent portion 1B of the TAB tape 10. The insulating resin 7 (solder resist) on the copper foil 3 is thinner than 5 to 50 μm (preferably 5 to 30 μm), so that it is insulated from the polyimide tape 1 located at the bent portion 1A of the TAB tape 10. The composite rigidity of the resin 7 (solder resist) is reduced to give the TAB tape 10 flexibility that can be easily bent.
[0024]
The semiconductor chip 6 is mounted on the TAB tape 10 shown in FIG. In order to electrically connect the semiconductor chips 6 mounted on the TAB tape 10, predetermined electric wiring (wiring pattern) is formed on the copper foil 3 by a photolithography technique using a photosensitive agent (solder resist).
The electrical connection between the semiconductor chip 6 mounted on the TAB tape 10 and the copper foil 3 (wiring pattern) is performed by heating the conductive paste 5 such as an Ag paste or a solder paste at a high temperature of 150 ° C. or more for 10 to 30 seconds or more. It is done by doing. The insulating resin 7 on the copper foil 3 is provided by a method such as printing in order to maintain electrical insulation and prevent the flow of the conductive paste 5.
[0025]
FIG. 6 is a cross-sectional view of a semiconductor device tape carrier in which a semiconductor chip 6 is mounted on a two-layer TAB tape 10 according to a third embodiment of the present invention.
In FIG. 6, the TAB tape 10 on which the semiconductor chips 6 are mounted has two or more semiconductor chips 6 mounted in one semiconductor package in order to increase the mounting density by mounting many semiconductor chips 6 in a small space. Then, the middle of the TAB tape 10 is bent and used.
In the TAB tape 10 of FIG. 6, the thickness of the polyimide tape 1 located at the portion 1A to be bent is formed thinner than the thickness of the portion 1B not to be bent, so that the polyimide tape 1 is easily bent. Further, the thickness of the insulating resin 7 (solder resist) formed on the copper foil 3 located at the portion 1A to be bent is larger than the thickness of the insulating resin 7 (solder resist) on the copper foil 3 located at the portion 1B not to be bent. Also, the insulating resin 7 (solder resist) located at the portion 1A to be bent has flexibility to be easily bent. As a result, the composite rigidity of the polyimide tape 1 and the insulating resin 7 (solder resist) is reduced. Therefore, the TAB tape 10 can be easily bent.
After mounting two or more semiconductor chips 6 on the TAB tape 10, the center of the TAB tape 10 is bent to form a semiconductor package with the mold resin 8, and the solder balls 9 for external connection are placed in the via holes 11. The semiconductor package is completed.
[0026]
FIG. 7 shows a cross section of a semiconductor device tape carrier in which a semiconductor chip 6 is mounted on a three-layer TAB tape 10 according to a fourth embodiment of the present invention.
In FIG. 7, a copper foil 3 is adhered on a polyimide tape 1 with an adhesive 2 to form a three-layer TAB tape 10. The TAB tape 10 has a via hole 11. The thickness of the polyimide tape 1 located at the bent portion 1 </ b> A of the TAB tape 10 and the thickness of the insulating resin 7 (solder resist) formed on the copper foil 3 The polyimide tape 1 located at the unfolded portion 1A of the tape 10 is formed to be thinner than the thickness of the polyimide tape 1 located at the unbent portion 1B and the thickness of the insulating resin 7 (solder resist) formed on the copper foil 3. The insulating resin 7 (solder resist) formed on the copper foil 3 is easily bent.
[0027]
In the case of the TAB tape 10 shown in FIG. 7, the thickness of the polyimide tape 1 at the bent portion 1A is 5 to 40 μm (preferably 5 to 30 μm), and the thickness of the adhesive 2 is 3 to 20 μm (preferably 5 to 18 μm). The thickness of the copper foil 3 is 5 to 30 μm (preferably 8 to 20 μm), the thickness of the polyimide tape 1 in the unbent portion 1B is 5 to 50 μm (preferably 10 to 40 μm), and the thickness of the adhesive 2 Is formed in a thickness of 3 to 20 μm (preferably 5 to 18 μm), and the thickness of the copper foil 3 is 5 to 30 μm (preferably 8 to 20 μm).
In addition, the thickness 1 to 10 μm (preferably 3 to 10 μm) of the insulating resin 7 (solder resist) formed on the copper foil 3 located at the bent portion 1A of the TAB tape 10 is applied to the unbent portion 1B of the TAB tape 10. By making the thickness of the insulating resin 7 (solder resist) on the located copper foil 3 thinner than 5 to 50 μm (preferably 5 to 30 μm), the polyimide tape 1 positioned at the bent portion 1A of the TAB tape 10 is bonded. The composite rigidity synthesized by the agent 2 and the insulating resin 7 (solder resist) is reduced to give the TAB tape 10 flexibility that can be easily bent.
[0028]
The semiconductor chip 6 is mounted on the TAB tape 10 shown in FIG. In order to electrically connect the semiconductor chips 6 mounted on the TAB tape 10, predetermined electric wiring (wiring pattern) is formed on the copper foil 3 by a photolithography technique using a photosensitive agent (solder resist).
The electrical connection between the semiconductor chip 6 mounted on the TAB tape 10 and the copper foil 3 (wiring pattern) is performed by heating the conductive paste 5 such as an Ag paste or a solder paste at a high temperature of 150 ° C. or more for 10 to 30 seconds or more. Is performed by The insulating resin 7 on the copper foil 3 is provided by a method such as printing in order to maintain electrical insulation and prevent the flow of the conductive paste 5.
[0029]
FIG. 8 shows a cross section of a semiconductor device tape carrier in which a semiconductor chip 6 is mounted on a three-layer TAB tape 10 according to a fourth embodiment of the present invention.
In FIG. 8, the TAB tape 10 on which the semiconductor chips 6 are mounted has two or more semiconductor chips 6 mounted in one semiconductor package in order to improve the mounting density by mounting many semiconductor chips 6 in a small space. Then, the middle of the TAB tape 10 is bent and used.
In the TAB tape 10 shown in FIG. 8, the thickness of the polyimide tape 1 located at the portion 1A to be bent is formed thinner than the thickness of the portion 1B not to be bent, so that the polyimide tape 1 is easily bent. Further, the thickness of the insulating resin 7 (solder resist) formed on the copper foil 3 located at the portion 1A to be bent is larger than the thickness of the insulating resin 7 (solder resist) on the copper foil 3 located at the portion 1B not to be bent. Also, the insulating resin 7 (solder resist) located at the bent portion 1A is provided with flexibility to be easily bent. As a result, the polyimide tape 1, the adhesive 2, and the insulating resin 7 (solder resist) The composite rigidity is reduced, and the TAB tape 10 can be easily bent.
After mounting two or more semiconductor chips 6 on the TAB tape 10, the center of the TAB tape 10 is bent to form a semiconductor package with the mold resin 8, and the solder balls 9 for external connection are placed in the via holes 11. The semiconductor package is completed.
[0030]
In the TAB tape 10 according to the embodiment of the present invention shown in FIGS. 1, 3, 5, and 7, an electric connection (wiring pattern) of the copper foil 3 of the unbent portion 1B of the TAB tape 10 is made. A plating layer (not shown) such as Au or Au / Ni necessary for plating is provided with a thickness of 0.2 to 1.5 μm by immersion in a plating solution, while a bent portion 1A of the TAB tape 10 is provided with a plating layer. It is configured such that no layer is formed.
In forming the electric wiring (wiring pattern) on the copper foil 3, in order to prevent the plating layer from being applied to the copper foil 3 (wiring pattern) of the bending portion 1A of the TAB tape 10, the bending portion 1A is formed before the plating step. By printing or applying a thin flexible resin (not shown) on the copper foil 3 of FIG. 1 and protecting the copper foil 3 (wiring pattern) on the lower surface of the flexible resin from the plating solution, a plating layer is formed on the wiring pattern. In addition, it serves to supplement the mechanical strength of the portion 1A to be bent into a flexible resin. The thin flexible resin is printed or applied not only on one side of the bent portion 1A (the front surface of the polyimide tape 1) but also on the back surface of the bent portion 1A (the back surface of the polyimide tape 1) to provide a polyimide. A thin flexible resin can be provided on both sides of the tape 1.
[0031]
FIG. 9 is a characteristic diagram showing the relationship between the thickness of the constituent material of the tape carrier for a semiconductor device according to the embodiment of the present invention and the bending shape acceptance ratio.
The configuration of the tape carrier of FIG. 9 is the same as that of the tape carrier shown in FIG. 1 (the polyimide tape 1 having a thickness of 5 to 50 μm, the copper foil 3 having a thickness of 5 to 30 μm, and the insulating resin 7 having a thickness of 1 to 5 μm. The thickness of the solder resist (insulating resin 7) of the non-bent portion 1B is set to 5 to 50 μm, and the thickness of the solder resist of the portion 1A to be bent is set as the thickness of the solder resist (insulating resin 7). Each of the samples was measured using 5 μm, 10 μm, 20 μm, 30 μm, and 40 μm formed samples (the number of samples n was 4, each having a total of n = 20 tape carriers). The sample was bent only once in the production line, and the sample where the sample was bent was determined to be acceptable, and the sample that was not bent was determined to be rejected.
[0032]
According to FIG. 9, the bending shape acceptance rate (%) is such that the solder resist thickness of 5 μm and 10 μm samples pass 100%, the solder resist thickness 20 μm sample passes 40%, whereas the solder resist thickness It can be seen that the pass rates of the 30 μm and 40 μm samples are almost 0%.
In addition, in the samples having the solder resist thicknesses of 5 μm and 10 μm, no cracking or chipping failure of the bent portion of the resin was observed.
As is clear from the characteristic diagram of FIG. 9, the thickness of the solder resist on the copper foil 3 (conductor pattern) located at the bent portion of the tape carrier according to the embodiment of the present invention is 1 to 15 μm, preferably 5 to 10 μm. Was found to be optimal.
[0033]
In order to measure a sample that supplements the characteristic diagram shown in FIG. 9, the tape carrier of the embodiment shown in FIG.
The thickness of the polyimide tape 1 located at the portion 1A to be bent is formed to be as thin as 10 to 30 μm than the thickness 20 to 40 μm of the polyimide tape 1 at the portion 1B which is not to be bent, and on the wiring pattern formed on the copper foil 3. The thickness of the insulating resin 7 (solder resist) on the wiring pattern formed on the copper foil 3 located on the portion 1A to be bent is smaller than the thickness of the insulating resin 7 (solder resist) located on the portion 1B where the portion is not bent. In a tape carrier having a thickness as small as 5 to 10 μm, the solder resist (insulating resin 7) has five thicknesses as shown in FIG. 9 (samples having solder resist thicknesses of 5 μm, 10 μm, 20 μm, 30 μm, and 40 μm). In the case of the above, the characteristics of the tape carrier of each sample were measured.
As a result, the bending shape acceptance ratio (%) when the thickness of the polyimide tape 1 in the bent portion 1A and the thickness of the insulating resin 7 (solder resist) are reduced is almost the same as the characteristic diagram of FIG. It turned out to show.
[0034]
【The invention's effect】
According to the tape carrier for a semiconductor device of the present invention, the thickness of the insulating resin on the copper foil located at the bent portion of the two-layer or three-layer TAB tape is formed smaller than the thickness of the insulating resin located at the unfolded portion. In addition to providing flexibility that is easy to bend and reducing the composite rigidity that is synthesized by the polyimide tape and the insulating resin located at the portion to be bent, two or three layers that are extremely easy to bend due to the synergistic action of the three members A tape carrier for a semiconductor device having a TAB tape configuration can be provided.
[0035]
According to the tape carrier for a semiconductor device of the two-layer or three-layer TAB tape of the present invention, since the TAB tape does not have a slit hole for bending, the copper foil of the TAB tape is cut off from the slit hole during the manufacturing. Therefore, the efficiency of assembling the semiconductor package can be improved.
Moreover, the composite rigidity is reduced by the polyimide tape, adhesive, copper foil, insulating resin on the copper foil, etc. that make up the TAB tape at the bent part without forming a plating layer on the electrical wiring located at the bent part. To maintain the appropriate strength of the TAB tape, making it easy to bend the TAB tape at 180 degrees, and it is possible to bend and fold at any angle, such as diagonal bending of the TAB tape. In addition, the problem of appearance abnormality of the semiconductor package due to cracking of the plating layer at the time of bending is completely eliminated, and it is possible to achieve a high-density semiconductor package, which can significantly contribute to high-density mounting of a semiconductor device.
[0036]
As described above, the tape carrier for a semiconductor device of the present invention can provide a tape carrier for a semiconductor device in which the TAB tape can be easily bent and the manufacturing cost is inexpensive. The effect of improving reliability and reducing the size of a semiconductor package used in high-speed digital data processing equipment can be obtained.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a cross section of a semiconductor device tape carrier in which a semiconductor chip is mounted on a two-layer TAB tape according to a first embodiment of the present invention.
FIG. 2 is an explanatory view showing a cross section in which a semiconductor device tape carrier in which a semiconductor chip is mounted on a two-layer TAB tape according to the first embodiment of the present invention is bent.
FIG. 3 is an explanatory view showing a cross section of a semiconductor device tape carrier in which a semiconductor chip is mounted on a three-layer TAB tape according to a second embodiment of the present invention.
FIG. 4 is an explanatory view showing a cross section of a semiconductor device tape carrier in which a semiconductor chip is mounted on a three-layer TAB tape according to a second embodiment of the present invention;
FIG. 5 is an explanatory view showing a cross section of a semiconductor device tape carrier in which a semiconductor chip is mounted on a two-layer TAB tape according to a third embodiment of the present invention.
FIG. 6 is an explanatory view showing a cross section in which a semiconductor device tape carrier in which a semiconductor chip is mounted on a two-layer TAB tape according to a third embodiment of the present invention is bent.
FIG. 7 is an explanatory view showing a cross section of a semiconductor device tape carrier in which a semiconductor chip is mounted on a three-layer TAB tape according to a fourth embodiment of the present invention.
FIG. 8 is an explanatory view showing a cross section of a semiconductor device tape carrier in which a semiconductor chip is mounted on a three-layer TAB tape according to a fourth embodiment of the present invention.
FIG. 9 is a characteristic diagram showing the relationship between the thickness of a component of a tape carrier for a semiconductor device and a bending shape acceptance ratio according to an embodiment of the present invention.
FIG. 10 is an explanatory view showing a cross section in which a semiconductor chip is mounted on a three-layer TAB tape by a conventional technique.
FIG. 11 is an explanatory diagram showing a cross section obtained by bending a three-layer TAB tape on which a semiconductor chip according to a conventional technique is mounted.
[Explanation of symbols]
1 Polyimide tape
1A Bending part
1B Non-bending part
2 adhesive
3 Copper foil (conductor pattern)
4 Plating layer
5 Conductive paste
6 Semiconductor chip
7 Insulating resin (solder resist)
8 Mold resin
9 solder balls
10 TAB tape
11 Via Hole
12 slit holes
13 Embedding resin

Claims (4)

ポリイミドテープと銅箔を有する２層のＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）テープ、あるいはポリイミドテープ、接着剤、および銅箔を有する３層のＴＡＢテープを、テープ長さ方向に折り曲げて用いる構成の半導体装置用テープキャリアにおいて、
前記２層あるいは３層のＴＡＢテープは、前記ＴＡＢテープの折り曲げる部分に位置する前記銅箔上の絶縁樹脂（ソルダーレジスト）の厚さを、前記ＴＡＢテープの折り曲げない部分に位置する前記銅箔上の絶縁樹脂の厚さよりも薄く形成して、前記ＴＡＢテープの折り曲げる部分に位置する前記絶縁樹脂に折り曲げ容易な柔軟性を付与するとともに、
前記ＴＡＢテープの折り曲げる部分に位置する前記ポリイミドテープと前記絶縁樹脂で合成される複合剛性を低減させることにより、
前記２層あるいは３層のＴＡＢテープの折り曲げを容易に構成したことを特徴とする半導体装置用テープキャリア。For a semiconductor device having a configuration in which a two-layer TAB (Tape Automated Bonding) tape having a polyimide tape and a copper foil, or a three-layer TAB tape having a polyimide tape, an adhesive, and a copper foil are bent in the tape length direction. In tape carriers,
The thickness of the insulating resin (solder resist) on the copper foil positioned at the bent portion of the TAB tape is adjusted by changing the thickness of the insulating resin (solder resist) on the copper foil positioned at the bent portion of the TAB tape. Formed thinner than the thickness of the insulating resin to impart bending flexibility to the insulating resin located at the bending portion of the TAB tape,
By reducing the composite rigidity synthesized by the polyimide resin and the insulating resin located at the bent portion of the TAB tape,
A tape carrier for a semiconductor device, wherein the two-layer or three-layer TAB tape is easily bent. 前記２層あるいは３層のＴＡＢテープは、前記ポリイミドテープの折り曲げる部分に位置する前記銅箔上の絶縁樹脂の厚さを１〜１０μｍに形成し、
前記ＴＡＢテープの折り曲げる部分にめっき層を有しない構成の請求項１に記載の半導体装置用テープキャリア。The two-layer or three-layer TAB tape is formed so that the thickness of the insulating resin on the copper foil located at the bent portion of the polyimide tape is 1 to 10 μm,
2. The tape carrier for a semiconductor device according to claim 1, wherein the TAB tape does not have a plating layer in a bent portion of the TAB tape. 3. 前記２層あるいは３層のＴＡＢテープは、前記ＴＡＢテープの折り曲げる部分に位置する前記ポリイミドテープの樹脂厚さが５〜４０μｍ、前記接着剤厚さが３〜２０μｍ、前記銅箔厚さが５〜３０μｍ、前記銅箔上の絶縁樹脂の厚さが１〜１０μｍに形成したことを特徴とする請求項１に記載の半導体装置用テープキャリア。The two-layer or three-layer TAB tape has a resin thickness of 5 to 40 μm, an adhesive thickness of 3 to 20 μm, and a copper foil thickness of 5 to 40 μm of the polyimide tape located at a bent portion of the TAB tape. 2. The tape carrier for a semiconductor device according to claim 1, wherein the thickness is 30 [mu] m and the thickness of the insulating resin on the copper foil is 1 to 10 [mu] m. 前記２層あるいは３層のＴＡＢテープは、前記ＴＡＢテープの折り曲げない部分に位置する前記ポリイミドテープの樹脂厚さが５〜５０μｍ、前記接着剤厚さが３〜２０μｍ、前記銅箔厚さが５〜３０μｍ、前記銅箔上の絶縁樹脂（ソルダーレジスト）の厚さが５〜５０μｍに形成したことを特徴とする請求項１に記載の半導体装置用テープキャリア。The two-layer or three-layer TAB tape has a resin thickness of 5 to 50 μm, an adhesive thickness of 3 to 20 μm, and a copper foil thickness of 5 to 50 μm of the polyimide tape located at the unbent portion of the TAB tape. 2. The tape carrier for a semiconductor device according to claim 1, wherein the thickness of the insulating resin (solder resist) on the copper foil is 5 to 50 [mu] m.
JP2003051689A 2003-02-27 2003-02-27 Tape carrier for semiconductor devices Expired - Fee Related JP3903931B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008029813A1 (en) * 2006-09-04 2008-03-13 Nec Corporation Wiring board composite body, semiconductor device, and method for manufacturing the wiring board composite body and the semiconductor device
WO2008038377A1 (en) * 2006-09-28 2008-04-03 Shinoda Plasma Co., Ltd. Display device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008029813A1 (en) * 2006-09-04 2008-03-13 Nec Corporation Wiring board composite body, semiconductor device, and method for manufacturing the wiring board composite body and the semiconductor device
JPWO2008029813A1 (en) * 2006-09-04 2010-01-21 日本電気株式会社 Wiring board composite, semiconductor device, and manufacturing method thereof
WO2008038377A1 (en) * 2006-09-28 2008-04-03 Shinoda Plasma Co., Ltd. Display device
JPWO2008038377A1 (en) * 2006-09-28 2010-01-28 篠田プラズマ株式会社 Display device
JP4927855B2 (en) * 2006-09-28 2012-05-09 篠田プラズマ株式会社 Display device

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