JP2004259798A - Semiconductor device - Google Patents

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JP2004259798A
JP2004259798A JP2003046802A JP2003046802A JP2004259798A JP 2004259798 A JP2004259798 A JP 2004259798A JP 2003046802 A JP2003046802 A JP 2003046802A JP 2003046802 A JP2003046802 A JP 2003046802A JP 2004259798 A JP2004259798 A JP 2004259798A
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chip
substrate
thermal expansion
semiconductor
coefficient
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Masanori Ochi
雅範 越智
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing the warp of a board and the crack and of an external terminal. <P>SOLUTION: The semiconductor device comprises a semiconductor chip 103, a first chip supporting board 101 for supporting the semiconductor chip 103, a second chip supporting board 104 which is provided with a first region where the first chip supporting board 101 is formed and a second region on its front surface, a first wiring layer 106 formed on the second region of the second chip supporting board 104, and a sealing material 110 which seals up the semiconductor chip 103. In the semiconductor device, the coefficient of thermal expansion of the first chip supporting board 101 is intermediate between those of the semiconductor chip 103 and the second chip supporting board 104. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、ＣＳＰ構造などの半導体装置に係り、特に、パッケージに搭載された半導体チップを支持するチップ支持基板の構造に関する。
【０００２】
【従来の技術】
半導体集積回路などが形成された半導体チップを有する半導体装置において、外部端子として半田などからなるバンプ電極が設けられ、半導体チップを支持するチップ支持基板を有する半導体装置の一例として、ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）などが知られている。
【０００３】
図２に、従来の半導体装置を示す。セラミック基板からなるチップ支持基板４０１上にダイボンド材４０２を介して半導体チップ４０３が載置されている。半導体チップ４０３上には、半導体集積回路などが形成されている。半導体チップ４０３上に形成された接続電極（図示しない）は、ワイヤ４０４を介して、チップ支持基板４０１上に形成された第１の配線層４０５に接続されている。ワイヤ４０４は、第１の配線層４０５から半導体チップ４０３へ電源電位またはグランド電位を供給している。
【０００４】
チップ支持基板４０１上に形成された第１の配線層４０５は、チップ支持基板４０１に形成されたコンタクト４０６を介して、チップ支持基板４０１の下に形成された第２の配線層４０７に接続されている。第２の配線層４０７には、外部端子としてバンプ電極４０８が形成されている。また、半導体チップ４０３は、樹脂などの封止体４０９によって封止されており、バンプ電極４０８を介して、チップ支持基板４０１と実装基板４１０が接続されている。この種の半導体装置に関連した技術としては、特許文献１や特許文献２などが知られている。
【０００５】
なお、特許文献１には、半導体チップよりも熱膨張係数が実装基板に近い応力緩和部（モールド樹脂）を半導体チップの下に配置することによってバンプ電極に応力が集中するのを回避する方法が記載されている。
【０００６】
また、特許文献２では、セラミック絶縁基板の裏面に封止部材よりも熱膨張係数が大きい熱硬化性樹脂からなる被覆層を形成することによって、絶縁基板の裏面にも圧縮応力を生じさせて、パッケージの封止部材と絶縁基板との熱膨張係数の違いによる絶縁基板の変形を防ぎ、安定した接続状態を維持できる方法が記載されている。
【０００７】
【特許文献１】
特開２００１−２１７２６１号公報（図３）
【特許文献２】
特開２０００−３４０７０７号公報（図１）
【０００８】
【発明が解決しようとする課題】
このように形成された半導体装置では、半導体チップ、チップ支持基板、実装基板で熱膨張係数に差が生じている。一般的に、半導体チップの熱膨張係数は、２．６〜３．６ｐｐｍ／℃程度，実装基板の熱膨張係数は、２０〜２５ｐｐｍ／℃程度である。半導体チップと実装基板の熱膨張係数の差が大きいため、チップ支持基板の熱膨張係数は、半導体チップの熱膨張係数と実装基板の熱膨張係数の間の値になるよう、７〜１５ｐｐｍ／℃程度で形成される。
【０００９】
図２に示すように、半導体チップとチップ支持基板の熱膨張係数の差がより小さくなるようにチップ支持基板の熱膨張係数が７ｐｐｍ／℃で形成すると、チップ支持基板と実装基板の熱膨張係数の差が大きくなり、温度サイクル試験において、チップ支持基板と実装基板の接続部であるバンプ電極に大きな熱応力がかかり、そりやクラックが発生し、接続不良を引き起こすという問題があった。チップ支持基板と実装基板を接続するバンプ電極にかかる熱応力は、特に、チップ支持基板の外周部に形成されたバンプ電極に大きくかかる。
【００１０】
また、図３に示すように、チップ支持基板と実装基板の熱膨張係数の差が小さくなるようにチップ支持基板の熱膨張係数が１５ｐｐｍ／℃で形成すると、半導体チップとチップ支持基板の熱膨張係数の差が大きくなり、温度サイクル試験において、半導体チップとチップ支持基板の間に大きな熱応力がかかり、そりやクラックが発生し、接続不良を引き起こすという問題があった。
【００１１】
本発明は、上記した問題点を解決すべくなされたもので、基板のそりや外部端子のクラックを低減することが可能な半導体装置を提供することを目的とする。
【００１２】
【課題を解決するための手段】
上記した目的を達成するための本発明の半導体装置の一形態は、半導体チップと、
前記半導体チップを支持する第１のチップ支持基板と、
表面に第１の領域及び第２の領域を有し、前記第１の領域上に前記第１のチップ支持基板が形成された第２のチップ支持基板と、
前記第２のチップ支持基板の前記第２の領域上に形成された第１の配線層と、
前記半導体チップを封止する封止体とを具備した半導体装置であって、
前記第１のチップ支持基板の熱膨張係数は、前記半導体チップの熱膨張係数と前記第２のチップ支持基板の熱膨張係数の間の大きさであることを特徴としている。
【００１３】
本発明の一形態によれば、基板のそりや外部端子のクラックを低減することができる。
【００１４】
【発明の実施の形態】
以下、図面を参照して、本発明の実施の形態について詳細に説明する。
（第１の実施の形態）
図１に本発明の第１の実施の形態に係る半導体装置を示す。図１に、ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）構造の半導体装置の要部断面図を示す。アルミナ系セラミック基板からなる第１のチップ支持基板１０１上にダイボンド材１０２を介して半導体チップ１０３が載置されている。ダイボンド材１０２は、導電性樹脂、絶縁性樹脂などであり、例えばＡｇペーストである。半導体チップ１０３上には、半導体集積回路などが形成されている。
【００１５】
第１のチップ支持基板１０１下には、ガラス系セラミック基板からなる第２のチップ支持基板１０４が燒結されている。第２のチップ支持基板１０４は、表面に第１の領域及び第２の領域を有しており、第１のチップ支持基板１０１は、第１の領域上に形成されている。第２の領域は、第１の領域の外周部に形成されている。ここで、アルミナ系セラミックスとは、アルミナ、窒化アルミニウム等を主成分とするセラミックスであり、ガラス系セラミックスとは、ホウ珪酸ガラス、リチウム珪酸ガラス等を主成分とするセラミックスである。
【００１６】
半導体チップ１０３上に形成された接続電極（図示しない）は、ワイヤ１０５を介して、第２のチップ支持基板１０４の第２の領域上に形成された第１の配線層１０６に接続されている。ワイヤ１０５は、第１の配線層１０６から半導体チップ１０３へ電源電位またはグランド電位を供給している。第２のチップ支持基板１０４上に形成された第１の配線層１０６は、第２のチップ支持基板１０４に形成されたコンタクト１０７を介して、第２のチップ支持基板１０４の下に形成された第２の配線層１０８に接続されている。第２の配線層１０８には、外部端子として半田ボールによって構成されるバンプ電極１０９が形成されている。半導体チップ１０３は、樹脂などの封止体１１０によって封止されている。樹脂としては、例えば熱硬化性エポキシ系樹脂などがある。
【００１７】
また、第２のチップ支持基板１０４は、バンプ電極１０９を介して、実装基板１１１に接続されている。実装基板１１１は、通常、熱膨張係数の大きいガラス入りエポキシ樹脂などの加工しやすい材料で構成されている。
【００１８】
半導体チップ１０３の熱膨張係数は、２．６〜３．６ｐｐｍ／℃程度、アルミナ系セラミックスからなる第１のチップ支持基板１０１の熱膨張係数は、５〜７ｐｐｍ／℃程度、ガラス系セラミックスからなる第２のチップ支持基板１０４の熱膨張係数は、８〜１８ｐｐｍ／℃程度、実装基板１１１の熱膨張係数は、２０〜２５ｐｐｍ／℃程度である。すなわち、上から半導体チップ１０３＜第１のチップ支持基板１０１＜第２のチップ支持基板１０４＜実装基板１１１の順に熱膨張係数が大きくなるように形成されている。すなわち、第１及び第２のチップ支持基板１０１，１０４の熱膨張係数が、半導体チップ１０３の熱膨張係数と実装基板１１１の熱膨張係数の間の大きさになるよう形成されている。また、実装基板を実装する前の段階では、第１のチップ支持基板１０１の熱膨張係数が、半導体チップ１０３の熱膨張係数と第２のチップ支持基板１０４の熱膨張係数の間の大きさになるよう形成されている。
【００１９】
また、半導体チップ１０３と第１のチップ支持基板１０１を接続しているダイボンド材１０２の熱膨張係数は、半導体チップ１０３よりもやや大きい程度であり、熱膨張係数の差による熱応力の観点からは特に問題にならない。
【００２０】
第１のチップ支持基板１０１は、半導体チップの熱膨張係数により近い材料で構成され、第２のチップ支持基板１０４は、実装基板の熱膨張係数により近い材料で構成されているため、半導体チップ、チップ支持基板、実装基板との熱膨張係数の差をさらに緩衝し、熱膨張係数の差に起因して発生する基板やバンプ電極のそりやクラックを低減することができる。第１及び第２のチップ支持基板１０１，１０４の熱膨張係数の差は、内部応力として蓄えられるが、熱膨張係数の大きい第２のチップ支持基板１０４を、熱膨張係数の小さい第１のチップ支持基板１０１よりも厚くなるように形成することによって、たわみにくいチップ支持基板を形成することができる。
【００２１】
チップ支持基板と実装基板を接続するバンプ電極１０９にかかる熱応力は、特に、チップ支持基板の外周部に形成されたバンプ電極に集中して生じる。本実施の形態では、第１及び第２の配線層１０６，１０８が、第２のチップ支持基板１０４の外周部の上下に形成されているが、仮に第１及び第２の配線層１０６，１０８が、第１及び第２のチップ支持基板を束ねるよう、第１のチップ支持基板１０１上及び第２のチップ支持基板１０４下に設けられている場合には、チップ支持基板と実装基板を接続する際に生じる熱応力が集中する部分に、第１及び第２のチップ支持基板１０１，１０４の内部に蓄えられている熱応力がさらに加わることになる。よって、そりやクラックなどの不良が発生することがあるため、好ましくない。したがって、第１及び第２の配線層１０６，１０８は、実装基板１１１との熱膨張係数の差が比較的少ない第２のチップ支持基板１０４の上下に設けられている方がよい。
【００２２】
本実施の形態では、チップ支持基板に形成された外部端子として、チップ支持基板側に半田ボールを形成してバンプ電極を設けたＢＧＡ（Ｂａｌｌ ＧｒｉｄＡｒｒａｙ）タイプのＣＳＰの例を記載したが、チップ支持基板側に半田ボールを設けないＬＧＡ （Ｌａｎｄ Ｇｒｉｄ Ａｒａｙ）タイプのＣＳＰでも同様に適用することができる。ＬＧＡタイプのＣＳＰでは、実装基板側に半田が形成され、パッケージが実装される。
【００２３】
また、ＢＧＡタイプでは、実装基板に実装する際、実装基板側及びチップ支持基板側に半田が形成されるため、半田量の多い接合部を形成することができ、熱応力の耐量が比較的高く、信頼性のより高い電極を形成することができるという点で好ましい。
【００２４】
また、第１及び第２のチップ支持基板を用いた例を記載したが、第１のチップ支持基板と第２のチップ支持基板の間に、第３のチップ支持基板が形成されていてもかまわない。このとき、第３のチップ支持基板の熱膨張係数は、第１及び第２のチップ支持基板の熱膨張係数の間の大きさである。すなわち、上から半導体チップ＜第１のチップ支持基板＜第３のチップ支持基板＜第２のチップ支持基板＜実装基板の順に熱膨張係数が大きくなるように形成する。したがって、第１のチップ支持基板は、半導体チップの熱膨張係数により近い材料で構成し、第２のチップ支持基板は、実装基板の熱膨張係数により近い材料で構成し、第３のチップ支持基板は、第１及び第２のチップ支持基板の熱膨張係数の間の大きさの材料で構成しているため、半導体チップ、チップ支持基板、実装基板との熱膨張係数の差をさらに緩衝し、熱膨張係数の差に起因して発生する基板やバンプ電極のそりやクラックを低減することができる。
【００２５】
【発明の効果】
以上詳述したように、本発明によれば、基板のそりや外部端子のクラックを低減することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態に係る半導体装置を示す要部断面図である。
【図２】従来の技術の半導体装置を示す要部断面図である。
【図３】従来の技術の他の半導体装置を示す要部断面図である。
【符号の説明】
１０１…第１のチップ支持基板
１０２，４０２…ダイボンド材
１０３，４０３…半導体チップ
１０４…第２のチップ支持基板
１０５，４０４…ワイヤ
１０６，４０５…第１の配線層
１０７，４０６…コンタクト
１０８，４０７…第２の配線層
１０９，４０８…バンプ
１１０，４０９…封止体
１１１，４１０…実装基板[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device such as a CSP structure, and more particularly to a structure of a chip supporting substrate that supports a semiconductor chip mounted on a package.
[0002]
[Prior art]
In a semiconductor device having a semiconductor chip on which a semiconductor integrated circuit or the like is formed, a bump electrode made of solder or the like is provided as an external terminal, and as an example of a semiconductor device having a chip supporting substrate for supporting the semiconductor chip, a CSP (Chip Size Package) is used. ) Are known.
[0003]
FIG. 2 shows a conventional semiconductor device. A semiconductor chip 403 is mounted on a chip supporting substrate 401 made of a ceramic substrate via a die bonding material 402. On the semiconductor chip 403, a semiconductor integrated circuit and the like are formed. A connection electrode (not shown) formed on the semiconductor chip 403 is connected to a first wiring layer 405 formed on the chip support substrate 401 via a wire 404. The wire 404 supplies a power supply potential or a ground potential from the first wiring layer 405 to the semiconductor chip 403.
[0004]
The first wiring layer 405 formed on the chip support substrate 401 is connected to a second wiring layer 407 formed below the chip support substrate 401 via a contact 406 formed on the chip support substrate 401. ing. On the second wiring layer 407, a bump electrode 408 is formed as an external terminal. The semiconductor chip 403 is sealed with a sealing body 409 such as a resin, and the chip supporting substrate 401 and the mounting substrate 410 are connected via the bump electrodes 408. Patent Literature 1 and Patent Literature 2 are known as techniques related to this type of semiconductor device.
[0005]
Patent Document 1 discloses a method of avoiding concentration of stress on a bump electrode by disposing a stress relaxation portion (mold resin) having a thermal expansion coefficient closer to a mounting substrate than a semiconductor chip under a semiconductor chip. Has been described.
[0006]
Further, in Patent Document 2, by forming a coating layer made of a thermosetting resin having a larger coefficient of thermal expansion than the sealing member on the back surface of the ceramic insulating substrate, a compressive stress is also generated on the back surface of the insulating substrate, It describes a method of preventing deformation of the insulating substrate due to a difference in thermal expansion coefficient between the sealing member of the package and the insulating substrate and maintaining a stable connection state.
[0007]
[Patent Document 1]
JP 2001-217261 A (FIG. 3)
[Patent Document 2]
JP 2000-340707 A (FIG. 1)
[0008]
[Problems to be solved by the invention]
In the semiconductor device formed as described above, the semiconductor chip, the chip supporting substrate, and the mounting substrate have different thermal expansion coefficients. Generally, the coefficient of thermal expansion of a semiconductor chip is about 2.6 to 3.6 ppm / ° C., and the coefficient of thermal expansion of a mounting board is about 20 to 25 ppm / ° C. Since the difference between the thermal expansion coefficients of the semiconductor chip and the mounting substrate is large, the thermal expansion coefficient of the chip supporting substrate is 7 to 15 ppm / ° C. so as to be a value between the thermal expansion coefficients of the semiconductor chip and the mounting substrate. Formed in the degree.
[0009]
As shown in FIG. 2, when the thermal expansion coefficient of the chip supporting substrate is formed at 7 ppm / ° C. so that the difference between the thermal expansion coefficients of the semiconductor chip and the chip supporting substrate becomes smaller, the thermal expansion coefficients of the chip supporting substrate and the mounting substrate are reduced. In the temperature cycle test, a large thermal stress is applied to the bump electrode, which is a connection portion between the chip supporting substrate and the mounting substrate, causing warpage and cracks, thereby causing a connection failure. The thermal stress applied to the bump electrodes connecting the chip supporting substrate and the mounting substrate is particularly large on the bump electrodes formed on the outer peripheral portion of the chip supporting substrate.
[0010]
Further, as shown in FIG. 3, when the thermal expansion coefficient of the chip supporting substrate is formed at 15 ppm / ° C. so that the difference between the thermal expansion coefficients of the chip supporting substrate and the mounting substrate is reduced, the thermal expansion of the semiconductor chip and the chip supporting substrate is reduced. The coefficient difference becomes large, and in a temperature cycle test, a large thermal stress is applied between the semiconductor chip and the chip supporting substrate, causing warpage and cracks, thereby causing a problem of poor connection.
[0011]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device capable of reducing warpage of a substrate and cracks of external terminals.
[0012]
[Means for Solving the Problems]
One embodiment of the semiconductor device of the present invention for achieving the above object includes a semiconductor chip,
A first chip support substrate that supports the semiconductor chip;
A second chip support substrate having a first region and a second region on a surface, wherein the first chip support substrate is formed on the first region;
A first wiring layer formed on the second region of the second chip support substrate;
And a sealing body for sealing the semiconductor chip,
The thermal expansion coefficient of the first chip support substrate is a magnitude between the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the second chip support substrate.
[0013]
According to one embodiment of the present invention, warpage of a substrate and cracks of external terminals can be reduced.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First Embodiment)
FIG. 1 shows a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a cross-sectional view of a main part of a semiconductor device having a CSP (Chip Size Package) structure. A semiconductor chip 103 is mounted on a first chip supporting substrate 101 made of an alumina-based ceramic substrate via a die bonding material 102. The die bonding material 102 is a conductive resin, an insulating resin, or the like, and is, for example, an Ag paste. On the semiconductor chip 103, a semiconductor integrated circuit and the like are formed.
[0015]
Under the first chip supporting substrate 101, a second chip supporting substrate 104 made of a glass-based ceramic substrate is sintered. The second chip support substrate 104 has a first region and a second region on the surface, and the first chip support substrate 101 is formed on the first region. The second region is formed on the outer periphery of the first region. Here, the alumina-based ceramic is a ceramic mainly composed of alumina, aluminum nitride and the like, and the glass-based ceramic is a ceramic mainly composed of borosilicate glass, lithium silicate glass and the like.
[0016]
A connection electrode (not shown) formed on the semiconductor chip 103 is connected to a first wiring layer 106 formed on a second region of the second chip support substrate 104 via a wire 105. . The wire 105 supplies a power supply potential or a ground potential from the first wiring layer 106 to the semiconductor chip 103. The first wiring layer 106 formed on the second chip supporting substrate 104 is formed below the second chip supporting substrate 104 via the contact 107 formed on the second chip supporting substrate 104. It is connected to the second wiring layer 108. On the second wiring layer 108, a bump electrode 109 composed of a solder ball is formed as an external terminal. The semiconductor chip 103 is sealed with a sealing body 110 such as a resin. Examples of the resin include a thermosetting epoxy resin.
[0017]
Further, the second chip support substrate 104 is connected to the mounting substrate 111 via the bump electrodes 109. The mounting board 111 is usually made of a material that is easy to process such as an epoxy resin containing glass having a large thermal expansion coefficient.
[0018]
The coefficient of thermal expansion of the semiconductor chip 103 is about 2.6 to 3.6 ppm / ° C., the coefficient of thermal expansion of the first chip supporting substrate 101 made of alumina ceramic is about 5 to 7 ppm / ° C., and made of glass ceramic. The thermal expansion coefficient of the second chip support substrate 104 is about 8 to 18 ppm / ° C., and the thermal expansion coefficient of the mounting board 111 is about 20 to 25 ppm / ° C. That is, the semiconductor chips 103 are formed such that the coefficient of thermal expansion increases from the top in the order of the semiconductor chip 103 <the first chip support substrate 101 <the second chip support substrate 104 <the mounting substrate 111. That is, the first and second chip supporting substrates 101 and 104 are formed so that the coefficient of thermal expansion is between the coefficient of thermal expansion of the semiconductor chip 103 and the coefficient of thermal expansion of the mounting substrate 111. Before the mounting substrate is mounted, the coefficient of thermal expansion of the first chip supporting substrate 101 is set to a value between the coefficient of thermal expansion of the semiconductor chip 103 and the coefficient of thermal expansion of the second chip supporting substrate 104. It is formed so that it becomes.
[0019]
Further, the coefficient of thermal expansion of the die bonding material 102 connecting the semiconductor chip 103 and the first chip supporting substrate 101 is slightly larger than that of the semiconductor chip 103, and from the viewpoint of thermal stress due to the difference in the coefficient of thermal expansion. There is no particular problem.
[0020]
The first chip support substrate 101 is made of a material closer to the thermal expansion coefficient of the semiconductor chip, and the second chip support substrate 104 is made of a material closer to the thermal expansion coefficient of the mounting board. The difference in the coefficient of thermal expansion between the chip supporting substrate and the mounting substrate can be further buffered, and the warpage and cracks of the substrate and the bump electrodes caused by the difference in the coefficient of thermal expansion can be reduced. The difference between the thermal expansion coefficients of the first and second chip supporting substrates 101 and 104 is stored as internal stress, but the second chip supporting substrate 104 having a large thermal expansion coefficient is replaced with a first chip having a small thermal expansion coefficient. By forming the substrate so as to be thicker than the supporting substrate 101, a chip supporting substrate which is hardly bent can be formed.
[0021]
Thermal stress applied to the bump electrodes 109 connecting the chip supporting substrate and the mounting substrate is generated particularly concentrated on the bump electrodes formed on the outer peripheral portion of the chip supporting substrate. In the present embodiment, the first and second wiring layers 106 and 108 are formed above and below the outer peripheral portion of the second chip support substrate 104. However, the first and second wiring layers 106 and 108 are assumed to be temporary. Is provided on the first chip supporting substrate 101 and below the second chip supporting substrate 104 so as to bundle the first and second chip supporting substrates, and connects the chip supporting substrate and the mounting substrate. The thermal stress stored inside the first and second chip supporting substrates 101 and 104 is further applied to a portion where the thermal stress generated at that time is concentrated. Therefore, defects such as warpage and cracks may occur, which is not preferable. Therefore, it is preferable that the first and second wiring layers 106 and 108 be provided above and below the second chip support substrate 104 having a relatively small difference in thermal expansion coefficient from the mounting substrate 111.
[0022]
In the present embodiment, an example of a BGA (Ball Grid Array) type CSP in which solder balls are formed on the chip support substrate side and bump electrodes are provided as external terminals formed on the chip support substrate has been described. An LGA (Land Grid Array) type CSP in which no solder ball is provided on the substrate side can be similarly applied. In the LGA type CSP, solder is formed on the mounting substrate side, and a package is mounted.
[0023]
Further, in the BGA type, when mounting on a mounting board, solder is formed on the mounting board side and the chip supporting board side, so that a joint having a large amount of solder can be formed, and the resistance to thermal stress is relatively high. This is preferable in that an electrode having higher reliability can be formed.
[0024]
Also, the example using the first and second chip supporting substrates has been described, but a third chip supporting substrate may be formed between the first chip supporting substrate and the second chip supporting substrate. Absent. At this time, the coefficient of thermal expansion of the third chip supporting substrate is a magnitude between the coefficients of thermal expansion of the first and second chip supporting substrates. That is, the semiconductor chips are formed such that the thermal expansion coefficient increases in the order of semiconductor chip <first chip support substrate <third chip support substrate <second chip support substrate <mounting substrate from the top. Therefore, the first chip support substrate is made of a material closer to the thermal expansion coefficient of the semiconductor chip, the second chip support substrate is made of a material closer to the thermal expansion coefficient of the mounting substrate, and the third chip support substrate Is made of a material having a magnitude between the coefficients of thermal expansion of the first and second chip supporting substrates, so that the difference in the coefficient of thermal expansion between the semiconductor chip, the chip supporting substrate, and the mounting substrate is further buffered, It is possible to reduce warpage and cracks of the substrate and the bump electrodes caused by the difference in thermal expansion coefficient.
[0025]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to reduce warpage of a substrate and cracks of external terminals.
[Brief description of the drawings]
FIG. 1 is a fragmentary cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a main part showing a conventional semiconductor device.
FIG. 3 is a cross-sectional view of a principal part showing another conventional semiconductor device.
[Explanation of symbols]
101: first chip supporting substrates 102, 402 ... die bonding materials 103, 403 ... semiconductor chip 104 ... second chip supporting substrates 105, 404 ... wires 106, 405 ... first wiring layers 107, 406 ... contacts 108, 407 ... Second wiring layers 109 and 408... Bumps 110 and 409.

Claims (7)

半導体チップと、
前記半導体チップを支持する第１のチップ支持基板と、
表面に第１の領域及び第２の領域を有し、前記第１の領域上に前記第１のチップ支持基板が形成された第２のチップ支持基板と、
前記第２のチップ支持基板の前記第２の領域上に形成された第１の配線層と、
前記半導体チップを封止する封止体とを具備した半導体装置であって、
前記第１のチップ支持基板の熱膨張係数は、前記半導体チップの熱膨張係数と前記第２のチップ支持基板の熱膨張係数の間の大きさであることを特徴とする半導体装置。A semiconductor chip,
A first chip support substrate that supports the semiconductor chip;
A second chip support substrate having a first region and a second region on a surface, wherein the first chip support substrate is formed on the first region;
A first wiring layer formed on the second region of the second chip support substrate;
And a sealing body for sealing the semiconductor chip,
The semiconductor device according to claim 1, wherein a thermal expansion coefficient of the first chip support substrate is a magnitude between a thermal expansion coefficient of the semiconductor chip and a thermal expansion coefficient of the second chip support substrate. 前記第２のチップ支持基板下に形成され、前記第２のチップ支持基板に形成されたコンタクトを介して、前記第１の配線層と接続された第２の配線層と、
前記第２の配線層と接続された外部端子とをさらに具備したことを特徴とする請求項１に記載の半導体装置。A second wiring layer formed below the second chip supporting substrate and connected to the first wiring layer via a contact formed on the second chip supporting substrate;
The semiconductor device according to claim 1, further comprising an external terminal connected to the second wiring layer. 前記外部端子に接続された実装基板をさらに具備し、
前記第１及び第２のチップ支持基板の熱膨張係数は、前記半導体チップの熱膨張係数と前記実装基板の熱膨張係数の間の大きさであることを特徴とする請求項２に記載の半導体装置。Further comprising a mounting board connected to the external terminal,
3. The semiconductor according to claim 2, wherein the first and second chip supporting substrates have a coefficient of thermal expansion between a coefficient of thermal expansion of the semiconductor chip and a coefficient of thermal expansion of the mounting substrate. 4. apparatus. 前記第２の領域は、前記第１の領域の外周部であることを特徴とする請求項１乃至３のいずれか一項に記載の半導体装置。4. The semiconductor device according to claim 1, wherein the second region is an outer peripheral portion of the first region. 5. 前記第１のチップ支持基板は、アルミナ系セラミックスであり、前記第２のチップ支持基板は、ガラス系セラミックスであることを特徴とする請求項１乃至４のいずれか一項に記載の半導体装置。5. The semiconductor device according to claim 1, wherein the first chip support substrate is made of alumina ceramics, and the second chip support substrate is made of glass ceramics. 6. 前記外部端子は、バンプ電極であることを特徴とする請求項２または請求項３に記載の半導体装置。The semiconductor device according to claim 2, wherein the external terminal is a bump electrode. 前記第１の配線層と前記半導体チップは、接続部材を介して接続されていることを特徴とする請求項１乃至６のいずれか一項に記載の半導体装置。The semiconductor device according to claim 1, wherein the first wiring layer and the semiconductor chip are connected via a connection member.
JP2003046802A 2003-02-25 2003-02-25 Semiconductor device Pending JP2004259798A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013187347A (en) * 2012-03-08 2013-09-19 Mitsubishi Electric Corp Substrate connection structure and substrate module
US9520544B2 (en) 2014-09-30 2016-12-13 Nichia Corporation Light source including ceramic substrate mounted on mounting substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013187347A (en) * 2012-03-08 2013-09-19 Mitsubishi Electric Corp Substrate connection structure and substrate module
US9520544B2 (en) 2014-09-30 2016-12-13 Nichia Corporation Light source including ceramic substrate mounted on mounting substrate
US10833235B2 (en) 2014-09-30 2020-11-10 Nichia Corporation Light source, method of manufacturing the light source, and method of mounting the light source

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