JP2004253402A - Electrostatic chuck - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrostatic chuck that makes a chucked-wafer releasing process easier and, in addition, minimizes the occurrence of particles on the rear surface of a wafer. <P>SOLUTION: This electrostatic chuck is formed in a bipolar type or unipolar type and has an insulating block 1 provided with a plurality of embossments 2 on its upper surface. Thin metallic electrodes 3 are respectively provided on the embossments 2 and connected to each other through a metallic wire 5 connected to a DC voltage supplier 6. In addition, thin dielectric layers 4 are respectively provided on the metallic electrodes 3. Moreover, a metallic plate 8 covers the upper surface of the insulating block 1 except the positions of the embossments 2. The metallic plate 8 is set in an electrically grounded state or electrically floating state and electrically insulated from the metallic electrodes 3. The insulating block 1 having the above-described structure is disposed on a metallic block 9. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
[Industrial applications]
The present invention relates to an electrostatic chuck apparatus, and more particularly, to use in plasma-assisted or unassisted plasma-assisted or unassisted wafer processing in semiconductor device manufacturing in the semiconductor industry to electrostatically clamp a wafer. And an electrostatic chuck device.
[0002]
[Prior art]
Clamping the wafer over the electrodes while the semiconductor wafer is being processed is important for controlling the temperature of the wafer. Wafer clamping can be achieved in two different ways. One method is mechanical clamping, in which the wafer is mechanically pressed from above against an O-ring on the electrode. Another method is electrostatic clamping, where electrostatic force is used to clamp the wafer over the electrodes. At present, mechanical clamps are generally not used because of particle contamination on the top surface of the wafer. On the other hand, electrostatic clamping is better and most popular for clamping wafers. However, this method also has some technical difficulties that still need to be improved. In particular, the generation of particles on the back surface (back surface) of the wafer and the ease of removing the wafer require further technical progress. These problems will be explained with reference to FIGS. 5, 6, 7, and 8.
[0003]
There are two types of electrostatic chucks (ESCs), called unipolar ESCs and bipolar ESCs. The operation of the unipolar ESC requires plasma over the entire surface of the wafer. The plasma creates the electrical connection necessary to create an electrostatic force between the wafer and ground. However, bipolar ESCs operate without the presence of plasma. Therefore, they can be used in a plasma process, as well as in the processing of other wafers where no plasma is present. The problems associated with the conventional ESC are explained using the unipolar ESC shown in FIGS. 5A, 5B and 5C.
[0004]
FIG. 5A shows a schematic configuration diagram of one conventional unipolar ESC, FIG. 5B shows a top view of the ESC, and FIG. 5C is an enlarged cross-sectional view at a location marked by the letter “A” in FIG. 5A. Is shown.
[0005]
The ESC 80 shown in FIGS. 5A, 5B, and 5C includes a metal electrode 51, a dielectric layer 53 on the metal electrode 51, an insulating block 54, and a metal shield 52 covering most of the bottom and side surfaces of the insulating block 54. It is composed of The metal electrode 51 is electrically insulated from other parts of the hardware by being placed on the insulating material 54. The thickness of the metal electrode 51 is not critical and can be in the range of a few micrometers to a few centimeters. The metal electrode 51 can be connected to either the DC voltage supply 55 or the ground via the switch unit 70.
[0006]
Usually, Al ₂ O ₃ , AlN, polyimide or the like is adopted as a material for the dielectric layer 53. The thickness and resistance characteristics of the dielectric layer 53 have a great influence on the efficiency of clamping and unclamping (or unclamping) of the wafer. However, the thickness of the dielectric layer 53 is not critical, and is typically around 100 m. A plurality of embosses 57 are formed on the upper surface of the dielectric layer 53. When the wafer 58 is placed on the ESC, the backside of the wafer contacts only the emboss 57. The height of the emboss 57 is 5 25 from m m. Because of these embosses 57, there is a space 59 between the wafer 58 and the dielectric layer 53, which space is usually filled with an inert gas for better heat transfer between the wafer 58 and the ESC 80. ing.
[0007]
During operation, the metal electrode 51 is connected to a DC voltage supply 55 to provide a suitable DC (direct current) voltage. At this time, as shown in FIG. 5A and FIG. 5C, there is a dielectric layer 53 between the metal electrode 51 on which electric charges are deposited on the metal electrode 51 and the silicon (Si) wafer 58. , An opposite charge is induced. Opposite polarity charges on wafer 58 and ESC 80 create an electrostatic force, which causes wafer 58 to be immobilized on ESC 80.
[0008]
In addition, here, Patent Document 1 is cited as a conventional technique.
[0009]
[Patent Document 1]
US Patent No. 5,530,616
[Problems to be solved by the invention]
There are problems with the generation of particles and adhesion to the backside of the wafer. When a DC voltage is applied to the metal electrode 51, charges accumulate on the metal electrode 51. However, these charges are moved to the upper surface of the dielectric layer 53 by the presence of the strong electric field E ₁ between the wafer 58 and the metal electrode 51. This is shown schematically in FIG. The transfer of charges to the upper surface of the dielectric or insulating layer 53 is likewise based on the fact that the dielectric layer 53 is not usually a perfect insulator. Further, the dielectric material 53 may be intentionally doped with impurities for the purpose of reducing the electrical resistance characteristics. The end result is that charges accumulate on the top surface of the dielectric layer 53 as shown in FIG.
[0011]
On a microscopic scale, the lower surface of the silicon wafer 58 and the upper surface of the dielectric layer 53 have rough surfaces. Therefore, the actual contact between the wafer 58 and the dielectric layer 53 has been considered at a few places, as shown in FIG. The separation between the wafer 58 and the dielectric layer 53 is limited by the thickness of the vacuum or air pocket 61 between them. That is, the distance between the opposite charges is very small. This results in the creation of a very strong attractive force between the wafer 58 and the ESC 80. The generated electrostatic force is too much stronger than actually required for clamping the wafer. This very strong force causes particles 56 to be generated due to scraping of the silicon wafer 58 and / or the dielectric layer 53 due to friction as shown in FIG.
[0012]
Some of these particles 56 quickly adhere to the backside of the wafer. Other particles 56 fall from the emboss 57 and accumulate on the surface of the dielectric layer 53. This is shown in FIG. Due to the steps repeated for the silicon wafer 58 on the ESC, the number of particles 56 accumulated on the dielectric layer 53 increases and begins to adhere to the backside of the wafer. Particle adhesion to the backside of the wafer occurs for two reasons. The first reason is that these accumulated particles 56 are charged when a DC voltage is applied to the metal electrode 51. Due to these induced charges, the particles 56 adhere to the back surface of the wafer by electrostatic force. The second mechanism is that the particles 56 begin to float due to the flow of the inert gas blown through the emboss 57. The charged particles 63 easily adhere to the back surface of the wafer by electrostatic force at that time.
[0013]
Conventional ESC has other disadvantages. It is the dechucking of the wafer. For the charge deposited on the top surface of the dielectric layer 53, the electric field E ₁ between the wafer 58 and the metal electrode 51 is reduced. The electric field E ₂ between the upper surface and the silicon wafer 58 of the dielectric layer 53 is increased instead. Thus, the enhancement of the charge on the upper surface of the dielectric layer 53 decreases with time. This presents a problem when unclamping (removing), even if it does not cause any problems with clamping the wafer using electrostatic force. This is because when the metal electrode 51 is connected to ground for removal of the wafer, the charge on the upper surface of the dielectric layer 53 cannot return to the metal electrode 51 immediately. The return flow of the charges to the metal electrode 51 changes depending on the electric resistance characteristics of the dielectric layer 53. In order to facilitate the return flow of charges to the metal electrode 51, the dielectric layer 53 is doped with impurities for reducing its electric resistance characteristics. However, with the return flow of charge to the metal electrode 51, the electric field in the dielectric layer 53 is weakened, and thus the return flow of the charge also becomes progressively slower over time as well. Thus, complete neutralization of the dielectric layer 53 by the return flow of electric charge requires a considerable time. Therefore, rapid dechucking of the wafer cannot be achieved.
[0014]
SUMMARY OF THE INVENTION An object of the present invention is to provide an electrostatic chuck device capable of minimizing generation of particles on the back surface of a wafer and simplifying a wafer removal process.
[0015]
[Means for Solving the Problems]
The electrostatic chuck device according to the present invention is configured as follows to achieve the above object.
[0016]
An electrostatic chuck device used to place and clamp a wafer includes an insulating block. The upper surface of the insulating block has a plurality of embosses. A thin metal electrode is placed on each emboss. All metal electrodes are preferably connected together by at least one metal wire connected to at least one DC voltage supply. A thin dielectric layer is provided on each of the metal electrodes. The metal plate covers the top surface of the insulating block except where the emboss is present. The metal plate is in an electrically grounded or electrically floating state and is electrically insulated from the metal electrode. The insulating block having the above structure is disposed on the metal block.
[0017]
In the above electrostatic chuck device, all of the metal electrodes are preferably connected together by a metal wire connected to one DC voltage supply, preferably as a unipolar type.
[0018]
In the above electrostatic chuck device, the plurality of metal electrodes are divided into two groups as a bipolar type, and one group of metal electrodes is connected to one of the DC voltage supply through one of the metal wires. On the other hand, the other group of electrodes is connected to the other of the DC voltage supply through the other of the metal wires.
[0019]
In the above-described electrostatic chuck device, the metal block preferably has a cooling mechanism or a heating mechanism to maintain the temperature thereon at a desired temperature.
[0020]
In the above electrostatic chuck, the metal block is preferably supplied with an rf current (high frequency current) operating at a frequency preferably in the range of 100 KHz to 100 MHz.
[0021]
According to the ESC of the present invention for clamping a semiconductor wafer over an electrode, a plurality of embossments are formed on the top surface of an insulator or dielectric block. In the dielectric block, the emboss is composed of a metal electrode and a thin dielectric layer on the metal electrode, and the metal plate covering the upper surface of the ESC is in an electrically insulating state or a ground state. The above arrangement reduces or eliminates particles adhering to the backside of the wafer and facilitates dechucking of the wafer.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments will be described with reference to the accompanying drawings. Through this description of the embodiments, the details of the invention will be apparent.
[0023]
A first embodiment of the present invention will be described with reference to FIGS. 1A, 1B and 1C. For the sake of simplicity, in the first embodiment, a unipolar ESC is assumed. A cross-sectional view of the ESC of the first embodiment is shown in FIG. 1A, and an enlarged cross-sectional view of a portion denoted by “B” is shown in FIG. 1B.
[0024]
The main part of the ESC 30 is made of the insulating block 1. The planar shape of the insulating block 1 is preferably circular. A plurality of embosses 2 are present on the upper surface of the insulating block 1. The height of emboss 2 is not important, It ranges from m to several millimeters. The horizontal cross-sectional shape of the emboss 2 is usually circular. However, different cross-sectional shapes can be selected for embossing. If the cross-sectional shape of the emboss is circular, the diameter of the emboss 2 is usually in the range of 1 mm to 10 mm. The number of embossments and the spacing between embossments 2 are not important.
[0025]
FIG. 1B shows an enlarged longitudinal sectional view of the emboss 2. Each emboss 2 has a metal electrode 3 and a thin dielectric layer 4 on its upper surface. The thicknesses of the metal electrode 3 and the thin dielectric layer 4 are not important, and basically depend on the overall height of the embossment 2. The total height of the emboss is indicated by the letter "h" in FIG. 1B. The diameter of the metal electrode 3 is equal to or smaller than the diameter of the emboss 2. If the diameter of the metal electrode 3 is smaller than the diameter of the emboss, the metal electrode 3 is embedded in the embossed top surface of the insulating block 1. This structure is shown in FIG. 1C. All metal electrodes 3 provided on the embossment of the insulating block 1 or provided in the embossment are connected together by a metal wire 5 and through the metal wire 5 to a DC voltage supply 6. The metal wire 5 is wired inside the insulating block 1. Therefore, each of the metal electrodes 3 can be provided with an appropriate DC voltage.
[0026]
The material of the thin dielectric layer 4 and the material of the insulating block 1 may or may not be the same. In general, a material with lower resistance is better for the thin dielectric layer 4. Usually, the thickness of the dielectric layer 4 is preferably as thin as possible. less than m. A thin dielectric layer 4 having a low resistance simplifies the wafer dechucking process. This will be explained later.
[0027]
A metal plate 8 is fixed on the upper surface of the insulating block 1. The upper surface of the insulating block 1 is covered with a metal plate 8 except for the emboss 2. This is shown schematically in FIGS. 1A, 1B, 1C. Each emboss 2 protrudes through a corresponding hole formed in the metal plate 8. The thickness of the metal plate 8 is not important, It is varied from m to several millimeters. This metal plate 8 is either electrically grounded or in a floating state. The electrical circuit for connecting the metal plate 8 to ground is not shown in FIG. 1A. 1A and 1C, the metal plate 8 is shown as being grounded.
[0028]
The above-described composite structure of the ESC 30 is disposed on the metal block 9. The metal block 9 has a cooling or heating device. For example, the metal block 9 shown in FIG. 1A includes a cooling device formed by a passage 16 for the flow of a cooling medium. The passage 16 has a cooling medium inlet 14 and a cooling medium outlet 15. The thickness of the metal block 9 is not important and is usually in the range of 1 cm to 10 cm. The metal block 9 is electrically insulated from the rest of the hardware by covering its bottom and side surfaces with an insulating material 11. Furthermore, the outer bottom and side surfaces of the insulating material 11 and the outer peripheral edge of the insulating block 1 are covered by a metal shield 12. The metal block 9 may or may not be supplied with the rf current from the rf power supply 10. This configuration is shown, for example, in FIG. If an rf current is provided to the metal block 9, the frequency of the rf current is not critical and lies in the range of 1 KHz to 10 MHz.
[0029]
Wafer clamping mechanisms have already been described in detail in the prior art. The same electrostatic force is used for clamping the wafer 7 in the ESC 30 of the first embodiment. The wafer 7 is placed on the insulating block 1. When the metal electrode 3 is provided with a DC bias voltage, charges accumulate on the metal electrode 3 and the wafer surface as shown in FIG. The charge on the metal electrode immediately moves to the surface of the thin dielectric layer 4 because the dielectric layer 4 is made of a low resistance material. Therefore, on each embossment 2, an electrostatic force is generated between the wafer 7 and the thin dielectric layer 4, which results in clamping the wafer 7.
[0030]
Here, it should be noted that the electrostatic force for clamping the wafer 7 is generated only on the embossment 2. There are no electrostatic forces on other areas of the surface of the ESC. Because all other areas of the ESC 30 are covered by the metal plate 8 except for the embossed surface area, which is electrically grounded or floating. Therefore, the wafer 7 is clamped only by the electrostatic force generated between the emboss 2 and the wafer 7.
[0031]
In the ESC 30, the thickness of the dielectric layer 4 on the metal electrode 3 is very small. For example, it can be as thin as 100 nm. Therefore, an increase in electrostatic force with a change in time due to the movement of charge through the thin dielectric layer 4 does not produce a significant change. Furthermore, since the dielectric layer 4 is so thin, the transfer of charge to the top surface of the thin dielectric layer 4 is considered to be completed within a very short time interval. Therefore, the required voltage applied to generate the required electrostatic force can be calculated more accurately. Furthermore, this force can be considered to be almost constant over time. This prevents the generation of very strong electrostatic forces and thus reduces the generation of particles.
[0032]
A second reason for the reduction of particle contamination in the ESC 30 is described below. As mentioned earlier, the entire top surface, except for the surface area where the embossment is present, is made of metal plate 8, which is in electrical ground or floating. Assume that the metal plate is in an electrically grounded state. In this state, the particles on the top surface of ESC 30 will not be charged because it is on a grounded metal surface. Therefore, these particles cannot adhere to the backside of the wafer due to electrostatic forces. If the metal plate 8 on the top surface of the ESC 30 is in a floating state, the particles on that surface will not be charged again. This is because there is no path for the flow of charge to the particles. Therefore, adhesion of particles to the back surface of the wafer is effectively prevented by the configuration of the ESC according to the first embodiment.
[0033]
The ESC configuration described above has other advantages. The height of the embossment 2, indicated by "h", can be increased to several millimeters. The reason is that there is no role for the metal plate 8 in creating electrostatic force and clamping the wafer 7. The clamping of the wafer is only caused by the electrostatic forces generated between the wafer 7 and the metal electrode 3, said electrostatic forces being very close to the wafer 7. The distance between the particles and the back side of the wafer is increased by increasing the height of the emboss 2. Therefore, higher attraction electrostatic forces are required to deposit particles on the backside of the wafer. Particles are very small, eg 1 Since it is smaller than m, higher charge accumulation on the particles is not expected. Therefore, increasing the height of the emboss reduces the particles that adhere to the backside of the wafer.
[0034]
Similarly to the above-described conventional ESC, when a DC bias voltage is applied to the metal electrode 3, charges are accumulated on the upper surface of the dielectric layer 4. However, the thickness of the dielectric layer 4 is very small, and the resistance is a low value. Therefore, when the metal electrode 3 is electrically grounded for de-chucking of the wafer by a switch section (for example, 6a in FIG. 1) added to the DC voltage supply 6, the accumulated charges are recharged. Is immediately neutralized by this process. In addition, the instantaneous application of an opposite DC voltage to the metal electrode 3 by using another DC voltage supply (eg 106 in FIG. 1) further enhances the reflow of charge to the metal electrode. Thus, this configuration facilitates the process of dechucking the wafer.
[0035]
Next, a second embodiment will be described with reference to FIG. Here, a configuration of a bipolar ESC is shown. The metal electrode 3 in this embodiment is divided into two groups, a group in a central region and a group in a peripheral region. The two groups of metal electrodes 3 are each connected to two different DC power supplies 6,13. A group in the peripheral region of the metal electrode 3 is supplied with a positive voltage by the DC power supply 6, and a group in the other central region of the metal electrode 3 is supplied with a negative voltage by the DC power supply 13. The appropriate voltage to be applied to each group of metal electrodes is calculated in a similar manner as that described in the first embodiment. Except for the differences described above regarding the configuration of the metal electrodes, all other hardware configurations are the same as those described in the first embodiment. Therefore, other hardware is not described here.
[0036]
The ESC of the second embodiment also provides all of the advantages mentioned in the first embodiment. In addition, the bipolar ESC can be employed even when plasma does not exist over the entire surface of the wafer.
[0037]
【The invention's effect】
According to the EPC of the present invention, particles adhering to the back surface of the wafer can be reduced, and the chuck release of the wafer can be easily performed.
[Brief description of the drawings]
FIG. 1A is a longitudinal sectional view of an ESC according to a first embodiment.
FIG. 1B is an enlarged view of an edge portion “B” in FIG. 1;
FIG. 1C is an enlarged view showing another configuration of the metal electrode provided inside the emboss.
FIG. 2 is a longitudinal sectional view showing a modification of the first embodiment including an rf power supply added to a metal block.
FIG. 3 is an enlarged cross-sectional view showing the distribution of charges on the upper surface of the ESC.
FIG. 4 is a longitudinal sectional view of an ESC according to a second embodiment.
FIG. 5A is a longitudinal sectional view of a conventional unipolar type ESC.
FIG. 5B is a plan view of the conventional ESC shown in FIG. 5A.
FIG. 5C is an enlarged view showing a portion labeled “A” in FIG. 5A.
FIG. 6 is an enlarged cross-sectional view showing charge accumulation near the top surface of the dielectric layer and the back surface of the wafer.
FIG. 7 is an enlarged sectional view showing the nature of the contact between the backside of the wafer and the dielectric layer.
FIG. 8 is an enlarged vertical sectional view showing a place where particles accumulate in a conventional ESC.
[Description of reference numerals]
DESCRIPTION OF SYMBOLS 1 Insulation block 2 Emboss 3 Metal electrode 4 Dielectric layer 5 Metal wire 6 DC voltage supply 7 Wafer 8 Metal plate 9 Metal block 10 Rf generator 11 Insulation material 13 DC voltage supply 30 ESC (electrostatic chuck)

Claims (5)

An electrostatic chuck device on which a wafer is placed and clamped.
An insulating block having a plurality of embosses on the upper surface,
A thin metal electrode disposed on each of said embosses, wherein all metal electrodes are connected together by at least one metal wire connected to at least one DC (direct current) voltage supply;
A thin dielectric layer disposed on each of the metal electrodes;
A metal plate covering an upper surface of the insulating block except for the embossed position, wherein the metal plate is in an electrically grounded state or in an electrically floating state, and is electrically insulated from the metal electrode. And a metal block on which the insulating block is disposed,
An electrostatic chuck device comprising: The electrostatic chuck device according to claim 1, wherein all the metal electrodes are unipolar, and are connected together by a metal wire connected to one DC voltage supply. The plurality of metal electrodes are divided into two groups, and as a bipolar type, one group of the metal electrodes is connected to one of the DC voltage supply devices via one of the metal wires, while the other is connected to the other one. 2. The electrostatic chuck device according to claim 1, wherein the electrodes of the group are connected to the other of the DC voltage supplies via the other of the metal electrodes. 4. The electrostatic chuck device according to claim 1, wherein the metal block has a cooling mechanism or a heating mechanism for maintaining a desired temperature on the metal block. 5. 4. The electrostatic chuck device according to claim 1, wherein the metal block is supplied with an rf current operating at a frequency in a range of 100 kHz to 100 MHz. 5.

Images