JPH09213778A - Semiconductor wafer processor and semiconductor wafer processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To apply a sufficiently high voltage to a wafer even in plasma processing using plasma with high density by a method wherein, by using an electrostatic chuck provided with a bias electrode coming into contact with the wafer, an AC voltage is applied to the bias electrode via a capacitor, etc. SOLUTION: This processor an electrostatic chuck 5 comprising an insulative base to which a wafer 6 is mounted, a bias electrode 5b coming into contact with the wafer 6 provided on a face of the base, and an electrostatic electrode 5c embedded under a face of the base. Further, the processor comprises an AC power supply 12 for applying an AC voltage to the bias electrode 5b, a capacitor 10 connected between the AC power supply 12 and the bias electrode 5b, and DC power supplies 7, 8 for applying a DC voltage to the electrostatic electrode 5c. For example, the bias electrode 5b is arranged in a center part of the base and the electrostatic electrode 5c is disposed in the periphery of the bias electrode 5b. Further, the capacitor 10 is made as a variable capacitance type capacitor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer processing apparatus that holds a wafer by an electrostatic chuck (wafer susceptor) and performs plasma processing on the wafer, and a semiconductor wafer using the semiconductor wafer processing apparatus. Regarding processing method.

[0002]

2. Description of the Related Art In a process of etching a wafer using plasma or a process of forming a thin film, as a method of holding the wafer, a method of vacuum-adsorbing the wafer by an electrostatic chuck having an exhaust hole on its surface, There are a method of mechanically clamping the wafer and a method of electrically attracting the wafer by an electrostatic chuck. Among them, the method using the electrostatic chuck is excellent in the temperature controllability of the wafer because the chuck is not in contact with the device forming surface of the wafer, it can be used in vacuum, and the adsorption force acts on the entire surface of the wafer. It is superior to other methods such as being present.

FIG. 14 (a) is a schematic sectional view showing a conventional electrostatic chuck (single-plate electrostatic chuck), and FIG. 14 (b) shows another conventional electrostatic chuck (dipolar electrostatic chuck). It is a schematic sectional view. In FIGS. 14A and 14B, 26 indicates a wafer. Single plate electrostatic chuck 21
As shown in FIG. 14A, is composed of a disk-shaped base 21a made of an insulating material and an electrostatic electrode 21b embedded in the base 21a. Then, the electrostatic electrode 21b is connected to the DC power source 22, and the DC power source 22
Causes a positive voltage to be applied.

On the other hand, the bipolar electrostatic chuck 23 is shown in FIG.
As shown in (b), a disc-shaped base 2 made of an insulating material.
3a and two semicircular electrostatic electrodes 23b embedded in the base 23a. Then, a positive voltage is applied from the DC power supply 24 to the one electrostatic electrode 23b, and a negative voltage is applied from the DC power supply 25 to the other electrostatic electrode 23b.

Thus, the conventional electrostatic chucks 21 and 2 are
3 has one or a plurality of electrostatic electrodes 21b and 23b. When a positive or negative voltage is applied to the electrostatic electrodes 21b and 23b, the wafer 26 and the electrostatic electrodes 21b and
The Coulomb force and the Johnson-Rahbek force act on 23b and the wafer 26 can be attracted to the chuck even in plasma.

By the way, most of the conventional plasma generators have a plasma density of about 10 ⁸ to 10 ⁹ / cm. In plasma, electrons have a smaller mass and move more easily than ions, so the wafer 26 is negatively charged. Therefore, in the single-plate electrostatic chuck, the wafer 26 can be attracted by applying a positive voltage to the electrostatic electrode. Further, in the bipolar electrostatic chuck, since positive and negative voltages are applied to the two electrostatic electrodes 23b, respectively, the wafer 26 can be attracted to the electrostatic chuck even before the plasma processing is started. . In this case, usually, the absolute values of the voltages of the one electrostatic electrode 23b and the other electrostatic electrode 23b are set to be the same. That is, if + 2000V is applied to one electrostatic electrode 23b, -2000V is applied to the other electrostatic electrode 23b.

FIG. 15 is a schematic view showing a conventional parallel plate type plasma generator equipped with the above-mentioned bipolar electrostatic chuck. The high frequency electrode 31 and the counter electrode 32 are arranged to face each other in the vertical direction. The radio frequency (RF) electrode 31 is connected to a radio frequency power source 34 via a matching circuit 33, and the radio frequency power source 34 supplies the radio frequency power.
Further, the counter electrode 32 is connected to the ground.

The electrostatic chuck 23 is mounted on the high frequency electrode 31. As described above, one electrostatic electrode 23b of the electrostatic chuck 23 is connected to the DC power supply 24 to apply a positive voltage, and the other electrostatic electrode 23b is connected to the DC power supply 25 to apply a negative voltage. To be done. The high frequency electrode 31 and the counter electrode 32 are both housed in a chamber (not shown).

In the plasma generator configured as described above, the inside of the chamber is set to, for example, an Ar (argon) atmosphere, and the high-frequency electrode 31 is supplied from the high-frequency power source 34 to the high-frequency electrode 31 via the matching circuit 33.
When the high frequency power of z is supplied, plasma is generated between the high frequency electrode 31 and the counter electrode 32. Due to this plasma, the surface of the wafer 26 is vertically etched (anisotropic etching).

FIG. 16A is a waveform diagram showing a voltage waveform at the high frequency electrode 32 (position A in FIG. 15).
(B) is a waveform diagram showing a voltage waveform on the wafer 26 (position B in FIG. 15). As shown in these drawings, in the potential (B) of the wafer 26, the voltage waveform (A) supplied from the power source 34 is shifted to the negative side. This voltage shift amount is called a self-bias voltage. Self-bias is generated due to the different mobilities of ions and electrons in plasma.

FIG. 17 is an equivalent circuit diagram of the plasma generator shown in FIG. The resistance R corresponds to the resistance of the plasma, the sheath capacitance Cs corresponds to the capacitor composed of the counter electrode 32, the high frequency electrode 31 and the plasma between them, and the blocking capacitance Cb corresponds to the capacitor composed of the high frequency electrode 31 and the wafer 26. ing. In FIG. 17, assuming that the plasma resistance R is extremely small, when the impedance of the sheath capacitance Cs is sufficiently smaller than the impedance of the blocking capacitance Cb (that is, Cb >> Cs),
It can be seen that the wafer is given a large voltage swing.

By the way, in recent years, in order to miniaturize the device and improve the throughput, the plasma density is 10 ¹⁰ / c.
A high-density plasma generator of m or more may be used. As a high-density plasma generator of this kind, EC
There are R (electron cyclotron resonance) device, ICP (inductively coupled plasma generator), helicon, and the like. In this type of high-density plasma generator, the capacitance (sheath capacitance; Cs) between the wafer and plasma increases. This is because the sheath width between the plasma and the wafer that defines Cs is inversely proportional to the 1/2 power of the plasma density. Therefore, in such a high-density plasma generator, Cb >> Cs does not hold, and it becomes difficult to give a sufficient voltage amplitude to the wafer. As a result, there are problems that the etching rate is lowered and it becomes difficult to perform etching perpendicular to the wafer surface.

In order to solve such a problem, a plasma processing apparatus of the type in which a bias voltage is applied to the electrostatic electrodes of the electrostatic chuck has been developed. FIG. 18 is a schematic diagram showing a conventional inductively coupled plasma generator of this system. As shown in FIG. 18, the chamber 41 is composed of a processing chamber 41a that accommodates the wafer 26 to be processed, and a plasma generation chamber 41b that is arranged above the processing chamber 41a and communicates with the processing chamber 41a. And plasma generation chamber 41b
A counter electrode 42 is arranged in the. This counter electrode 42
Are connected to a high frequency power supply 44 via a matching circuit 43.

The wafer 26 is placed on the electrostatic chuck 23 arranged in the processing chamber 41a. One electrostatic electrode 23b of the electrostatic chuck 23 is connected to the positive electrode of the DC power supply 24, and the other electrostatic electrode 23b is connected to the negative electrode of the DC power supply 25. An AC voltage (bias) is applied to the two electrostatic electrodes 23b from an AC power supply 46 via the matching circuit 45.

In this plasma generator, since a bias voltage is applied to the electrostatic electrode 23b, the wafer 26 and the electrostatic electrode 23 which form a blocking capacitance.
The interval of b can be reduced. Therefore, the plasma generator has a larger blocking capacitance than the device shown in FIG. This allows
A high voltage can be applied to the wafer 26.

[0016]

However, FIG.
The plasma processing apparatus having the structure shown in (1) has the following problems. That is, in recent years, it has been desired to further increase the plasma density, and in order to cope with this, it is necessary to further increase the capacitance value of the blocking capacitance. In the conventional plasma generator, the distance between the electrostatic electrode and the wafer is generally set to about 0.5 to 1 mm, but the distance between the two is increased in order to increase the blocking capacitance. Further narrowing, the withstand voltage of the electrostatic chuck decreases,
The electrostatic chuck may be destroyed.

Incidentally, Japanese Patent Application Laid-Open No. 3-95953 proposes an electrostatic chuck provided with electrodes for contacting and biasing the wafer. However, this electrostatic chuck does not apply a high frequency voltage to the wafer. That is, this electrostatic chuck is basically shown in FIG.
The device has the same blocking capacitance as that of the device shown in FIG. 1 and cannot apply a sufficient voltage to the wafer.

Further, Japanese Patent Application Laid-Open No. 4-279044 proposes an electrostatic chuck in which a conductive member is provided on the peripheral edge of a sample in order to control the energy of ions in the plasma. Further, Japanese Patent Application Laid-Open No. 5-67671 proposes an electrostatic chuck provided with an electrode for applying a positive voltage to a wafer. However, even in these electrostatic chucks, the blocking capacitance is formed by the wafer and the conductor inside the chuck, and the above problems cannot be solved.

The present invention was created in view of the problems of the above-mentioned conventional example, and a semiconductor wafer process capable of applying a sufficiently high voltage to a wafer even in a plasma process using high-density plasma. An object of the present invention is to provide an apparatus and a semiconductor wafer processing method.

[0020]

The above-mentioned problems are solved by an insulating substrate on which a wafer is placed, a bias electrode provided on the surface of the substrate and in contact with the wafer, and a static electrode embedded below the surface of the substrate. An electrostatic chuck composed of an electric electrode, an AC power supply for applying an AC voltage to the bias electrode, a capacitor connected between the AC power supply and the bias electrode, and a DC voltage applied to the electrostatic electrode. This is solved by a semiconductor wafer processing apparatus characterized by having a DC power source for applying.

The above-mentioned problems are constituted by an insulating substrate on which a wafer is mounted, a bias electrode provided on the surface of the substrate and in contact with the wafer, and an electrostatic electrode embedded below the surface of the substrate. A semiconductor wafer processing method of holding a wafer by an electrostatic chuck and performing plasma processing on the wafer, wherein a DC voltage is applied to the electrostatic electrode to electrostatically adsorb the wafer, and a capacitor is attached to the bias electrode. This is solved by a semiconductor wafer processing method characterized in that an alternating voltage is applied through the method.

Further, the above-mentioned problems are constituted by an insulating substrate on which a wafer is mounted, a bias electrode provided on the surface of the substrate and in contact with the wafer, and an electrostatic electrode embedded below the surface of the substrate. A semiconductor wafer processing method for holding a wafer by an electrostatic chuck and performing plasma processing on the wafer, wherein a specific potential is applied to the wafer via the bias electrode, and a DC voltage having a reverse potential is applied to the electrostatic electrode. Is applied to attract the wafer to the electrostatic chuck, and a step of applying an AC voltage to the bias electrode via a capacitor is solved.

In the present invention, the electrostatic chuck is provided with a bias electrode which is in direct contact with the wafer, and an AC voltage (bias voltage) is applied to this bias electrode from the bias power supply via the capacitor. In this case, the capacitor acts as a blocking capacitance. Therefore, the capacitance value of the blocking capacitance can be set arbitrarily.

The capacitance value required as the blocking capacitance varies depending on the content of the plasma treatment, the plasma density, etc., but it is generally required to be 200 pF or more. Also, for example, considering that a 6-inch wafer is processed by high-density plasma, the capacitance value of the capacitor is preferably 3000 pF or more. It should be noted that the larger the blocking capacitance is, the easier the matching of the bias power supplies is.

If a variable capacitance type capacitor (variable capacitor) is used as the capacitor, the capacitance value of the blocking capacitance can be adjusted according to the contents of processing. By the way, if the capacitance value of the capacitor is large, electric charges accumulated in the capacitor at the end of the plasma processing may flow to the wafer, and the elements on the wafer in the process of being formed may be destroyed. Therefore, when the variable capacitance type capacitor is used as described above, immediately before the plasma processing is finished, the capacitance value is gradually reduced to reduce the amount of stored electricity, and then the plasma power supply is turned off to stop the plasma generation. Is preferred. When a fixed capacitance type capacitor is used as the capacitor, a switch is provided between the capacitor and the bias electrode, the switch is turned off immediately before the plasma processing is finished, and then the plasma power supply is turned off to generate plasma. Is preferably stopped. As a result, it is possible to reliably prevent destruction of the element due to the electric charge accumulated in the capacitor.

In the present invention, since the bias voltage is directly applied to the wafer via the bias electrode, it is necessary that the wafer and the bias electrode are in reliable contact with each other.
Therefore, by using a conductive rubber having elasticity as a material of the bias electrode or providing an urging member such as a spring for urging the bias electrode to the wafer, the adhesion between the bias electrode and the wafer can be enhanced. preferable.

When two electrostatic electrodes are provided and a positive voltage is applied to one side and a negative voltage is applied to the other side, the potential difference between the wafer voltage and each electrostatic electrode is made equal. The wafer can be sucked with a uniform suction force over the entire surface of the chuck. For example, if the wafer is biased at -500V, applying + 500V to one electrostatic voltage and -1500V to the other electrostatic electrode:
The potential difference between the wafer and each electrostatic electrode is 1000 V, and the wafer can be attracted to the electrostatic chuck with a uniform attracting force over the entire surface, and the temperature controllability can be improved. For this reason, it is preferable to detect the voltage of the wafer by the bias voltage detection means and adjust the positive voltage and the negative voltage applied to the two electrostatic electrodes, respectively, based on the detection result.

In the case of a single-plate type electrostatic chuck, if the wafer is charged in advance, the wafer can be attracted to the electrostatic chuck even before plasma is generated. In the present invention, since the bias electrode and the wafer are in contact with each other while the wafer is placed on the electrostatic chuck,
When a DC voltage is applied to the wafer via the bias electrode, the wafer is charged and can be attracted to the electrostatic chuck even before the plasma processing is started.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. (First Embodiment) FIG. 1 is a schematic diagram showing the structure of an inductively coupled plasma processing apparatus according to the first embodiment of the present invention, and FIG. 2 is a plan view showing an electrostatic chuck of the processing apparatus.
FIG. 3 is a schematic diagram showing the connection between the electrostatic chuck and the power supply.

The chamber 1 is composed of a processing chamber 1a for accommodating a wafer 6 to be processed and a plasma generating chamber 1b which is disposed above the processing chamber 1a and communicates with the processing chamber 1a. The counter electrode 2 is arranged in the chamber 1b. The counter electrode 2 is connected to a radio frequency (RF) power source 4 via a matching circuit 3. Wafer 6
Is placed on the electrostatic chuck 5 arranged in the processing chamber 1a. The electrostatic chuck 5 includes a disk-shaped base 5a made of an insulating material such as ceramics or resin, a circular bias electrode 5b made of a conductive material and arranged at the center of the base 5a, and the base 5 And two fan-shaped electrostatic electrodes 5c embedded under the surface of the. As shown in FIG. 2, the electrostatic electrode 5c is arranged so as to surround the periphery of the bias electrode 5.

The bias electrode 5b can be made to have good adhesion between the electrostatically adsorbed wafer 6 and the bias electrode 5b by forming the bias electrode 5b from a conductive resin (rubber) having elasticity. . When the bias electrode 5b is made of metal, a spring 5d may be provided in the base 5a, and the bias electrode 5b may be urged toward the wafer 6 by the spring 5d, for example, as shown in FIG.

To the bias electrode 5b of the electrostatic chuck 5, a variable capacitance type capacitor 10, a matching circuit 11 and an AC power supply (bias power supply) 12 are connected in this order.
Further, one of the two electrostatic electrodes 5c is connected to the positive electrode of the DC power supply 7, and the other is connected to the negative electrode of the DC power supply 8. Hereinafter, a method for etching the surface of a wafer using the semiconductor wafer processing apparatus according to this embodiment configured as described above will be described.

First, the wafer 6 is placed on the electrostatic chuck 5. After that, a positive voltage (for example, +500 V) is applied from the power source 7 to the one electrostatic electrode 5c, and
From the other to the other electrostatic electrode 5c with a negative voltage (for example, −
1500 V) is applied. As a result, the wafer 6 is electrically attracted to the electrostatic chuck 5. Next, the inside of the chamber 1 is evacuated by a vacuum pump (not shown). afterwards,
A gas such as Ar (argon) is supplied into the chamber 1.
Then, the alternating-current power supply 12 supplies the bias electrode 5b with alternating-current power having a frequency of 100 kHz to 1 MHz, and the high-frequency power supply 4 supplies high-frequency power of, for example, 13.56 MHz to the counter electrode 2 via the matching circuit 3. As a result, the gas in the chamber 1 is turned into plasma,
Ions in the plasma reach the wafer 6 and the surface of the wafer 6 is vertically etched.

In this case, as shown in FIG. 5, a voltmeter 13 for measuring the potential of the bias electrode 6 (that is, the potential of the wafer) is provided to detect the potential difference between the electrostatic electrode 5c on one side and the wafer 6 and the other. It is preferable to adjust the voltage of the AC power supplies 7 and 8 so that the potential difference between the electrostatic electrode 5c and the wafer 6 becomes equal. This allows the wafer to be attracted to the electrostatic chuck with a uniform attraction force over the entire surface,
The temperature of the wafer surface can be made uniform. The potential of the bias electrode 6 in this case means the center voltage (bias voltage) of the AC waveform, as shown in FIG.

Immediately before the etching is finished, the capacitance value of the capacitor 10 is gradually reduced to the minimum capacitance value, and then the high frequency power source 4 and the AC power source 12 are turned off. As a result, it is possible to surely prevent the charge accumulated in the capacitor 10 from flowing to the wafer 6 and destroying the element being formed. In the semiconductor wafer processing apparatus of this embodiment, since the bias electrode 5b is in contact with the wafer 6, the capacitor 10 acts as a blocking capacitance. That is, in the present embodiment, the capacitance value of the blocking capacitance can be determined to be the optimum value by the capacitor 10. Therefore, in plasma processing using high-density plasma, it is possible to increase the impedance of the blocking capacitance and apply a high voltage to the wafer 6.

(Second Embodiment) FIG. 6 shows a second embodiment of the present invention.
It is a schematic diagram which shows the semiconductor wafer processing apparatus which concerns on embodiment of FIG. 6, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. In the present embodiment, the switch 9 and the fixed capacitance type capacitor 1 are provided between the bias electrode 5b of the electrostatic chuck 5 and the matching circuit 11.
0a is connected. In the semiconductor wafer processing apparatus of this embodiment, the switch 9a is turned on when performing the plasma processing. Then, as in the case of the first embodiment, plasma is generated in the chamber 1 to carry out processes such as anisotropic etching of the wafer, and immediately before the bias power supply 12 and the high frequency power supply 4 are turned off, the switch is turned on. Turn off 9a.

Also in this embodiment, since the switch 9a is turned off immediately before the plasma processing is completed, it is possible to prevent the charge accumulated in the capacitor 10a from flowing to the wafer 6 and destroying the element in the process of being formed. It is preferable that the electric charge charged in the capacitor 10a is released to the ground before the next plasma processing is started. (Third Embodiment) FIG. 7 is a schematic view showing a semiconductor wafer processing apparatus according to a third embodiment of the present invention, and FIG. 8 is a plan view showing the electrostatic chuck thereof. Note that this embodiment is an example applied to a semiconductor wafer processing apparatus having a single-plate electrostatic chuck. In addition, in FIG.
The same parts as those in FIG.

The electrostatic chuck 5 includes a disk-shaped base 5a made of an insulating material, a bias electrode 5b made of a conductive material and arranged at the center of the base 5a, and the base 5a.
And a ring-shaped electrostatic electrode 5e embedded in the. As shown in FIG. 8, the electrostatic electrode 5e is arranged concentrically with the bias electrode 5b. The bias electrode 5b is connected to the AC power supply 12 via the variable capacitance type capacitor 10 and the matching circuit 11. The bias electrode 5b is connected to the negative electrode of the DC power supply 16 via the switch 15.

A wafer 6 is produced by this semiconductor wafer processing apparatus.
In the case of performing plasma processing on the wafer 6, first, the wafer 6 is placed on the electrostatic chuck 5, and then the switch 15 is turned on to negatively charge the wafer 6 via the bias electrode 5b. Then, the DC power supply 7 applies a positive voltage to the electrostatic electrode 5c. As a result, the wafer 6 is electrically attracted to the electrostatic chuck 5. Then, the switch 15 is turned off. In this case, even if the switch 15 is turned off, since the wafer 6 is sufficiently negatively charged, the wafer 6 remains electrically attracted to the electrostatic chuck 5.

Then, as in the first embodiment, after the chamber 1 is evacuated by a vacuum pump (not shown),
A gas such as Ar is supplied into the chamber 1. Then, while the high frequency power is supplied from the AC power supply 12 to the bias electrode 5b, the high frequency power having a frequency of 13.56 MHz is supplied from the high frequency power supply 4 to the counter electrode 2 through the matching circuit 3. As a result, the gas in the chamber 1 is turned into plasma, the ions in the plasma reach the wafer 6, and the surface of the wafer 6 is etched.

In this embodiment, the same effect as in the first embodiment can be obtained, and the wafer 6 is negatively charged via the bias electrode 5b before the plasma processing is started. Therefore, even a single plate type electrostatic chuck has an advantage that the wafer can be attracted to the electrostatic chuck before starting the plasma processing. The results of performing plasma processing under various conditions using the semiconductor wafer processing apparatus according to the present invention will be described below.

Example 1 First, the relationship between the capacitance value of the blocking capacitance and the bias voltage applied to the wafer was examined. That is, using the semiconductor wafer processing apparatus of FIG. 1, the capacitance value of the variable capacitance type capacitor 10 is adjusted, or a fixed capacitance type capacitor is used instead of the variable capacitance type capacitor to change the capacitance value of the blocking capacitance Cb. 200pF, 600pF, 1500p
F, 3000 pF or 200 nF. Then, the wafer was plasma-treated. At this time, the connection point between the capacitor 10 and the matching circuit 11 (hereinafter referred to as point A),
The connection point between the bias electrode 5b and the capacitor 10 (hereinafter,
The voltage (referred to as point B) and the voltage (pp voltage) were measured, and the ratio (B / A) between them was obtained. The frequency of the high frequency power supply is 1
The gas introduced into the chamber at 3.56 MHz is Ar (argon), and the pressure is 4 mTorr. The frequency of the bias power supply was 100 kHz, and the input power was adjusted so that the voltage at point A had an amplitude value (pp value) of 1000V. Further, for comparison, in the conventional plasma processing apparatus (conventional example) shown in FIG. 18, the voltage at the point A (the connection point between the matching circuit 45 and the electrostatic electrode 23b) and the point B (the surface of the wafer 26). Was calculated.

In FIG. 9, the horizontal axis represents the plasma generation power, and the vertical axis represents the ratio of the voltage amplitude at the point A to the voltage amplitude at the point B. The block capacitance is 200 pF to 2
It is a figure which shows the relationship between the plasma generation electric power and voltage amplitude ratio at 00 nF. As is apparent from FIG. 9, the conventional device and the blocking capacitance Cb are 1500
When pF or less, B increases with increase in plasma generation power.
The ratio of the voltage at the point / the voltage at the point A becomes small. That is,
In a conventional plasma generator or a plasma generator having a blocking capacitance Cb of 1500 pF or less, only a low voltage is applied to the wafer although a high voltage is supplied by the bias power supply. When the plasma generation power is increased, the plasma density rises in proportion to this. That is, the higher the plasma generation power, the more difficult it is to apply a voltage to the wafer.

On the other hand, when a bias voltage is applied to the wafer via a capacitor of 3000 pF or more, the voltage drop at the blocking capacitance Cb is reduced and a sufficient voltage can be applied to the wafer. From this,
It can be seen that it is preferable to set the value of the capacitor to 3000 pF or more especially when the plasma generation power is large.

(Embodiment 2) Next, whether or not there is a risk of device destruction depending on the method of ending the plasma treatment was examined. That is, the wafer was plasma-processed using the apparatus shown in FIGS. The power supply frequency of the high frequency power supply at this time is 1
3.56 MHz, input power is 2 kW, gas in the chamber is Ar, pressure is 4 mTorr, processing time is 10 minutes, and frequency of bias power supply is 100 kHz. The capacitance value of the variable capacitance type capacitor 10 was adjusted to 200 nF.

Immediately before ending the plasma treatment,
Whether or not there is a risk of element breakdown was examined in the case where the plasma was turned off after the value of the variable capacitance type capacitor 10 was minimized (Example) and the case where the plasma was turned off with 200 nF left (Comparative Example). That is, after the plasma processing, the wafer is pushed up from below the electrostatic chuck by a rod called a lift pin and is separated from the chuck. No abnormalities were observed when the plasma was turned off after the capacitance value of the capacitor 10 was minimized when the wafer was separated from the electrostatic chuck. However, when the plasma was turned off with the capacitance value of the capacitor 10 kept at 200 pF, discharge (sparks, sparks) occurred when the wafer was removed from the electrostatic chuck. This is because electric charges are accumulated in the capacitor during plasma processing, and electric discharge is generated when the wafer is separated from the electrostatic chuck. A large current may flow through the wafer due to such discharge, and the device under fabrication may be destroyed.

In the comparative example, assuming that the self-bias voltage is 500 V when the wafer is released, the capacitor 10 is charged with 500 (V) × 200 (pF) = 1 × 10 ⁻⁴ (C). Accumulated. This charge amount is a sufficient charge amount to generate discharge. Therefore, when the plasma processing is completed, the capacitance of the variable capacitance type capacitor should be reduced, or the plasma power should be turned off after the capacitor and the bias electrode are electrically cut off by a switch. It turns out that is preferable.

Example 3 Next, in a plasma processing apparatus using a bipolar electrostatic chuck, the relationship between the DC voltage applied to each electrostatic electrode and the temperature distribution on the wafer surface was examined.
That is, the following experiment was conducted using the apparatus shown in FIGS. 1 to 3 and the apparatus shown in FIG. Frequency is 13.56M
Plasma was generated using a high frequency power source 4 of Hz. The input power at this time is 2 kW, the gas is Ar, and the pressure is 4 mTor.
r, the plasma treatment time is 1 minute. The frequency of the bias power source 12 is 100 kHz and the self-bias voltage is -500V. The capacitance value of the capacitor 10 was adjusted to 200 pF.

Then, the voltage of the two DC power supplies A and B for applying a voltage to the two electrostatic electrodes is set to the values shown in Table 1 below, the wafer is plasma-processed, and the temperature distribution on the wafer surface immediately after the plasma processing is thermographed. It investigated using.

[0050]

[Table 1]

The results of measuring the temperature distributions of these examples, conventional examples and comparative examples are shown in FIGS. 10 (a) to 10 (d). However, FIG. 10A shows the temperature distribution of Conventional Example 1, and FIG.
0 (b) shows the temperature distribution of the conventional example 2, FIG. 10 (c) shows the temperature distribution of the example, and FIG. 10 (d) shows the temperature distribution of the comparative example.
As is clear from these figures, there is almost no difference between the conventional examples 1 and 2. These are due to the principle of electrostatic attraction. That is, the strength of the electrostatic attraction force is determined by the potential difference between the two conductors (semiconductors) if the distance is the same. In this case, a self-bias voltage of -500V is applied to the wafer. In the case of the conventional example 1, the potential difference between the electrode connected to the DC power supply A and the wafer is 1500 V, and the potential difference between the electrode connected to the DC power supply B and the wafer is 5 V.
00V. That is, there is a distribution of the attraction force within the wafer surface. If the adsorption force has a distribution, the cooling performance of the wafer becomes uneven, and a relatively large temperature variation occurs.

On the other hand, in the case of the embodiment, the potential difference between the electrode to which the DC power supply A is connected and the wafer is 1000 V,
The potential difference between the electrode to which the DC power source B is connected and the wafer is 1000 V, and the potential difference between them is the same. As a result, it is possible to obtain a uniform temperature distribution without uneven suction force on the wafer surface. Further, in the comparative example, the potential difference between the electrode connected to the DC power supply A and the wafer is 0 V, and the potential difference between the electrode connected to the DC power supply B and the wafer is 2000.
V, and the attraction force is significantly different. Therefore, in this comparative example, the variation in temperature is relatively large.

From this, it is possible to measure the bias voltage of the wafer and make the potential difference between one electrostatic electrode and the wafer equal to the potential difference between the other electrostatic electrode and the wafer based on the measurement result. It turns out to be preferable. (Example 4) Next, the relationship between the structure of the electrostatic chuck and the temperature distribution was investigated. That is, the temperature distribution when the wafer was processed using the electrostatic chuck shown in FIG. 2 as an example and the electrostatic chuck shown in FIG. 11 as a comparative example was measured using thermography.

As shown in FIG. 11, the electrostatic chuck 17 of the comparative example has two semi-circular electrostatic electrodes 17c embedded in the central portion of the base 17a and a ring shape surrounding these electrostatic electrodes 17c. And the bias electrode 17b.
Then, as shown in FIG. 12, the matching circuit 11 and the capacitor 1 are connected to the bias electrode 17b from the AC power supply 12.
AC voltage is applied via 0, and one electrostatic electrode 17c
Is applied with a positive voltage from the DC power supply 7, and the other electrostatic electrode 17c is applied with a negative voltage from the DC power supply 8.

Plasma treatment was performed on the wafer using the electrostatic chucks of these Examples and Comparative Examples. The frequency of the high frequency power supply is 13.56 MHz, the input power is 2 kW, the gas is Ar, the pressure is 4 mtorr, and the plasma processing time is 1 minute. The frequency of the wafer bias voltage is 100k.
Hz, self-bias is −500 V, and the blocking capacitance Cb has a capacitance of 200 nF. Voltages of +500 V and -1500 V were applied to the two electrostatic electrodes, respectively. Then, the temperature distribution immediately after the plasma treatment was examined by thermography.

The results are shown in FIG. However, in FIG.
FIG. 13A shows a temperature distribution when the electrostatic chuck (example) shown in FIG. 2 is used, and FIG. 13B shows a temperature distribution when the electrostatic chuck (comparative example) shown in FIG. 11 is used. This figure 1
As is clear from FIG. 3, a uniform temperature distribution was obtained with the electrostatic chuck of FIG. 2, but the temperature distribution was not uniform with the electrostatic chuck of FIG. 9, and the peripheral edge had a high temperature. This is because the attraction force does not act on the portion on the bias electrode, and the temperature of the peripheral portion of the wafer easily rises. From this fact, the electrostatic chuck is, as shown in FIG.
It is preferable that the bias electrode is arranged at the center and the electrostatic electrode is arranged so as to surround the bias electrode.

The present invention can be applied not only to the plasma etching process but also to a film forming process using plasma.

[0058]

As described above, according to the present invention,
An electrostatic chuck provided with a bias electrode in contact with the wafer is used, and an AC voltage is applied to the bias electrode from an AC power source via a capacitor. Therefore, the impedance of the blocking capacitance can be set arbitrarily. As a result, a high voltage can be applied to the wafer in a semiconductor wafer processing process using high-density plasma, the etching rate during plasma etching is increased, and anisotropic etching can be performed more vertically.

Further, by using the electrostatic chuck in which the bias electrode is arranged in the central portion of the electrostatic chuck and the electrostatic electrode is arranged around the electrostatic chuck, the temperature of the wafer surface during the plasma processing is reduced. The distribution can be made uniform. As a result, it is possible to form an element having uniform characteristics. Further, a variable capacitance type capacitor is used as the capacitor, and the capacitance value of the capacitor is reduced immediately before the plasma processing is finished, and then the plasma power supply is turned off to prevent destruction of the element due to the electric charge accumulated in the capacitor. be able to. Further, even if a switch is provided between the capacitor and the bias voltage, the switch is turned off immediately before the plasma processing is finished, and then the plasma power supply is turned off, destruction of the element is prevented as in the above case. can do.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration of an inductively coupled plasma processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a plan view showing an electrostatic chuck of the semiconductor wafer processing apparatus according to the first embodiment.

FIG. 3 is a schematic diagram showing a connection between an electrostatic chuck and a power supply of the semiconductor wafer processing apparatus according to the first embodiment.

FIG. 4 is a schematic view showing another example of the electrostatic chuck.

FIG. 5 is a schematic diagram showing the connection of a voltmeter for measuring the potential of the wafer.

FIG. 6 is a schematic diagram showing a semiconductor wafer processing apparatus according to a second embodiment of the present invention.

FIG. 7 is a schematic diagram showing a semiconductor wafer processing apparatus according to a third embodiment of the present invention.

FIG. 8 is a plan view showing an electrostatic chuck of a semiconductor wafer processing apparatus according to a third embodiment.

FIG. 9 is a diagram showing a relationship between plasma generation power and voltage amplitude ratio.

FIG. 10 is a diagram showing a temperature distribution on a wafer surface after plasma processing.

FIG. 11 is a plan view showing an electrostatic chuck of a comparative example.

FIG. 12 is a schematic diagram showing connection of an electrostatic chuck of a comparative example.

FIG. 13 is a diagram showing a temperature distribution on a wafer surface after plasma processing.

14A is a schematic cross-sectional view showing a conventional single-plate electrostatic chuck, and FIG. 14B is a schematic cross-sectional view showing a conventional bipolar electrostatic chuck.

FIG. 15 is a schematic view showing a conventional parallel plate type plasma generator provided with a bipolar electrostatic chuck.

16A is a waveform diagram showing a voltage waveform in a high frequency electrode, and FIG. 16B is a waveform diagram showing a voltage waveform in a wafer.

FIG. 17 is an equivalent circuit diagram of the plasma generator shown in FIG.

FIG. 18 is a schematic diagram showing a conventional inductively coupled plasma generator.

[Explanation of symbols]

 1,41 Chamber 2,32,42 Counter electrode 3,11,33,43,45 Matching circuit 4,16,31,44 High frequency power source 5,17 Electrostatic chuck 5a, 17a, 21a, 23a Substrate 5b, 17b Bias electrode 5c, 5e, 17c, 21b, 23b Electrostatic electrode 6,26 Wafer 7,8,22,24,25 DC power supply 10,10a Capacitor 12,34,46 AC power supply 15 Switch

Claims (12)

[Claims] 1. An electrostatic device composed of an insulating substrate on which a wafer is mounted, a bias electrode provided on the surface of the substrate and in contact with the wafer, and an electrostatic electrode embedded below the surface of the substrate. A chuck, an AC power supply for applying an AC voltage to the bias electrode, a capacitor connected between the AC power supply and the bias electrode, and a DC power supply for applying a DC voltage to the electrostatic electrode. Characteristic semiconductor wafer processing equipment. 2. The semiconductor wafer processing apparatus according to claim 1, wherein the bias electrode is arranged in a central portion of the base, and the electrostatic electrode is arranged around the bias electrode. 3. The first and second electrostatic electrodes, which are electrically separated from each other, are provided as the electrostatic electrodes, and a positive voltage is applied to the first electrostatic electrodes as the DC power source. A second direct current power source and a second electrostatic voltage applied to the second electrostatic electrode;
3. The DC power supply according to claim 1 or 2.
The semiconductor wafer processing apparatus according to. 4. The capacitance value of the capacitor is 200 pF or more, according to any one of claims 1 to 3.
The semiconductor wafer processing apparatus according to item. 5. The semiconductor wafer processing apparatus according to claim 1, wherein the capacitor is a variable capacitance type capacitor. 6. The electrostatic chuck is provided with urging means for urging the bias electrode toward the wafer, according to any one of claims 1 to 5. Semiconductor wafer processing equipment. 7. The semiconductor wafer processing apparatus according to claim 1, wherein the bias electrode is made of conductive rubber. 8. A wafer by means of an electrostatic chuck composed of an insulating substrate on which a wafer is mounted, a bias electrode provided on the surface of the substrate and in contact with the wafer, and an electrostatic electrode embedded below the surface of the substrate. And a semiconductor wafer processing method for performing plasma processing on the wafer, wherein a DC voltage is applied to the electrostatic electrode to electrostatically adsorb the wafer, and an AC voltage is applied to the bias electrode via a capacitor. A method for processing a semiconductor wafer, which comprises applying a voltage. 9. The method for processing a semiconductor wafer according to claim 8, wherein when the plasma processing is finished, the capacitance value of the capacitor is decreased with time, and then the plasma generation is stopped. 10. When the plasma processing is completed, the capacitor and the bias electrode are electrically disconnected from each other,
After that, the generation of plasma is stopped, and the semiconductor wafer processing method according to claim 8. 11. A value of a self-bias voltage applied to the wafer during plasma processing is detected, and a voltage value applied to the electrostatic electrode is adjusted according to the detected self-bias voltage. The semiconductor wafer processing method according to claim 8. 12. A wafer by an electrostatic chuck composed of an insulating substrate on which a wafer is mounted, a bias electrode provided on the surface of the substrate and in contact with the wafer, and an electrostatic electrode embedded below the surface of the substrate. A semiconductor wafer processing method for holding a wafer and performing plasma processing on the wafer, wherein a specific potential is applied to the wafer via the bias electrode, and a DC voltage having a reverse potential is applied to the electrostatic electrode. A semiconductor wafer processing method comprising: a step of attracting a wafer to the electrostatic chuck; and a step of applying an AC voltage to the bias electrode via a capacitor.