JP2004247342A - Mounting board, semiconductor integrated circuit substrate, scribing device, and semiconductor device - Google Patents

Mounting board, semiconductor integrated circuit substrate, scribing device, and semiconductor device Download PDF

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Publication number
JP2004247342A
JP2004247342A JP2003032538A JP2003032538A JP2004247342A JP 2004247342 A JP2004247342 A JP 2004247342A JP 2003032538 A JP2003032538 A JP 2003032538A JP 2003032538 A JP2003032538 A JP 2003032538A JP 2004247342 A JP2004247342 A JP 2004247342A
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Japan
Prior art keywords
wiring board
groove
cut
dimension width
groove side
Prior art date
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JP2003032538A
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Japanese (ja)
Inventor
Toru Miyazawa
徹 宮澤
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a mounting board which is capable of preventing fissures from spreading when it is divided and also reducing its warpage and distortion caused by stress induced when it is bent so as to get very reliable by improving the structure of dividing grooves; and to provide a semiconductor integrated circuit board, a scribing device, and a semiconductor device. <P>SOLUTION: A laminated wiring board 11 is a multilayered copper-plated laminated wiring board which is, for instance, composed of a glass epoxy resin as a mother material and a five or more-layered copper wiring pattern formed on the glass epoxy resin. The laminated wiring board 11 has such a structure where the same wiring board regions are provided or several sets of wiring board regions of various sizes and shapes are provided on the same board. Therefore, a wiring pattern non-forming region 12 used for division is provided, and a cut region 13 where grooves are cut is provided as a scribe region 13. The cut region 13 is composed of a groove side face 131 having a maximum width W1 and a V-shaped groove 132 having a maximum width W2 smaller than the width W1 and located near at the center of the bottom of the groove side faces 131. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は、半導体装置製造に係り、特に多層のプリント配線基板のスクライブを伴う実装用基板、半導体集積回路基板及び溝切り刃及び半導体装置に関する。
【0002】
【従来の技術】
近年、電子機器の内部においてLSIの高機能化が進み、シリコンチップの機能向上、非常な微細化、高集積化が進められている。これに応じて実装側でも、プリント回路、プリント配線基板等を用いて、微細回路からの入出力信号がパフォーマンスを落とすことなく実使用可能なように電子回路を構成する必要がある。このようなプリント配線基板は、より多層かつ高密度配線化され、反り、歪み等があっては長期信頼性に不安が残る。
【0003】
上記プリント配線基板は、用途に応じた様々な形、大きさで形成される。製造上の効率化を図るため、プリント配線基板1枚の中に同じ配線板領域を複数持つ構成、数箇所に取り付けるためのセットが揃った構成が少なくない。よって、プリント配線基板1枚の中にはスクライブ領域があり、分割溝に沿って複数枚に折曲分割されるようになっている。この場合、従来では分割溝のカット形状はV字溝であった。しかし、V字溝が切ってあるだけでは折曲動作で基板に亀裂が広がる懸念があった。配線領域へ亀裂が広がれば、断線の危険性がある。プリント基板に対するこのような問題は従来から知られており、溝の一方面がV字溝、他方面が方形溝という形態で改善する例がある(例えば、実用新案文献1)。
【0004】
【実用新案文献1】
実開昭58−127666(第4図)
【0005】
【発明が解決しようとする課題】
しかしながら、より多層かつ高密度配線化されたプリント配線基板では、分割時の折曲動作で大きな力が加わりやすい。応力による反り、歪みにより、微細なスルーホールまたはビアへの信頼性に不安が払拭できず、また分割近傍の亀裂が広範囲に渡る等の懸念が解消されない。
【0006】
本発明は上記のような事情を考慮してなされたもので、分割溝の構造を改良して分割時の亀裂拡散防止はもとより折曲動作での応力による反り、歪みを大幅に減少させ高信頼性が得られる実装用基板、半導体集積回路基板及びスクライビング装置及びこれらを利用した半導体装置を提供しようとするものである。
【0007】
【課題を解決するための手段】
本発明に係る実装用基板は、
複数層の配線パターンが層間の接続部を含んで重ねられた所定平面形状の積層配線板と、
前記積層配線板における前記配線パターンの非形成領域にあって、第1の寸法幅を有する溝側面と、溝側面間底部中央付近に第1の寸法幅より小さい第2の寸法幅を有するV字溝とで構成されるカット領域と、
を具備したことを特徴とする。
【0008】
上記のような本発明に係る実装用基板によれば、カット領域は2段構造となる。1段目でV字溝よりも広い第1の寸法幅を有する溝側面を有することにより、折曲動作時の応力が、2段目のV字溝へより集中するようになる。これにより、分割し易く、亀裂の広がりも2段目のV字溝部分で吸収され、基板内部にまで侵入しない。
【0009】
上記本発明に係る実装用基板において、より好ましい実施態様を各々次に記す。
前記カット領域は前記溝側面に関し方形の短辺と同等の形態を有することを特徴とする。
前記カット領域は前記溝側面が逆台形のテーパ面であることを特徴とする。
前記カット領域は前記溝側面及びV字溝を形成する段差の角が丸められた形状を呈していることを特徴とする。
【0010】
本発明に係る半導体集積回路基板は、
複数層の配線パターンが層間の接続部を含んで重ねられ露出面が実装領域となっている積層配線板と、
前記実装領域に実装された半導体装置と、
前記積層配線板における前記配線パターンの非形成領域にあって、第1の寸法幅を有する溝側面と、溝側面間底部中央付近に第1の寸法幅より小さい第2の寸法幅を有するV字溝とで構成されるカット領域と、
を具備したことを特徴とする。
【0011】
上記本発明に係る半導体集積回路基板によれば、上述の実装用基板同様、カット領域は2段構造となる。1段目でV字溝よりも広い第1の寸法幅を有する溝側面を有することにより、折曲動作時の応力が、2段目のV字溝へより集中するようになる。これにより、分割し易く、亀裂の広がりも2段目のV字溝部分で吸収され、基板内部にまで侵入しない。
なお、上記実装用基板で記したより好ましい実施態様各々が、そのまま上記半導体集積回路基板に当てはめられる。
【0012】
本発明に係るスクライビング装置は、
積層配線板における分割領域に対して、互いに表裏から第1の寸法幅を有する溝側面と、溝側面間底部中央付近に第1の寸法幅より小さい第2の寸法幅を有するV字溝の両カット形状を同時に与えることのできる研削盤を有することを特徴とする。
【0013】
上記のような本発明に係るスクライビング装置によれば、積層配線板の表裏のカット領域は2段構造となる。1段目がV字溝よりも広い第1の寸法幅を有する溝側面、2段目がV字溝となり、かつ互いに対向するよう位置合わせされる。
なお、前記研削盤は積層配線板の表裏へ互いに数回に分けてより深く溝を刻んでいくことを特徴とする。
また、前記研削盤は前記溝側面及びV字溝を形成する段差の角が丸められた形状を呈していることを特徴とする。
あるいは、前記研削盤は前記溝側面が長方形の短辺と同等の形態を有するものでもよい。また、前記研削盤は前記溝側面が逆台形のテーパ面を有するようにしてもよい。
【0014】
また、本発明に係る半導体装置は、上述したような実装用基板を用いて形成されたことを特徴とする。あるいは、上述したような半導体集積回路基板を用いて形成された半導体装置、あるいは、上述したようなスクライビング装置を用いて形成された半導体装置も本発明にかかる。
【0015】
【発明の実施の形態】
図1は、本発明の第1実施形態に係る実装用基板の要部を示す断面図である。積層配線板11は、例えばガラスエポキシ樹脂を母材とし5層以上の銅配線パターンが形成された多層の銅張積層配線板である。積層配線板11は、この1枚の中に同じ配線板領域を複数持つ構成、または数箇所に取り付けるための様々な形、大きさがセットで揃った構成となっている。このため、分割するために配線パターンの非形成領域12があり、スクライブ領域として溝が刻まれているカット領域13を有する。この実施形態では、カット領域13は、最大寸法幅W1を有する溝側面131と、溝側面間底部中央付近に寸法幅W1より小さい最大寸法幅W2を有するV字溝132とで構成される。
【0016】
カット領域13は、積層配線板11の表裏に互いに少なくともV字溝132の底部が対向するように、もしくは位置合わせされるように設けられている。両カット領域13の深さD1×2は、積層配線板11全体の40〜60%を占める。溝側面131は方形の短辺と同等の形態を有し、V字溝132の深さより浅い。V字溝132の鋭角は30°〜60°が好ましい範囲である。これにより、積層配線板11は折曲力によって、カット領域13、すなわちV字溝132の底部を境にして分割される。
【0017】
上記実施形態によれば、カット領域13は2段構造となっている。1段目でV字溝132よりも広い寸法幅W1を有する溝側面131を有することにより、折曲動作時の応力が、2段目のV字溝132へより集中するようになる。これにより、分割し易く、亀裂の広がりも2段目のV字溝132部分で吸収され、積層配線板11の配線パターンのある内部にまで侵入しない。さらに、折曲動作での応力による反り、歪みを大幅に減少させるので、微細なスルーホールまたはビアへの信頼性が大幅に向上する。
【0018】
図2は、本発明の第2実施形態に係る実装用基板の要部を示す断面図である。前記第1実施形態と同様の積層配線板21に配線パターンの非形成領域22が存在しカット領域23が設けられている。カット領域23は、最大寸法幅W3を有して逆台形のテーパ面を有する溝側面231と、溝側面間底部中央付近に逆台形の底部寸法幅W4より小さい最大寸法幅W5を有するV字溝232とで構成される。V字溝232は前記第1実施形態と同様の構成である。カット領域23は、積層配線板21の表裏に互いに位置合わせされるように設けられるのも第1実施形態と同様である。両カット領域23の深さD2×2は、積層配線板21全体の40〜60%を占める。これにより、積層配線板21は折曲力によって、カット領域23、すなわちV字溝232の底部を境にして分割される。
【0019】
上記実施形態によれば、前記第1実施形態と同様にカット領域13は2段構造となっており、折曲動作時の応力が、2段目のV字溝232へより集中するようになる。これにより、分割し易く、亀裂の広がりも2段目のV字溝232部分で吸収され、積層配線板21の配線パターンのある内部にまで侵入しない。
【0020】
図3は、本発明の第3実施形態に係る実装用基板の要部を示す断面図である。前記第1実施形態と同様の積層配線板31に配線パターンの非形成領域32が存在しカット領域33が設けられている。カット領域33は、最大寸法幅W6を有して段差の角が丸められた緩やかな斜面を有する溝側面331と、溝側面間底部中央付近にやはり角が丸められた大略寸法幅W7を有するV字溝332とで構成される。カット領域33は、積層配線板31の表裏に互いに位置合わせされるように設けられるのも第1実施形態と同様である。両カット領域33の深さD3×2は、積層配線板31全体の40〜60%を占める。これにより、積層配線板31は折曲力によって、カット領域33、すなわちV字溝332の底部を境にして分割される。
【0021】
上記実施形態によれば、前記第1実施形態と同様にカット領域33は2段構造となっており、折曲動作時の応力が、2段目のV字溝332へより集中するようになる。これにより、分割し易く、亀裂の広がりも2段目のV字溝332部分で吸収され、積層配線板31の配線パターンのある内部にまで侵入しない。なお、カット領域33の溝側面33の1は緩やかな斜面を有する構成としたが、基本形を前記図1のような方形とし、角を丸めた構成でもよい。
図4は、第3実施形態の応用例であり、上記した逆台形の基本形を前記図1のような方形とし、角を丸めた構成である。第3実施形態と同様の箇所には同一の符号を付して説明は省略する。
【0022】
図5は、本発明の第4実施形態に係る半導体集積回路基板の構成を示す概略図である。積層配線板41は、複数層の配線パターンが層間の接続部を含んで重ねられており、露出面の実装領域Sに所定の半導体装置が実装される。半導体装置は半導体集積回路チップ、トランジスタ、抵抗、コンデンサ等、各素子チップなどが所定領域に実装されている。積層配線板41は、分割するために配線パターンの非形成領域42があり、スクライブ領域として溝が刻まれているカット領域43を有する。カット領域43は、例えば前記図1〜図4のいずれかのカット領域13,23、33が採用される。これにより、分割し易く、亀裂の広がりも防ぐことができ、積層配線板41の配線パターンのある内部にまで侵入しない。
【0023】
図6(a),(b)は、本発明の第5実施形態に係るスクライビング装置の要部を示す概略図である。積層配線板51はスクライビング装置50内に位置合わせされ搬送される。分割領域に対して、互いに表裏から対向する第1の寸法幅を有する溝側面と、溝側面間底部中央付近に第1の寸法幅より小さい第2の寸法幅を有するV字溝の両カット形状を同時に与えることのできる研削盤52を有する(図6(b))。これにより、前記図3に示すようなカット領域33の形状を実現する。研削盤52は積層配線板51の表裏へ互いに数回に分けてより深く溝を刻んでいき、所望の深さのカット領域33を実現するようにしてもよい。その他、研削盤52の形状を変えれば、それぞれ図1、図2、図4のいずれかのカット領域13,23、33が実現される。
【0024】
図7(a)〜(f)は、研削盤を溝側面用と、V字溝用と、それぞれのカット形状を別々に与えることのできる研削盤の断面形状である。図7(a)〜(d)の521a〜dは1段目の溝側面用、図7(e),(f)の522a,bはV字溝用として示した。このような構成によれば、溝側面、V字溝それぞれの深さを容易に自由に設定できるカット領域ができる。
【0025】
以上説明したように、上記各実施形態の構成によれば、カット領域は2段構造となる。1段目でV字溝よりも広い第1の寸法幅を有する溝側面を有することにより、折曲動作時の応力が、2段目のV字溝へより集中するようになる。これにより、分割し易く、亀裂の広がりも2段目のV字溝部分で吸収され、基板内部にまで侵入しない。この結果、分割溝の構造を改良して分割時の亀裂拡散防止はもとより折曲動作での応力による反り、歪みを大幅に減少させ高信頼性が得られる実装用基板、半導体集積回路基板及びスクライビング装置及びこれらを利用した半導体装置を提供することができる。
【図面の簡単な説明】
【図1】第1実施形態に係る実装用基板の要部を示す断面図。
【図2】第2実施形態に係る実装用基板の要部を示す断面図。
【図3】第3実施形態に係る実装用基板の要部を示す断面図。
【図4】第3実施形態の応用例の要部を示す断面図。
【図5】第4実施形態に係る半導体集積回路基板の構成を示す概略図。
【図6】第5実施形態に係るスクライビング装置の要部を示す概略図。
【図7】それぞれ研削盤の断面図。
【符号の説明】
11,21,31,41,51…積層配線板、12,22,32,42…配線パターンの非形成領域(スクライブ領域)、13,23,33…カット領域、131,231,331…溝側面、132,232,332…V字溝、50…スクライビング装置、52,521a〜d,522a,b…研削盤。
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to the manufacture of semiconductor devices, and more particularly to a mounting board, a semiconductor integrated circuit board, a groove cutting blade, and a semiconductor device involving scribing of a multilayer printed wiring board.
[0002]
[Prior art]
2. Description of the Related Art In recent years, the functions of LSIs have been advanced in electronic devices, and the functions of silicon chips have been improved, the semiconductor devices have been extremely miniaturized, and the integration has been advanced. Accordingly, it is necessary for the mounting side to configure an electronic circuit using a printed circuit, a printed wiring board, or the like so that input / output signals from the fine circuit can be actually used without deteriorating the performance. Such a printed wiring board has a multi-layered and high-density wiring, and if there is a warp, distortion, or the like, there is a concern about long-term reliability.
[0003]
The printed wiring board is formed in various shapes and sizes depending on the application. In order to increase the efficiency in manufacturing, there are not a few configurations in which a single printed wiring board has a plurality of the same wiring board regions, and a configuration in which sets for attaching to a plurality of locations are prepared. Therefore, there is a scribe area in one printed wiring board, and the printed wiring board is bent and divided along the division groove. In this case, conventionally, the cut shape of the dividing groove is a V-shaped groove. However, if the V-shaped groove is only cut, there is a concern that the substrate may be cracked by the bending operation. If the crack spreads to the wiring area, there is a risk of disconnection. Such a problem with respect to a printed circuit board has been conventionally known, and there is an example in which one side of the groove is improved by a V-shaped groove and the other side is formed by a rectangular groove (for example, Utility Model Document 1).
[0004]
[Utility model document 1]
58-127666 (Fig. 4)
[0005]
[Problems to be solved by the invention]
However, in a printed wiring board having a multi-layered and high-density wiring, a large force is likely to be applied by the bending operation at the time of division. Due to warpage or distortion due to stress, concerns about the reliability of fine through holes or vias cannot be wiped out, and concerns such as widespread cracks near the division cannot be solved.
[0006]
The present invention has been made in consideration of the above-described circumstances, and by improving the structure of the dividing groove, not only preventing crack diffusion at the time of dividing, but also significantly reducing warpage due to stress in bending operation, distortion, and achieving high reliability. It is an object of the present invention to provide a mounting substrate, a semiconductor integrated circuit substrate, a scribing device, and a semiconductor device using the same, which can obtain the property.
[0007]
[Means for Solving the Problems]
The mounting substrate according to the present invention,
A multilayer wiring board having a predetermined planar shape in which a plurality of wiring patterns are stacked including a connection portion between the layers,
A V-shape having a groove side face having a first dimension width and a second dimension width smaller than the first dimension width near the center of the bottom between the groove side faces in a region where the wiring pattern is not formed in the laminated wiring board; A cut area composed of a groove and
It is characterized by having.
[0008]
According to the mounting substrate according to the present invention as described above, the cut region has a two-stage structure. By having the groove side surface having the first dimension width wider than the V-shaped groove in the first stage, the stress at the time of the bending operation is more concentrated on the V-shaped groove in the second stage. As a result, it is easy to divide, and the spread of the crack is absorbed by the V-shaped groove portion of the second stage, and does not enter the inside of the substrate.
[0009]
Preferred embodiments of the mounting board according to the present invention will be described below.
The cut region has a shape similar to a rectangular short side with respect to the groove side surface.
The cut region is characterized in that the groove side surface is an inverted trapezoidal tapered surface.
The cut region has a shape in which the corner of a step forming the groove side surface and the V-shaped groove is rounded.
[0010]
The semiconductor integrated circuit board according to the present invention is
A multilayer wiring board in which a plurality of wiring patterns are stacked including a connection portion between the layers and the exposed surface is a mounting area,
A semiconductor device mounted in the mounting area;
A V-shape having a groove side face having a first dimension width and a second dimension width smaller than the first dimension width near the center of the bottom between the groove side faces in a region where the wiring pattern is not formed in the laminated wiring board; A cut area composed of a groove and
It is characterized by having.
[0011]
According to the semiconductor integrated circuit substrate of the present invention, the cut region has a two-stage structure, similarly to the mounting substrate described above. By having the groove side surface having the first dimension width wider than the V-shaped groove in the first stage, the stress at the time of the bending operation is more concentrated on the V-shaped groove in the second stage. As a result, it is easy to divide, and the spread of the crack is absorbed by the V-shaped groove portion of the second stage, and does not enter the inside of the substrate.
Each of the more preferred embodiments described for the mounting substrate can be applied to the semiconductor integrated circuit substrate as it is.
[0012]
The scribing device according to the present invention,
With respect to the divided region in the laminated wiring board, both the groove side surface having the first dimension width from the front and back and the V-shaped groove having the second dimension width smaller than the first dimension width near the center of the bottom between the groove side surfaces. It is characterized by having a grinding machine capable of simultaneously giving a cut shape.
[0013]
According to the scribing apparatus according to the present invention as described above, the cut regions on the front and back of the laminated wiring board have a two-stage structure. The first step is a groove side surface having a first dimension width wider than the V-shaped groove, and the second step is a V-shaped groove and is positioned so as to face each other.
The grinding machine is characterized in that grooves are formed deeper into the front and back surfaces of the laminated wiring board in several steps.
Further, the grinding machine has a feature that the corners of the steps forming the groove side surface and the V-shaped groove are rounded.
Alternatively, the grinding machine may have a configuration in which the groove side surface is equivalent to a rectangular short side. In the grinding machine, the groove side surface may have an inverted trapezoidal tapered surface.
[0014]
Further, a semiconductor device according to the present invention is formed using the mounting substrate as described above. Alternatively, a semiconductor device formed using the above-described semiconductor integrated circuit substrate, or a semiconductor device formed using the above-described scribing device is also related to the present invention.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a sectional view showing a main part of a mounting board according to the first embodiment of the present invention. The multilayer wiring board 11 is a multilayer copper-clad multilayer wiring board in which five or more copper wiring patterns are formed using, for example, a glass epoxy resin as a base material. The laminated wiring board 11 has a configuration in which a plurality of the same wiring board area is provided in one piece, or a configuration in which various shapes and sizes for mounting at several places are arranged in a set. For this reason, there is a non-formation area 12 of the wiring pattern for division, and a cut area 13 in which a groove is cut as a scribe area. In this embodiment, the cut region 13 includes a groove side surface 131 having a maximum dimension width W1, and a V-shaped groove 132 having a maximum dimension width W2 smaller than the dimension width W1 near the bottom center between the groove side faces.
[0016]
The cut regions 13 are provided on the front and back surfaces of the laminated wiring board 11 such that at least the bottoms of the V-shaped grooves 132 face each other or are aligned. The depth D1 × 2 of both cut regions 13 occupies 40 to 60% of the entire laminated wiring board 11. The groove side surface 131 has a form equivalent to the short side of the rectangle, and is shallower than the depth of the V-shaped groove 132. The acute angle of the V-shaped groove 132 is preferably in a range of 30 ° to 60 °. Thereby, the laminated wiring board 11 is divided by the bending force at the cut region 13, that is, at the bottom of the V-shaped groove 132.
[0017]
According to the above embodiment, the cut area 13 has a two-stage structure. By having the groove side surface 131 having the dimension width W1 wider than the V-shaped groove 132 at the first stage, the stress at the time of the bending operation is more concentrated on the V-shaped groove 132 at the second stage. As a result, it is easy to divide, and the spread of cracks is absorbed by the V-shaped groove 132 at the second stage, and does not enter the inside of the multilayer wiring board 11 where the wiring pattern exists. Furthermore, since warpage and distortion due to stress in the bending operation are greatly reduced, the reliability of fine through holes or vias is greatly improved.
[0018]
FIG. 2 is a cross-sectional view showing a main part of a mounting board according to a second embodiment of the present invention. In the same multilayer wiring board 21 as in the first embodiment, a non-formation area 22 of a wiring pattern exists and a cut area 23 is provided. The cut region 23 has a groove side surface 231 having a maximum dimension width W3 and having an inverted trapezoidal tapered surface, and a V-shaped groove having a maximum dimension width W5 smaller than the inverted trapezoidal bottom dimension width W4 near the bottom center between the groove side faces. 232. The V-shaped groove 232 has the same configuration as in the first embodiment. The cut regions 23 are provided on the front and back surfaces of the multilayer wiring board 21 so as to be aligned with each other, similarly to the first embodiment. The depth D2 × 2 of both cut regions 23 occupies 40 to 60% of the entire laminated wiring board 21. Thus, the laminated wiring board 21 is divided by the bending force at the cut region 23, that is, at the bottom of the V-shaped groove 232.
[0019]
According to the above-described embodiment, the cut region 13 has a two-stage structure as in the first embodiment, and the stress during the bending operation is more concentrated on the V-shaped groove 232 of the second stage. . As a result, it is easy to divide, and the spread of the crack is absorbed by the V-shaped groove 232 of the second stage, and does not enter the inside of the laminated wiring board 21 where the wiring pattern exists.
[0020]
FIG. 3 is a sectional view showing a main part of a mounting board according to a third embodiment of the present invention. In the same multilayer wiring board 31 as in the first embodiment, a non-formed area 32 of a wiring pattern is present and a cut area 33 is provided. The cut area 33 has a maximum dimension width W6, a groove side surface 331 having a gentle slope with rounded corners of a step, and a V having an approximate dimension width W7 also having a rounded corner near the bottom center between the groove side faces. And a groove 332. The cut regions 33 are provided on the front and back surfaces of the multilayer wiring board 31 so as to be aligned with each other, similarly to the first embodiment. The depth D3 × 2 of both cut regions 33 occupies 40 to 60% of the entire laminated wiring board 31. Thus, the multilayer wiring board 31 is divided by the bending force at the cut region 33, that is, at the bottom of the V-shaped groove 332.
[0021]
According to the above-described embodiment, the cut region 33 has a two-stage structure as in the first embodiment, and the stress during the bending operation is more concentrated on the V-shaped groove 332 of the second stage. . As a result, it is easy to divide, and the spread of the crack is absorbed by the V-shaped groove 332 in the second stage, and does not enter the inside of the multilayer wiring board 31 where the wiring pattern exists. In addition, although one of the groove side surfaces 33 of the cut region 33 has a gentle slope, the basic shape may be a square as shown in FIG. 1 and the corner may be rounded.
FIG. 4 shows an application example of the third embodiment, in which the above-described basic shape of the inverted trapezoid is changed to a square as shown in FIG. 1 and the corners are rounded. The same parts as in the third embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0022]
FIG. 5 is a schematic diagram showing a configuration of a semiconductor integrated circuit substrate according to a fourth embodiment of the present invention. In the laminated wiring board 41, a plurality of wiring patterns are overlapped with each other including a connection portion between layers, and a predetermined semiconductor device is mounted on the mounting area S on the exposed surface. In a semiconductor device, each element chip such as a semiconductor integrated circuit chip, a transistor, a resistor, and a capacitor is mounted in a predetermined region. The laminated wiring board 41 has a non-formation area 42 of the wiring pattern for division and a cut area 43 in which a groove is cut as a scribe area. As the cut area 43, for example, any of the cut areas 13, 23, and 33 shown in FIGS. This makes it easy to divide and prevent the crack from spreading, and does not penetrate into the inside of the laminated wiring board 41 where the wiring pattern exists.
[0023]
FIGS. 6A and 6B are schematic views showing a main part of a scribing device according to a fifth embodiment of the present invention. The laminated wiring board 51 is positioned and transported in the scribing device 50. Both cut shapes of a groove side face having a first dimension width and a V-shaped groove having a second dimension width smaller than the first dimension width near the center of the bottom between the groove side faces facing each other from the front and back sides with respect to the divided area. (See FIG. 6 (b)). Thereby, the shape of the cut region 33 as shown in FIG. 3 is realized. The grinder 52 may cut the groove deeper into the front and back surfaces of the laminated wiring board 51 several times to realize the cut region 33 having a desired depth. In addition, if the shape of the grinder 52 is changed, the cut regions 13, 23, and 33 shown in FIGS. 1, 2, and 4 are realized.
[0024]
FIGS. 7A to 7F are cross-sectional shapes of a grinding machine capable of separately giving a cutting shape for a groove side surface and a V-shaped groove. 7A to 7D, 521a to 521d are used for the first groove side surface, and 522a and 522b in FIGS. 7E and 7F are used for the V-shaped groove. According to such a configuration, there is a cut region in which the depth of each of the groove side surface and the V-shaped groove can be easily and freely set.
[0025]
As described above, according to the configuration of each of the above embodiments, the cut region has a two-stage structure. By having the groove side surface having the first dimension width wider than the V-shaped groove at the first stage, the stress at the time of the bending operation is more concentrated on the V-shaped groove at the second stage. As a result, it is easy to divide, and the spread of the crack is absorbed by the V-shaped groove portion of the second stage, and does not enter the inside of the substrate. As a result, the mounting substrate, the semiconductor integrated circuit substrate, and the scribing, which improve the structure of the dividing groove to prevent crack diffusion at the time of dividing, as well as significantly reduce warpage and distortion due to stress in bending operation and obtain high reliability. A device and a semiconductor device using the same can be provided.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a main part of a mounting board according to a first embodiment.
FIG. 2 is a sectional view showing a main part of a mounting board according to a second embodiment.
FIG. 3 is a sectional view showing a main part of a mounting board according to a third embodiment.
FIG. 4 is a sectional view showing a main part of an application example of the third embodiment.
FIG. 5 is a schematic diagram showing a configuration of a semiconductor integrated circuit substrate according to a fourth embodiment.
FIG. 6 is a schematic view showing a main part of a scribing device according to a fifth embodiment.
FIG. 7 is a sectional view of a grinding machine.
[Explanation of symbols]
11, 21, 31, 41, 51: laminated wiring board; 12, 22, 32, 42: non-forming area (scribe area) of wiring pattern; 13, 23, 33: cut area; 131, 231, 331: groove side face , 132, 232, 332 ... V-shaped groove, 50 ... scribing device, 52, 521a-d, 522a, b ... grinding machine.

Claims (10)

複数層の配線パターンが層間の接続部を含んで重ねられた所定平面形状の積層配線板と、
前記積層配線板における前記配線パターンの非形成領域にあって、第1の寸法幅を有する溝側面と、溝側面間底部中央付近に第1の寸法幅より小さい第2の寸法幅を有するV字溝とで構成されるカット領域と、
を具備したことを特徴とする実装用基板。
A multilayer wiring board having a predetermined planar shape in which wiring patterns of a plurality of layers are stacked including connection portions between the layers,
A V-shape having a groove side face having a first dimension width and a second dimension width smaller than the first dimension width near a center of a bottom between groove side faces in a region where the wiring pattern is not formed in the laminated wiring board; A cut area composed of a groove and
A mounting substrate, comprising:
前記カット領域は前記積層配線板の表裏に互いに少なくともV字溝の底部が対向するように設けられていることを特徴とする請求項1記載の実装用基板。2. The mounting substrate according to claim 1, wherein the cut region is provided on both sides of the laminated wiring board so that at least bottom portions of the V-shaped grooves face each other. 前記カット領域は前記溝側面に関し方形の短辺と同等の形態を有することを特徴とする請求項1記載の実装用基板。The mounting substrate according to claim 1, wherein the cut region has a shape equivalent to a rectangular short side with respect to the groove side surface. 前記カット領域は前記溝側面が逆台形のテーパ面であることを特徴とする請求項1記載の実装用基板。The mounting substrate according to claim 1, wherein the cut region has an inverted trapezoidal tapered surface on the side surface of the groove. 前記カット領域は前記溝側面及びV字溝を形成する段差の角が丸められた形状を呈していることを特徴とする請求項1記載の実装用基板。The mounting substrate according to claim 1, wherein the cut region has a shape in which a corner of a step forming the groove side surface and the V-shaped groove is rounded. 複数層の配線パターンが層間の接続部を含んで重ねられ露出面が実装領域となっている積層配線板と、
前記実装領域に実装された半導体装置と、
前記積層配線板における前記配線パターンの非形成領域にあって、第1の寸法幅を有する溝側面と、溝側面間底部中央付近に第1の寸法幅より小さい第2の寸法幅を有するV字溝とで構成されるカット領域と、
を具備したことを特徴とする半導体集積回路基板。
A multilayer wiring board in which a plurality of wiring patterns are stacked including a connection portion between the layers and an exposed surface is a mounting area,
A semiconductor device mounted in the mounting area;
A V-shape having a groove side face having a first dimension width and a second dimension width smaller than the first dimension width near a center of a bottom between groove side faces in a region where the wiring pattern is not formed in the laminated wiring board; A cut area composed of a groove and
A semiconductor integrated circuit substrate, comprising:
積層配線板における分割領域に対して、互いに表裏から対向する第1の寸法幅を有する溝側面と、溝側面間底部中央付近に第1の寸法幅より小さい第2の寸法幅を有するV字溝の両カット形状を同時に与えることのできる研削盤を有することを特徴とするスクライビング装置。A groove side face having a first dimension width opposed to the divided region in the laminated wiring board from the front and back, and a V-shaped groove having a second dimension width smaller than the first dimension width near a bottom center between the groove side faces. A scribing device having a grinding machine capable of simultaneously giving both cut shapes. 前記研削盤は積層配線板の表裏へ互いに数回に分けてより深く溝を刻んでいくことを特徴とする請求項7記載のスクライビング装置。8. The scribing apparatus according to claim 7, wherein the grinder cuts the groove deeper into the front and back of the laminated wiring board several times. 前記研削盤は前記溝側面及びV字溝を形成する段差の角が丸められた形状を呈していることを特徴とする請求項7または8記載のスクライビング装置。9. The scribing apparatus according to claim 7, wherein the grinding machine has a shape in which corners of a step forming the groove side surface and the V-shaped groove are rounded. 前記請求項1〜5いずれかに記載の実装用基板を用いて形成されたことを特徴とする半導体装置。A semiconductor device formed using the mounting substrate according to claim 1.
JP2003032538A 2003-02-10 2003-02-10 Mounting board, semiconductor integrated circuit substrate, scribing device, and semiconductor device Withdrawn JP2004247342A (en)

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Cited By (7)

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Publication number Priority date Publication date Assignee Title
JP2006339459A (en) * 2005-06-02 2006-12-14 Matsushita Electric Works Ltd Dividing method of microwave circuit substrate
JP2008028065A (en) * 2006-07-20 2008-02-07 Denso Corp Method for manufacturing ceramic substrate
JP2008270560A (en) * 2007-04-20 2008-11-06 Tdk Corp Working method of laminate and laminate
US7672082B2 (en) * 2005-08-31 2010-03-02 Tdk Corporation Flexible wiring board for magnetic head assembly
EP1881749A3 (en) * 2006-07-20 2010-04-07 Dyconex AG Method of fabricating an electrical connecting element, and electrical connecting element
CN104051278A (en) * 2014-02-18 2014-09-17 无锡江南计算技术研究所 Molding and milling-cutting method of DBC ceramic substrate
CN105764258A (en) * 2016-04-22 2016-07-13 深圳崇达多层线路板有限公司 Method of making step groove on PCB

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006339459A (en) * 2005-06-02 2006-12-14 Matsushita Electric Works Ltd Dividing method of microwave circuit substrate
US7672082B2 (en) * 2005-08-31 2010-03-02 Tdk Corporation Flexible wiring board for magnetic head assembly
JP2008028065A (en) * 2006-07-20 2008-02-07 Denso Corp Method for manufacturing ceramic substrate
EP1881749A3 (en) * 2006-07-20 2010-04-07 Dyconex AG Method of fabricating an electrical connecting element, and electrical connecting element
US7892625B2 (en) 2006-07-20 2011-02-22 Dyconex Ag Method of fabricating an electrical connecting element, and an electrical connecting element
JP2008270560A (en) * 2007-04-20 2008-11-06 Tdk Corp Working method of laminate and laminate
JP4720775B2 (en) * 2007-04-20 2011-07-13 Tdk株式会社 Laminate processing method
CN104051278A (en) * 2014-02-18 2014-09-17 无锡江南计算技术研究所 Molding and milling-cutting method of DBC ceramic substrate
CN104051278B (en) * 2014-02-18 2016-11-02 无锡江南计算技术研究所 The molding milling method of DBC ceramic substrate
CN105764258A (en) * 2016-04-22 2016-07-13 深圳崇达多层线路板有限公司 Method of making step groove on PCB

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