JP2008047771A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interconnection structure for minimizing the number of positions where reflection or impairment of a signal takes place by minimizing the number of vias in a semiconductor device having a microstrip line structure or a strip line structure. <P>SOLUTION: The semiconductor device has a strip line structure including a power supply layer 1, a first ground layer 2, a signal layer 3, and a second ground layer 4. The first ground layer 2 is provided between the power supply layer 1 and the signal layer 3; and the power supply layer 1, the first ground layer 2, and the signal layer 3 are wire bonded to a semiconductor chip 100 in an opening 10 for a semiconductor chip. The inner circumferential end on the side of the opening 10 for a semiconductor chip has a step structure, and the inner circumferential end on the side of the opening 10 for a semiconductor chip is located closest to the semiconductor chip 100 so that the wire 71 of the signal layer 3 becomes shortest. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a wiring structure of a semiconductor device having a microstrip line structure or a strip line structure.

As a transmission signal becomes higher in frequency, a semiconductor device having a microstrip line structure or a strip line structure often employs a multilayer wiring structure in which layers are connected by vias (see, for example, Patent Document 1 and Non-Patent Document 1).
JP 2006-13029 A Shunichi Imaoka and 4 others, "Ultra-thin, high-frequency multilayer ISB module technology", SANYO TECHNICAL REVIEW, VOL.37, NO.2, MAR. 2006, pp.37-44

  However, in a multilayer wiring structure using vias, a plurality of vias continue as discontinuous points, and there are many places where signal reflection and degradation can occur.

  The present invention has been made in view of the above circumstances, and in a semiconductor device having a microstripline structure or a stripline structure, the number of vias is reduced as much as possible to minimize signal reflection and deterioration. It is an object of the present invention to provide a wiring structure suppressed to a low level and a semiconductor device including the wiring structure.

  In order to solve the above problems, the wiring structure of the present invention has a microstrip line structure including a power supply layer, a first ground layer, and a signal layer, or a strip line structure further including a second ground layer. A wiring structure of a semiconductor device, wherein a first ground layer is provided between a power supply layer and a signal layer, and the power supply layer, the first ground layer, and the signal layer are accommodated in an opening for a semiconductor chip. The inner peripheral end of the semiconductor chip opening side is a staircase structure and the inner peripheral end of the signal layer so that the wire of the signal layer is shortest and is wire-bonded to the semiconductor chip. Is located closest to the semiconductor chip.

  In this wiring structure, the signal layer wire is within 1 mm, one or both of the power supply layer and the ground layer are ribbon wires, and the line width of one or both of the power supply layer and the ground layer It is further characterized by being thick.

  Further, the power supply layer is further arranged as the uppermost layer.

  Further, it is further characterized in that a ball grid array is provided and a second ground layer is not provided under the solder balls in the stripline structure.

  The semiconductor device of the present invention has these wiring structures.

  The semiconductor device is further characterized in that a heat radiator is provided on the back side of the semiconductor chip.

  Furthermore, it is connected to the motherboard via a connection jig having a staircase structure that matches the height of the solder balls of each layer, connected to a motherboard that has a staircase structure that matches the height of the solder balls of each layer, It is also characterized in that the size of the solder balls in each layer is adjusted so that the connection height with the motherboard is the same between the layers.

  According to the present invention having the features as described above, it is possible to realize a wiring structure in which the number of vias is reduced as much as possible to minimize signal reflection and deterioration, and a semiconductor device including the wiring structure. Can do.

[First embodiment]
1 to 3 are a sectional view, a partially enlarged sectional view, and a plan view, respectively, showing an embodiment of the present invention.

  The present embodiment has a stripline structure including a power supply layer 1, a first ground layer 2, a signal layer 3, and a second ground layer 4. In this stripline structure, the first ground layer 2 is formed. Is provided between the power supply layer 1 and the signal layer 3, and the power supply layer 1, the first ground layer 2, and the signal layer 3 are provided on the semiconductor chip 100 accommodated in the semiconductor chip opening 10. The inner peripheral end of the semiconductor chip opening 10 side has a staircase structure and the inner peripheral end of the signal layer 3 is wire-bonded so that the wire 73 of the signal layer 3 is the shortest. It is located closest to the semiconductor chip 100.

  More specifically, first, the power supply layer 1, the first ground layer 2, and the signal layer 3 are provided with the power supply line 12, the ground line 22, and the signal line 32 on the surfaces of the insulating substrates 11, 21, 31 whose central regions are opened. They are provided (see FIG. 2), and are stacked on the heat sink 300 in order from the signal layer 3. The heat sink 300 and the signal layer 3 are fixed with an adhesive 301.

  The insulating substrates 11, 21, 31 have planar areas of different sizes, and are sequentially reduced from the signal layer 3 when viewed from the heat sink 300, and conversely, the rectangular openings 13, 23 and 33 (see FIG. 2) are opened from the signal layer 3 in order.

  As a result, when the layers are stacked and the openings 13, 23, 33 are overlapped, one semiconductor chip opening 10 is formed in which the opening region extends from the signal layer 3 to the power supply layer 1. The inner peripheral edge of each layer facing the chip opening 10 has a staircase structure (also called a step structure) in which the inner peripheral edge of the signal layer 3 protrudes inward.

  A semiconductor chip 100 such as an IC chip is accommodated in the semiconductor chip opening 10 having this staircase structure, and is fixed on the heat sink 300 via an adhesive 200 such as an Ag paste.

  Each layer and the semiconductor chip 100 are wire-bonded with wires 71, 72, and 73.

  The wires 71, 72, and 73 are the wire pad 101 (see FIG. 3) provided on the semiconductor chip 100, the power supply line 12 that is exposed in the staircase structure in the semiconductor chip opening 10, the ground line 22, and the signal, respectively. The wire 32 (see FIG. 2) is connected. At this time, the wire 73 that connects the signal line 32 closest to the semiconductor chip 100 is the shortest. The wire 73 is preferably within 1 mm.

  According to the multilayer wiring structure as described above, a via-less structure that does not require a via connecting the power supply layer 1, the first ground layer 2, and the signal layer 3 is used. A low-cost semiconductor device suitable for high-frequency signal transmission is realized without reflection and signal degradation.

  In this embodiment, the second ground layer 4 is suitable for higher frequencies than the microstrip line structure, and the second ground layer 4 is provided in the lowermost layer so as to be embedded in the insulating substrate 31 of the signal layer 3, thereby further preventing signal leakage. A stripline structure that can be effectively suppressed is adopted. In this stripline structure, through-hole-shaped vias 5 that pass through the signal layer 3 and connect the first and second ground layers 2 and 4 are provided, but the first and second ground layers 2 and 4 are connected. Therefore, it can be said that the stripline structure is more preferable in consideration of the further high frequency response.

  The stacked structure of each layer is the order in which the first ground layer 2 is sandwiched between the power supply layer 1 and the signal layer 3.

  Thereby, the noise to the signal layer 3 by the power supply layer 1 can be reduced.

  In addition, by arranging the power supply layer 1 as the uppermost layer (which can be said to be the lowermost layer when face-down mounting is described later), the design of the power supply layer 1 can be freely changed, so that the current can be increased by increasing the layer thickness. It is also possible to easily increase the amount of power supply.

  As for the wire bonding structure, for example, it is preferable to use a ribbon wire for one or both of the wires 71 and 72 of the power supply layer 1 and the first ground layer 2, and further, the power supply line 12 and the ground line 22 are It is preferable to increase the line width.

  Thereby, the ground effect between the semiconductor chip 100 and the power supply layer 1 and the first ground layer 2 can be enhanced, and the power supply can be efficiently connected. In addition, noise between the power supply layer 1, the first ground layer 2, and the signal layer 3 can be reduced. In addition, about a ribbon wire, the wire which can obtain the performance equivalent to a ribbon wire may be sufficient, and a wire thinner than a ribbon wire shall also be included.

  Moreover, since it is a wire bonding structure, it becomes possible to easily connect the heat radiating body to the back side of the semiconductor chip 100 (the side opposite to the circuit surface). As a radiator, not only the radiator plate 300 but also a radiator fin 400 can be provided (see FIG. 1).

  Thereby, the heat dissipation which is anxious about high frequency transmission can be improved easily and effectively.

  In the present embodiment, a ball grid array (BGA) is further provided, a solder ball 81 for the power supply layer 1, a solder ball 82 for the first ground layer 2, and a solder ball for the signal layer 3. 83 are provided on the corresponding power supply layer 1, first ground layer 2, and signal layer 3, respectively.

  More specifically, each layer has the insulating substrates 11, 21, 31 having different sizes as described above, and the inner peripheral end of the semiconductor chip opening 10 side has a staircase structure. On the other hand, the outer peripheral end also has a staircase structure in which the signal layer 3 protrudes outward. Solder balls 81, 82, 83 are attached to the power supply line 12, the ground line 22, and the signal line 32 on the insulating substrates 11, 21, 31 exposed in this staircase structure.

  In the BGA structure, the second ground layer 4 is not provided under the solder balls 81, 82, 83 in the stripline structure.

  When the second ground layer 4 is provided under the solder balls 81, 82, 83, a land (not shown) with which the solder balls 81, 82, 83 are in contact with the second ground layer 4 is provided. Since the signal is delayed due to the capacitance, the above structure can realize an inductive structure that is more preferable for transmitting a high-speed signal.

  The semiconductor device as described above can be handled as a semiconductor package (PKG), and can be mounted on the mother board 500 in a face-down manner as illustrated in FIGS.

  In the embodiment of FIG. 4, in order to connect the PKG BGA and the mother board 500, it corresponds to the staircase structure of each layer constituting the PKG, more specifically, the height of the BGA mounted on the staircase structure of each layer. A connection jig 501 having a combined staircase structure is installed on the mother board 500. The wiring extending from the connecting jig 501 to the mother board 500 is preferably a wiring surrounded by a ground, and is in the same state as the coaxial line, and suppresses signal deterioration from or to the PKG. In addition, semiconductor chip components can be arranged on the wiring portion of the mother board 500.

  In the embodiment of FIG. 5, the mother board 500 itself is processed into a staircase structure corresponding to the staircase structure of the PKG, and the PKG is embedded in the mother board 500. The signal line is an embedded strip line, and the solder ball portion is a microstrip line. Good transmission characteristics are realized, and signal deterioration from or to PKG is suppressed. Further, semiconductor chip components can be arranged on the wiring portion of the mother board 500, and further, there is an advantage that it can be made thinner even if PKG is mounted.

  4 and FIG. 5, when the solder balls 81, 82, 83 having the same diameter are used for each layer, the mounting using the step-like connection jig 501 and the mother board 500 are stepped. For example, when the connection jig 501 is difficult to adopt, or when the mother board 500 cannot be stepped or difficult, as shown in FIG. By installing solder balls 81, 82 and 83 having different sizes according to the size of the staircase, an embodiment is possible in which the ball height is made uniform and can be connected without processing the motherboard 500 or the like. is there.

  In the embodiment of FIG. 6, since the signal layer 3 is farthest from the mother board 500 at the time of mounting, the solder ball 83 having the maximum diameter is installed, and thereafter the first ground layer 2 and the power supply layer 1 are adjusted to be smaller in order. The solder balls 82 and 81 having the same diameter are adopted, and finally the height positions of the solder balls 81, 82 and 83 on the mother board 500 side are made the same. Thereby, since the connection height with the mother board 500 becomes uniform, the use of the connecting jig 501 in FIG. 4 and FIG.

  Hereinafter, an example of a manufacturing process of the semiconductor device according to the present embodiment will be described with reference to FIG. In the manufacturing process, the second ground layer 4 is omitted.

  First, as shown in FIG. 7A, a power supply layer 1 in which a power supply line 12, a ground line 22, and a signal line 32 are provided on insulating substrates 11, 21, 31 having openings 13, 23, and 33 at the center. The first ground layer 2 and the signal layer 3 are bonded together with an adhesive (not shown).

  Next, as shown in FIG. 7B, a heat dissipation plate 300 is attached to the power source layer 1, the first ground layer 2, and the signal layer 3 after bonding through an adhesive 301.

  Next, as shown in FIG. 7C, in the opening 10 for a semiconductor chip formed by overlapping the openings 13, 23, 33 of the power supply layer 1, the first ground layer 2, and the signal layer 3. The adhesive 200 is applied to the region on the heat dissipation plate 300 exposed at.

  Next, as shown in FIG. 7D, the semiconductor chip 100 is mounted on the heat sink 300 via the adhesive 200 and placed in the semiconductor chip opening 10.

  Next, as shown in FIG. 7E, the semiconductor chip 100 and each layer are wire-bonded. Specifically, the wire pad 101 (see FIG. 3) of the semiconductor chip 100 is connected to the power line 12, the ground line 22, and the signal line 32 of each layer exposed in the step structure by the wire 7. At this time, the wire 73 (see FIGS. 1 and 3) of the signal line 32 is the shortest as described above.

  Next, as shown in FIG. 7F, sealing is performed with a sealing resin 9. Specifically, the semiconductor chip opening 10 including the semiconductor chip 100 and the wire 7 is sealed.

  Then, a BGA is provided as shown in FIG. Specifically, the solder balls 8 are attached on the step structure provided on the outer peripheral portion of each layer.

  The semiconductor device assembled as described above can be mounted face down on the mother board 500 as described above.

  In the semiconductor device of the present embodiment as described above, the following materials and dimensions are one preferable example. Of course, it is not limited to this example.

-Sealing resin 9 ... Material = Epoxy-based insulating material-Solder ball 8 ... Diameter = 100 m to 600 m
-Wire 7 ... material Au, diameter = 25 micrometers-100 micrometers
Power supply line 12, ground line 22, signal line 32... Width = 10 μm to 100 μm, thickness = 5 μm to 30 μm, material = Cu
· Adhesive 301 ··· Material = Epoxy insulating material · Adhesive 200 · · · Material = Ag paste · Heat sink 300, heat sink 400 · · · Material = Al, SiO ₂ , AlN, etc. · Insulating substrates 11 and 21 , 31 ... Thickness = 10 µm to 100 µm, Dielectric constant ε _r = 2 to 5, Material = Polyimide, Liquid crystal polymer, BT resin, etc. · Ball land ... Diameter r _BL (see Fig. 2) = 100 µm to 600 µm
・ Via 5... Diameter = 50 μm to 200 μm
[Second Embodiment]
8 to 10 are a sectional view, a partially enlarged sectional view, and a plan view, respectively, showing another embodiment of the present invention.

  In the present embodiment, unlike the first embodiment, the BGA is provided on the back side.

  More specifically, in the stripline structure including the power supply layer 1, the first ground layer 2, the signal layer 3, and the second ground layer 4, the first ground layer 2 includes the power supply layer 1 and the signal layer. 3, and the power source layer 1, the first ground layer 2, and the signal layer 3 are connected to the semiconductor chip 100 accommodated in the semiconductor chip opening 10 provided in the central region thereof. The inner peripheral end of the semiconductor chip opening 10 side has a staircase structure and the inner peripheral end of the signal layer 3 is a semiconductor so that the wire 73 of the signal layer 3 is shortest. The position closest to the chip 100 is the same as in the first embodiment, and the outer peripheral end of each layer has a step structure as in the first embodiment. Description of other parts similar to those of the first embodiment is omitted.

  On the other hand, in this embodiment, in the staircase structure of the outer peripheral end portion, the outer peripheral end portion of the signal layer 3 is located closest to the semiconductor chip 100, and each step surface faces downward, that is, each layer is configured. The power supply line 12, the ground line 22, and the signal line 32 (see FIG. 9) provided on the insulating substrates 11, 21, 31 to be exposed are exposed downward at the outer peripheral end.

  Solder balls 81, 82, and 83 are provided on the exposed power supply line 12, ground line 22, and signal line 32.

  Thereby, in the signal layer 32, the wire 73 connected to the signal line 32 exposed upward at the inner end portion thereof, and the solder ball 83 connected to the signal line 32 exposed downward at the outer end portion thereof. The distance between the two is the shortest, the signal transmission line in the signal layer 32 is shortened, and a semiconductor device that can cope with higher speed transmission is realized.

  As described above, with the BGA provided on the back side, the heat radiating plate 300 and the heat radiating fins 400 as heat radiating bodies are provided on the front side so as to cover the entire semiconductor device.

  The semiconductor device of the present embodiment as described above can also be handled as the semiconductor package PKG similarly to the first embodiment. As illustrated in FIGS. 11 and 12, the semiconductor device is similar to that of FIGS. It can be mounted on the mother board 500 via a connecting jig 501 having a staircase structure corresponding to the staircase structure of the apparatus, or on the mother board 500 in which the staircase structure is directly formed. Further, as illustrated in FIG. 13, similarly to FIG. 6, by installing solder balls 81, 82, 83 having different sizes in each layer and making the connection height with the mother board 500 the same between the layers, Mounting that does not require the use of the connecting jig 501 or the processing of the mother board 500 is also possible.

  Hereinafter, an example of a manufacturing process of the semiconductor device according to the present embodiment will be described with reference to FIG. In the manufacturing process, the second ground layer 4 is omitted.

  First, as shown in FIG. 14A, a power supply layer 1 in which a power supply line 12, a ground line 22, and a signal line 32 are provided on insulating substrates 11, 21, 31 having openings 13, 23, and 33 in the center. The first ground layer 2 and the signal layer 3 are bonded together with an adhesive (not shown). Furthermore, a cover plate 6 having the opening 61 and made of the same material as that of the insulating substrates 11, 21, 31 is also bonded to these via an adhesive (not shown). Note that the opening 33 of the signal layer 3 is a concave shape having a bottom, unlike the through-shaped openings 13, 23, 61 of the other layers.

  Next, as shown in FIG. 14B, the power source layer 1, the first ground layer 2, the signal layer 3 and the openings 13, 23, 33, 61 of the cover plate 6 after the bonding are formed to overlap each other. Further, the adhesive 200 is applied to the inner bottom surface of the stepped semiconductor chip opening 10 obtained by scraping off the ball placement portion of one substrate. Next, as shown in FIG. 14C, the semiconductor chip 100 is mounted in the semiconductor chip opening 10 via the adhesive 200.

  Next, as shown in FIG. 14D, the semiconductor chip 100 and each layer are wire-bonded. Specifically, the wire pad 101 (see FIG. 3) of the semiconductor chip 100 and the power supply line 12, the ground line 22, and the signal line 32 of each layer are connected by the wire 7. At this time, as described above, the wire 73 (see FIGS. 8 and 10) of the signal line 32 is the shortest.

  Next, as shown in FIG. 14E, sealing is performed with a sealing resin 9. Specifically, a partial space in the semiconductor chip opening 10 including the wire 7 is sealed. At this time, the space on the semiconductor chip 100 that does not include the wire 7 is not sealed.

  Next, as shown in FIG. 14F, an adhesive 302 is applied onto the semiconductor chip 100 exposed in the space left without being sealed. The adhesive 302 has insulating properties and high thermal conductivity.

  Next, as shown in FIG. 14G, the heat sink 300 is mounted. The heat sink 300 and the semiconductor chip 100 are fixed by the adhesive 302.

  Then, a BGA is provided as shown in FIG. Specifically, the solder ball 8 is attached to the step surface exposed downward in the outer peripheral portion of each layer.

  The semiconductor device assembled as described above can be mounted face down on the mother board 500 as described above.

  In the semiconductor device of the present embodiment as described above, the following materials and dimensions are one preferable example. Of course, it is not limited to this example.

-Sealing resin 9 ... Material = Epoxy-based insulating material-Solder ball 8 ... Diameter = 100 m to 600 m
-Wire 7 ... material Au, diameter = 25 micrometers-100 micrometers
Power supply line 12, ground line 22, signal line 32... Width = 10 μm to 100 μm, thickness = 5 μm to 30 μm, material = Cu
· Adhesive 301 ··· Material = Epoxy insulating material · Adhesive 200 · · · Material = Ag paste · Heat sink 300, heat sink 400 · · · Material = Al, SiO ₂ , AlN, etc. · Insulating substrates 11 and 21 31 = thickness = 10 μm to 100 μm, dielectric constant ε _r = 2 to 5, material = polyimide, liquid crystal polymer, BT resin, etc. ・ Ball land—diameter r _BL (see FIG. 9) = 100 μm to 600 μm
・ Via 5... Diameter = 50 μm to 200 μm
-Adhesive 302 ... Material = Epoxy insulating material [Third embodiment]
15 to 17 are a sectional view, a partially enlarged sectional view, and a plan view, respectively, showing still another embodiment of the present invention.

  In the present embodiment, unlike the first and second embodiments, the outer end of each layer is not a staircase structure.

  More specifically, in the stripline structure including the power supply layer 1, the first ground layer 2, the signal layer 3, and the second ground layer 4, the first ground layer 2 includes the power supply layer 1 and the signal layer. 3, and the power source layer 1, the first ground layer 2, and the signal layer 3 are connected to the semiconductor chip 100 accommodated in the semiconductor chip opening 10 provided in the central region thereof. The inner peripheral end of the semiconductor chip opening 10 side has a staircase structure and the inner peripheral end of the signal layer 3 is a semiconductor so that the wire 73 of the signal layer 3 is shortest. The position closest to the chip 100 is the same as in the first and second embodiments. Description of other parts similar to those of the first and second embodiments is omitted.

  On the other hand, in the present embodiment, the outer peripheral end of each layer is not a staircase structure.

  Accordingly, it is not necessary to provide a staircase structure at the outer peripheral end portion where the solder ball 8 for secondary mounting is attached, and it is not necessary to provide a staircase structure on the mother board 500 (see FIGS. 4 and 5).

  In the present embodiment, it is preferable to reduce discontinuous points having different shapes as much as possible, for example, discontinuous points such as when connecting from the wiring to the via 5 and the vias 5, so that only one discontinuous point is set.

  As a result, the via 5 in the present embodiment includes the via 5 that connects the power line 12 of the power layer 1 and the signal line 32 of the signal layer 3, the power line 12 of the power layer 1, and the ground line 22 of the first ground layer 2. It is suppressed only by the via 5 connecting the two.

  The via 5 between the power supply line 12 and the signal line 32 needs to penetrate the ground line 22 of the first ground layer 2 provided between the power supply layer 1 and the signal layer 3. Is provided with a via opening 24 through which the via 5 is insulated from the ground line 22 (see FIG. 16).

  Hereinafter, an example of the manufacturing process of the semiconductor device according to the present embodiment will be described with reference to FIG. In the manufacturing process, the second ground layer 4 is omitted.

  First, as shown in FIG. 18A, a power supply layer 1 in which a power supply line 12, a ground line 22, and a signal line 32 are provided on an insulating substrate 11, 21, 31 having openings 13, 23, and 33 at the center. The first ground layer 2 and the signal layer 3 are bonded together with an adhesive (not shown).

  Next, as shown in FIG. 18B, vias 5 as described above are formed in the power supply layer 1, the first ground layer 2, and the signal layer 3 after bonding.

  Next, as illustrated in FIG. 18C, the heat dissipation plate 300 is attached through the adhesive 301.

  Next, as shown in FIG. 18D, inside the opening 10 for a semiconductor chip formed by overlapping the openings 13, 23, 33 of the power supply layer 1, the first ground layer 2, and the signal layer 3. The adhesive 200 is applied to the region on the heat dissipation plate 300 exposed at.

  Next, as shown in FIG. 18E, the semiconductor chip 100 is mounted on the heat sink 300 via the adhesive 200 and placed in the semiconductor chip opening 10.

  Next, as shown in FIG. 18F, the semiconductor chip 100 and each layer are wire-bonded. Specifically, the wire pad 101 (see FIG. 17) of the semiconductor chip 100 and the power supply line 12, the ground line 22, and the signal line 32 of each layer are connected by the wire 7. At this time, the wire 73 (see FIGS. 15 and 17) of the signal line 32 is the shortest as in the first and second embodiments.

  Next, as shown in FIG. 18G, sealing is performed with a sealing resin 9. Specifically, the semiconductor chip opening 10 including the semiconductor chip 100 and the wire 7 is sealed.

  Then, as shown in FIG. 18H, the BGA as described above is provided.

  The assembled semiconductor device can be mounted face-down on the mother board 500 in the same manner as in the first embodiment, but a staircase structure for connection to the mother board 500 is not necessary.

  In the semiconductor device of the present embodiment as described above, the following materials and dimensions are one preferable example. Of course, it is not limited to this example.

-Sealing resin 9 ... Material = Epoxy-based insulating material-Solder ball 8 ... Diameter = 100 m to 600 m
-Wire 7 ... material Au, diameter = 25 micrometers-100 micrometers
Power supply line 12, ground line 22, signal line 32... Width = 10 μm to 100 μm, thickness = 5 μm to 30 μm, material = Cu
· Adhesive 301 ··· Material = Epoxy insulating material · Adhesive 200 · · · Material = Ag paste · Heat sink 300, heat sink 400 · · · Material = Al, SiO ₂ , AlN · Insulating substrates 11 and 21 , 31 ... Thickness = 10 µm to 100 µm, Dielectric constant ε _r = 2 to 5, Material = Polyimide, Liquid crystal polymer, BT resin, etc. · Ball land ... Diameter r _BL (see Fig. 16) = 100 µm to 600 µm
・ Via opening 24... Diameter r _GND (see FIG. 16) = 100 μm to 600 μm according to land diameter r _BL
・ Via 5 ... 50 μm to 200 μm in diameter

Sectional drawing which shows 1st embodiment of this invention. The partially expanded sectional view of 1st embodiment. The top view of a first embodiment. Sectional drawing which showed the example of mounting to the motherboard of the semiconductor device which concerns on 1st embodiment. Sectional drawing which showed another example of mounting to the motherboard of the semiconductor device which concerns on 1st embodiment. Sectional drawing which showed another example of mounting to a motherboard. (A)-(G) is a figure for demonstrating an example of the manufacturing process of 1st embodiment. Sectional drawing which shows 2nd embodiment of this invention. The partially expanded sectional view of 2nd embodiment. The top view of 2nd embodiment. Sectional drawing which showed the example of a connection to the motherboard of the semiconductor device which concerns on 2nd embodiment. Sectional drawing which showed another example of the connection to the motherboard of the semiconductor device which concerns on 2nd embodiment. Sectional drawing which showed another example of mounting to a motherboard. (A)-(H) is a figure for demonstrating an example of the manufacturing process of 1st embodiment. Sectional drawing which shows 3rd embodiment of this invention. The partially expanded sectional view of 3rd embodiment. The top view of 3rd embodiment. (A)-(H) is a figure for demonstrating an example of the manufacturing process of 3rd embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Power supply layer 11 Insulating substrate 12 Power supply line 13 Opening 2 1st ground layer 21 Insulating substrate 22 Ground line 23 Opening 24 Via opening 3 Signal layer 31 Insulating substrate 32 Signal line 33 Opening 4 Second ground layer 5 Via 6 Cover plate 61 Opening 7, 71, 72, 73 Wire 8, 81, 82, 83 Solder ball 9 Sealing resin 10 Opening for semiconductor chip 100 Semiconductor chip 101 Wire pad 200 Adhesive 300 Heat sink 301 Adhesive 302 Adhesive 400 Radiation fin 500 Motherboard 501 Connection jig

Claims (12)

A wiring structure of a semiconductor device having a microstrip line structure including a power supply layer, a first ground layer, and a signal layer, or a strip line structure including a second ground layer,
The first ground layer is provided between the power supply layer and the signal layer,
The power supply layer, the first ground layer, and the signal layer are wire-bonded to the semiconductor chip housed in the semiconductor chip opening, and the wire for the signal layer is shortest so that the wire for the signal layer is the shortest. A wiring structure characterized in that the inner peripheral end portion on the side has a staircase structure and the inner peripheral end portion of the signal layer is located closest to the semiconductor chip.   2. The wiring structure according to claim 1, wherein the wire of the signal layer is within 1 mm.   3. The wiring structure according to claim 1, wherein one or both of the power supply layer and the ground layer are ribbon wires.   4. The wiring structure according to claim 1, wherein the wiring width of either one or both of the power supply layer and the ground layer is large.   5. The wiring structure according to claim 1, wherein the power supply layer is disposed on the uppermost layer.   The wiring structure according to claim 1, further comprising a ball grid array.   7. The wiring structure according to claim 6, wherein the second ground layer is not provided under the solder ball in the stripline structure.   A semiconductor device having the wiring structure according to claim 1.   The semiconductor device according to claim 8, wherein a heat radiator is provided on the back side of the semiconductor chip.   9. The semiconductor device according to claim 8, wherein the semiconductor device is connected to the mother board via a connection jig having a step structure adapted to the height of the solder ball of each layer.   9. The semiconductor device according to claim 8, wherein the semiconductor device is connected to a mother board having a staircase structure corresponding to the height of solder balls of each layer.   9. The semiconductor device according to claim 8, wherein the size of the solder balls in each layer is adjusted so that the connection height with the mother board is the same between the layers.

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