JP2004241642A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for efficiently removing a resist layer and manufacturing a conductive plug to embed a connection hole at an excellent yield, even when a reactive layer and a polymer layer are formed on a resist pattern surface by etching for connection hole formation. <P>SOLUTION: The manufacturing method of the semiconductor device comprises: (a) a process of forming first metal wiring above a semiconductor substrate; (b) a process of forming an inter-layer insulating film on the semiconductor substrate covering the first metal wiring; (c) a process of forming a resist pattern having an opening corresponding to the connection part of the first metal wiring on the inter-layer insulating film; (d) a process of anisotropically etching the interlayer insulating film with the resist pattern as an etching mask and forming the connection hole reaching the first metal wiring; (e) a process of supplying oxygen radicals and removing the reactive layer on the resist pattern surface; and (f) a process of treating the resist pattern surface with a liquid chemical containing an amine based organic solvent and removing at least reaction products by the anisotropic etching. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of etching a connection hole having a high aspect ratio in an interlayer insulating film using a resist pattern as an etching mask.
[0002]
[Prior art]
Multi-layer wiring is used for large-scale semiconductor devices. The wiring layers are insulated by an interlayer insulating film. A connection hole is formed in the interlayer insulating film for electrical connection between the wiring layers. In a situation where it is difficult to fill the connection hole with the upper wiring layer, a conductive plug is buried in the connection hole to form an electrical connection between the upper and lower wiring layers.
[0003]
Along with the high integration of semiconductor devices, a significant reduction in dimensions is required for the gate width of the MOS transistor, the width of the lower layer wiring, the diameter of the connection hole, and the like. In particular, the connection hole tends to be deeper as the hole diameter is reduced. In order to etch a connection hole having a high aspect ratio, which is the ratio of the depth to the hole diameter, it is necessary to perform anisotropic etching with increased plasma acceleration voltage Vpp and ion energy to ensure an etching shape.
[0004]
When anisotropic etching with high ion energy is performed on the interlayer insulating film and the lower layer wiring is exposed, the etched lower layer wiring metal reacts with the etching gas (fluorine, carbon), and the reaction product is organic or inorganic. A polymer of the compound is formed and adheres to the side wall and bottom surface of the connection hole. In addition, a reaction (altered) layer is formed on the resist surface exposed to high ion energy plasma. When ashing with oxygen plasma is performed on such a resist pattern, even if the resist pattern can be removed, the organic or inorganic polymer is oxidized, making it difficult to remove.
[0005]
Even if the conductive plug is embedded, an oxide layer is interposed between the conductive plug and the lower layer wiring, making it difficult to obtain an electrical contact with a sufficiently low resistance. Further, the oxide layer serves as a degassing source, and obstructs ohmic contact of the conductive plug in the subsequent process.
[0006]
EKC265, EKC270, (EKC Technology) ACT935, ACT936, (Ashland) (ST-26S (Nissan Chemical) SPR-201 (Kanto Chemical) Reps-ssc (Sumitomo Chemical)), etc. Although amine-based chemicals are known, oxidized reaction products cannot be sufficiently removed with amine-based chemicals.
[0007]
Then, following anisotropic etching, a method of removing the polymer of the reaction product adhering to the side wall and bottom surface of the connection hole with an amine chemical solution is taken. However, the reaction product is water repellent and prevents the penetration of the chemical solution. The reaction can be promoted by increasing the temperature of the chemical treatment. For example, the temperature of the chemical solution is set to 65 ° C. to 85 ° C., and wet treatment is performed for 10 minutes to 25 minutes.
[0008]
8A to 8C show a connection hole forming process according to the related art. 8A and 8B, a dense pattern region with many connection holes is shown on the left side, and a sparse pattern region with few connection holes is shown on the right side.
[0009]
As shown in FIG. 8A, an element isolation region 2 is formed in a semiconductor substrate 1 by shallow trench isolation, and necessary wells are formed by ion implantation. A gate insulating film is formed on the active region surrounded by the element isolation region 2, and a gate electrode 3 made of polycrystalline silicon, polycide, or the like is formed thereon. After ion implantation of the extension region of the source / drain region, a sidewall spacer 4 such as a silicon oxide film is formed on the sidewall of the gate electrode 3. High concentration source / drain regions are ion-implanted outside the sidewall spacer to form a MOS structure.
[0010]
The MOS structure is covered with a first interlayer insulating film 7 such as silicon oxide, and the surface is planarized by chemical mechanical polishing (CMP) or the like as necessary. Contact holes are formed in the first interlayer insulating film 7 using photolithography and etching, and conductive plugs 8 such as polycrystalline silicon and tungsten are embedded. For example, after sputtering the Ti layer, a blanket tungsten layer is deposited by chemical vapor deposition (CVD), and unnecessary portions are removed by CMP.
[0011]
On the first interlayer insulating film 7, a first wiring layer is formed by stacking, for example, a Ti layer 11a, an Al layer 11b, and a Ti layer 11c, and patterned by photolithography and etching to form the first wiring 11. The first wiring 11 is covered with a second interlayer insulating film 12 such as silicon oxide. A resist pattern PR having an opening corresponding to the connection portion of the first wiring is formed on the second interlayer insulating film 12.
[0012]
Using the resist pattern PR as an etching mask, the second interlayer insulating film 12 is etched to expose the connection portion of the first wiring 11. The two connection holes on the left side of the figure have a borderless contact structure that exposes the end of the first wiring. In order to reliably form the connection hole, the etching for forming the connection hole is over-etched to about 1.5 times the depth of the target connection hole. The surface of the resist pattern PR is exposed to high ion energy plasma to form a reaction layer PRx. The exposed first wiring is exposed to an etching gas to generate an organic or inorganic polymer 13 as a reaction product, and in particular, adheres to the side wall and bottom surface of the connection hole and the resist surface. .
[0013]
As shown in FIG. 8B, a wet chemical treatment is used to remove the organic or inorganic compound polymer on the side walls and bottom of the connection holes using a treatment chemical solution containing an amine organic solvent as a main component. The treatment (chemical solution) temperature is 65 ° C to 85 ° C, and the treatment time is about 10 minutes to 25 minutes. Subsequently, the substrate is carried into the plasma ashing chamber, and an ashing process is performed at a high frequency power of 1500 W, a working gas O ₂ : N ₂ = 2000: 100, a stage temperature of 250 ° C. for about 60 seconds, and the remaining resist is removed.
[0014]
When the chemical treatment temperature is 65 ° C., all resist cannot be removed even by the wet treatment and the ashing treatment, and the resist residue RS remains on the surface. This residue RS may move on the substrate surface and cover the formed connection hole. In this state, even if the conductive plug is formed in the connection hole, the conductive plug is not formed in the connection hole covered with the resist residue RS.
[0015]
When the chemical treatment temperature is set to a high temperature, for example, 85 ° C., the resist residue RS hardly remains, but in the borderless contact where the shoulder portion of the lower layer wiring is exposed, the Al layer of the main wiring layer 11b is dissolved, resulting in poor contact. It may happen. Further, when the chemical solution is heated to a high temperature, the lifetime of the chemical solution is shortened because moisture evaporation occurs violently because the standing temperature is high.
[0016]
FIG. 8C is a graph showing the yield when the ashing process is performed following the wet process using the amine chemical solution. The horizontal axis represents the chemical treatment temperature of the wet treatment, and the vertical axis represents the yield in%. When the processing temperature of the wet processing is 65 ° C., the yield is remarkably low at 20% or less. When the processing temperature is raised to 75 ° C. and 85 ° C., the yield is improved, but other problems such as the above-described contact failure and chemical life reduction also occur.
[0017]
The present inventor examined in wet processing what kind of influence is caused by exposing the resist surface to etching plasma. When the etching process was not performed on the resist surface, the resist could be removed by performing a wet process at 75 ° C. for 1 minute. On the other hand, when the etching process is performed on the resist formed on the entire surface of the wafer, it is impossible to remove the resist layer even if the wet process at 75 ° C. is performed for 30 minutes.
[0018]
It is clear that a reaction layer is formed on the resist surface by etching treatment, and once the reaction layer is formed, the resist layer cannot be removed by wet treatment. Since the reaction layer on the resist surface cannot be removed with an amine organic solvent, it is considered that the resist residue cannot be removed by wet treatment.
[0019]
When connection holes exist in the wafer, it was observed that the degree of resist residue varies depending on the distribution of connection holes. When the entire surface is covered with resist and there is no connection hole, the resist cannot be removed by wet processing. When connection holes are present, the resist becomes easier to remove as the distribution density of the connection holes increases.
[0020]
Japanese Patent Application Laid-Open No. 2001-176855 proposes converting the resist surface from water-repellent to hydrophilic by performing oxygen plasma ashing while the substrate is heated. It is described that the surface of a resist layer and a polymer layer is converted to hydrophilicity by reacting with oxygen.
[0021]
Japanese Patent Application Laid-Open No. 2002-18379 proposes a method of stripping a resist using ultraviolet rays, ozone, and water vapor.
Japanese Patent Application No. 2002-138610 proposes a method of removing a resist layer by irradiating ultraviolet rays onto a resist surface that has been altered by dry etching and then treating it with an amine-based chemical solution.
[0022]
[Patent Document 1]
JP 2001-176855 A [Patent Document 2]
JP 2002-18379 A [Patent Document 3]
Japanese Patent Application No. 2002-138610
[0023]
[Problems to be solved by the invention]
An object of the present invention is to provide a semiconductor device that efficiently removes a resist layer and manufactures a conductive plug filling a connection hole with a high yield even when a reaction layer or a polymer layer is formed on the surface of the resist pattern by etching for forming a connection hole. It is to provide a manufacturing method.
[0024]
Another object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a multilayer wiring structure in which upper and lower wirings are connected by a conductive plug with a high yield.
[0025]
[Means for Solving the Problems]
According to one aspect of the present invention, (a) a step of forming a first metal wiring over the semiconductor substrate, and (b) a step of covering the first metal wiring and forming an interlayer insulating film on the semiconductor substrate. And (c) forming a resist pattern having an opening corresponding to the connection portion of the first metal wiring on the interlayer insulating film, and (d) using the resist pattern as an etching mask, Forming a connection hole reaching the first metal wiring by anisotropic etching; (e) supplying oxygen radicals to remove a reaction layer on the resist pattern surface; and (f) an amine organic solvent. And a step of treating the resist pattern surface with a chemical solution containing at least a reaction product from at least the anisotropic etching.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A to FIG. 4H are cross-sectional views and graphs schematically showing main steps of a semiconductor device manufacturing method according to an embodiment of the present invention.
[0027]
As shown in FIG. 1A, an element isolation region 2 such as shallow trench isolation is formed on the surface of a semiconductor substrate 1 such as a silicon substrate, and a MOS transistor or the like is formed in an active region surrounded by the element isolation region 2. The semiconductor element is formed.
[0028]
In the figure, a gate electrode 3 such as polycrystalline silicon or polycide is formed on the surface of the active region via a gate insulating film such as a thermal oxide film, and after ion implantation for extension region formation, Side wall spacers 4 such as silicon oxide are formed. After the sidewall spacer 4 is formed, ion implantation for forming a high concentration source / drain region is performed.
[0029]
A first interlayer insulating film 7 is formed of silicon oxide or the like so as to embed the gate electrode structure. The surface of the first interlayer insulating film 7 is planarized by CMP or the like as necessary.
A connection hole is formed in the first interlayer insulating film 7 by photolithography and etching to expose the source / drain region of the MOS transistor. By sputtering a Ti layer in the connection hole and subsequently forming a blanket tungsten layer by CVD, the conductive plug 8 for filling the connection hole is formed. An unnecessary metal layer on the surface of the first interlayer insulating film 7 is removed by CMP or the like, and the embedded plug 8 is left.
[0030]
On the surface of the first interlayer insulating film 7, a first wiring layer 11 made of a laminate of, for example, a Ti layer 11a, an Al layer 11b, a Ti layer 11c, and the like is formed and patterned using photolithography and etching. The lamination of the first wiring is not limited to the above example. For example, a TiN layer or a Ta layer can be used as the barrier layer. The main wiring is not limited to the Al layer, and an Al alloy layer or the like may be used. An antireflection film such as SiN may be formed on the surface.
[0031]
After forming the first wiring 11, a second interlayer insulating film 12 such as silicon oxide is formed to cover the first wiring 11. A resist pattern PR is formed on the surface of the second interlayer insulating film 12. The resist pattern PR has an opening in a region corresponding to the connection portion of the first wiring.
[0032]
In the drawing, the via hole dense region where the connection holes are densely distributed is shown on the left side, and the via hole sparse region where the connection holes are sparsely distributed is shown on the right side.
As shown in FIG. 1B, a semiconductor substrate is placed on a stage maintained at 10 ° C., CF ₄ : CHF ₃ : Ar = 40: 40: 150 is used as an etching gas, and RF power of 2000 W is applied to the upper electrode. Then, 1200 W of HF power is applied to the lower electrode, and anisotropic etching by RIE is performed. The surface of the resist pattern PR is exposed to etching plasma to form a reaction layer PRx. The second interlayer insulating film 12 exposed in the opening of the resist pattern PR is anisotropically etched to form a connection hole.
[0033]
When the first wiring 11 is exposed at the bottom of the connection hole, the metal of the first wiring and the etching gas react to generate an organic or inorganic polymer as a reaction product. This polymer adheres to the side wall and the bottom surface of the connection hole to form a polymer deposit 13. Note that the most polymer adheres to the resist layer surface. After the first wiring 11 is exposed, overetching of about 50% is further performed so that the first wiring is completely exposed on the bottom surface of the connection hole.
[0034]
When the etching is completed, a reaction layer PRx is formed on the surface of the resist pattern PR, and an organic or inorganic polymer 13 as a reaction product is attached on the surface of the connection hole.
[0035]
As shown in FIG. 2C, oxygen radical O ^* is supplied onto the surface of the semiconductor substrate to remove the surface reaction layer.
As a method for supplying oxygen radicals, for example, O ₂ : H ₂ N ₂ : CF ₄ = 2000: 100: 50 is supplied as a working gas, and excited by 1700 W μ-wave to generate plasma. O ₂ is a main source gas for generating oxygen radicals, and H ₂ N ₂ is a gas having a function of activating oxygen. A substrate is placed on a stage set at 270 ° C. in a downflow region downstream of the plasma, and a downflow process is performed for 10 seconds. Ions in the plasma disappear and oxygen radicals are supplied onto the resist layer surface.
[0036]
FIG. 7A shows an example of a plasma downflow processing apparatus. Oxygen gas is introduced from the gas inlet 300 and the plasma is excited by the μ wave from the μ wave chamber 301. Downflow downstream of the plasma flows on the wafer 303 through the diffusion plate 302.
Ions have disappeared at the position of the wafer 303, and oxygen radicals remain. Wafer 303 is held by lift pins 304 and heated by lamp heater 305.
[0037]
The working gas is not limited to the above example. Various working gases capable of generating oxygen radicals could be employed. The plasma downflow processing apparatus is not limited to the above. For example, a plasma downflow apparatus that includes a punching metal and does not allow ions to pass downstream of the punching metal may be used.
[0038]
As shown in FIG. 2 (D), after the oxygen radical treatment, the substrate is carried into a batch type post-treatment apparatus as shown in FIG. 7 (B), for example, and an amine chemical solution AM is supplied from above to perform a wet treatment. Do.
[0039]
In FIG. 7B, the chemical solution is introduced from the chemical solution introduction port 107, and the chemical solution is blown out from the nozzle 109. The direction in which the chemical solution is blown out changes according to the rotation of the rotor rotation shaft. The processed chemical solution is discharged from the chemical solution discharge port 108.
[0040]
As the amine chemical solution, EKC265, EKC270 (EKC Technology), ACT935, ACT936 (Ashland), ST-26S (Nissan Chemical), SPR-201 (Kanto Chemical), Reps-ssc (Sumitomo Chemical) or the like is used.
[0041]
The organic or inorganic compound polymer formed on the side wall or bottom surface of the connection hole is removed by wet treatment with the amine chemical solution.
The wet treatment conditions are, for example, a treatment temperature of 65 ° C. to 85 ° C. and a treatment time of about 10 minutes to 25 minutes.
[0042]
Thereafter, ashing is performed to remove the remaining resist pattern. If necessary, wet treatment such as washing after ashing is performed.
FIG. 3E is a graph showing the results of examining how the contact angle of the resist layer surface with water changes due to the oxygen radical treatment by plasma downflow. The horizontal axis indicates the processing time in seconds, and the vertical axis indicates the contact angle in degrees.
[0043]
In the initial state, the contact angle is as high as about 90 degrees to 100 degrees, but as the process proceeds, the contact angle rapidly decreases, and the contact angle decreases to 10 degrees or less after 5 seconds of processing. When the oxygen radical treatment was performed for 10 seconds or longer, the resist layer was completely removed by the next wet treatment. When the resist is completely removed by the wet process, the ashing process may be omitted.
[0044]
As shown in FIG. 3F, a Ti layer 14 is formed as a barrier layer, for example, by sputtering on the semiconductor substrate surface from which the resist pattern has been removed, and then a blanket tungsten layer 15 is formed by CVD. Since the resist pattern is completely removed and there is no residue, the buried conductive layers 14 and 15 form good electrical contact with the first wiring 11.
[0045]
As shown in FIG. 4G, CMP is performed to remove the W layer 15 and the Ti layer 14 on the surface of the second interlayer insulating film 12 to form a flat surface.
As shown in FIG. 4H, for example, a Ti layer 17a, an Al layer 17b, and a Ti layer 17c are stacked on the surface of the second interlayer insulating film on which the conductive plug is formed, and patterned by photolithography and etching. Thus, the second wiring 17 is formed.
[0046]
If necessary, an interlayer insulating film for embedding the second wiring is formed, a connection hole is formed, a conductive plug is formed, and a third wiring is formed on the surface. The number of wiring layers can be increased or decreased arbitrarily.
[0047]
In the above-described embodiment, oxygen radicals are supplied by plasma downflow. The method for supplying oxygen radicals is not limited to plasma downflow.
5A and 5B are cross-sectional views and graphs for explaining a method of manufacturing a semiconductor device according to another embodiment of the present invention. First, the steps shown in FIGS. 1A and 1B are performed to form connection holes. In this state, the reaction layer PRx is formed on the surface of the resist layer PR, and the polymer layer 13 is deposited on the side wall and the bottom surface of the connection hole.
In this state, the substrate is placed in the atmosphere, and ultraviolet rays UV are irradiated from above. Oxygen in the atmosphere is activated by ultraviolet irradiation, and oxygen radicals are generated.
[0048]
FIG. 7C illustrates an example of an ultraviolet irradiation device. A wafer 200 is placed on the stage 201 and irradiated with ultraviolet rays from an upper low-pressure mercury lamp 202. A heater 203 is provided below the stage 201 and can heat the wafer 200 to a desired temperature.
[0049]
As an ultraviolet ray source, a UV curing device that supplies ultraviolet rays having peak wavelengths of 185 nm and 254 nm was used. 185 nm and 254 nm are absorption wavelengths of oxygen, and oxygen radicals can be efficiently generated by irradiation with ultraviolet rays having this wavelength. The stage temperature was set to 100 ° C., and 40 mW / cm ² of ultraviolet light was irradiated for about 300 seconds, for example.
[0050]
After the ultraviolet irradiation, a wet treatment mainly containing an amine-based organic solvent as in the above examples was performed, and further ashing was performed.
FIG. 5B is a graph showing changes in the contact angle due to the above-described ultraviolet irradiation. The horizontal axis indicates the treatment time of ultraviolet irradiation in unit seconds, and the vertical axis indicates the contact angle in unit degrees.
[0051]
In the initial state, the contact angle is about 90 to 100 degrees as in the case of FIG. The contact angle decreases with increasing UV irradiation time. The contact angle becomes 5 degrees or less by ultraviolet irradiation for about 180 seconds. In the notch portion, the contact angle is slightly large, and the contact angle is about 10 degrees after 180 seconds of processing. When the processing for 360 seconds was performed, all the contact angles were 5 degrees or less regardless of the position on the wafer. When the above treatment for about 250 seconds or more was performed, the resist formed on the entire surface of the substrate by the subsequent wet treatment could be removed.
[0052]
The wavelength of ultraviolet light is not limited to 185 nm and 254 nm.
The case of irradiating with a wavelength of 345 nm of an ultraviolet source widely used for general points will be described below. Irradiation with ultraviolet rays of 345 nm was performed for 120 seconds at an energy of 40 mW / cm ² at a stage temperature of 190 ° C. Thereafter, the same wet treatment with an amine organic solvent as described above was performed, and further ashing was performed.
[0053]
FIG. 6A is a graph showing changes in contact angle due to ultraviolet irradiation. The horizontal axis indicates the processing time in unit seconds, and the vertical axis indicates the contact angle in unit degrees. In the initial state, the contact angle was about 90 degrees, but the contact angle gradually decreased as the ultraviolet light was irradiated. The contact angle decreased to about 80 degrees by the ultraviolet irradiation for about 160 seconds. However, this ultraviolet irradiation does not remove the resist layer in the next wet treatment.
[0054]
FIG. 6B is a graph showing the change in the number of defects as a result when the processing temperature is changed. The horizontal axis indicates the processing temperature in ° C., and the vertical axis indicates the number of defects. When the processing temperature is set to 100 ° C. to 150 ° C., the number of defects is reduced by about one digit as compared with the processing at the processing temperature of 0 to 50 ° C. However, if the temperature is out of this range, the number of defects increases.
[0055]
FIG. 6C is a graph showing changes in the number of defects with respect to the processing time. The horizontal axis indicates the processing time in unit seconds, and the vertical axis indicates the number of defects. When the process is started, the number of defects rapidly decreases, and the number of defects is reduced by one digit or more by the process for about 30 seconds as compared with the process for about 10 seconds or less. Thereafter, the number of defects once increases slightly and then gradually decreases. By performing processing for about 30 seconds or more, the number of defects can be reduced by one digit or more as compared with processing for about 10 seconds or less.
[0056]
FIG. 6D is a graph showing the results of examining the change in yield when the surface treatment is performed and when the surface treatment is not performed. The horizontal axis represents the wet processing temperature, and the vertical axis represents the yield. When surface treatment is performed, the yield is 90% or more even when the temperature of the wet treatment is 65 ° C., and when the temperature is raised to 75 ° C., the yield increases. When the surface treatment was not performed, the yield was as low as 30% or less when the wet treatment temperature was 65 ° C., and the yield increased to almost the same as when the temperature was raised to 75 ° C. and the surface treatment was performed. Although it is possible to increase the yield without performing surface treatment, the temperature condition becomes severe. If the process conditions change, the yield is likely to decrease, and the process margin becomes narrower.
[0057]
As shown in FIG. 6A, ultraviolet rays having a wavelength of 345 nm reduce the contact angle, but the degree is low. As shown in FIGS. 3E and 5B, the contact angle is greatly reduced when exposed to oxygen radicals in plasma downflow or when irradiated with ultraviolet rays having wavelengths of 185 nm and 254 nm. It will be apparent that higher yields can be expected when the contact angle is greatly reduced in this way.
[0058]
Hereinafter, the present invention has been described along examples, but the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0059]
【The invention's effect】
With a high yield, a connection hole with a high aspect ratio can be formed and a conductive plug can be embedded.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the invention.
FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
3A and 3B are a graph and a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the invention.
FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first example of the invention.
5A and 5B are a cross-sectional view and a graph showing a method for manufacturing a semiconductor device according to a second embodiment of the invention.
FIG. 6 is a graph for explaining another embodiment of the present invention.
FIG. 7 is a cross-sectional view showing a processing apparatus used in an embodiment of the present invention.
8A and 8B are a cross-sectional view and a graph showing a method for manufacturing a semiconductor device according to related technology.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation region 3 Gate electrode 4 Side wall spacer 7 1st interlayer insulation film 8 Conductive plug 11 1st wiring 12 2nd interlayer insulation film 13 Reaction product PR Photoresist layer PRx (Photoresist layer) Reaction layer O ^* Oxygen radical AM Amine-based chemical solution 14 Ti layer 15 W layer 17 Second wiring UV UV 107 Chemical solution inlet 108 Chemical solution outlet 109 Nozzle 110 Rotor rotating shaft 300 Gas inlet 301 μ-wave 302 Diffuser plate 303 Wafer 304 Lift pin 305 Lamp heater

Claims (5)

(A) forming a first metal wiring above the semiconductor substrate;
(B) forming an interlayer insulating film on the semiconductor substrate so as to cover the first metal wiring;
(C) forming a resist pattern having an opening corresponding to the connection portion of the first metal wiring on the interlayer insulating film;
(D) anisotropically etching the interlayer insulating film using the resist pattern as an etching mask to form a connection hole reaching the first metal wiring;
(E) supplying oxygen radicals and removing the reaction layer on the resist pattern surface;
(F) A method of manufacturing a semiconductor device, comprising: treating the resist pattern surface with a chemical solution containing an amine-based organic solvent to remove at least the reaction product by the anisotropic etching. The method of manufacturing a semiconductor device according to claim 1, wherein the step (e) includes exposing the semiconductor substrate to a plasma downflow of a gas containing oxygen. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (e) includes irradiating ultraviolet rays having a wavelength that generates oxygen radicals in an atmosphere containing oxygen. The method of manufacturing a semiconductor device according to claim 3, wherein the ultraviolet rays have peak wavelengths of 185 nm and 254 nm. further,
(G) The manufacturing method of the semiconductor device of any one of Claims 1-4 including the process of performing the ashing using oxygen plasma after the said process (f), and removing the remaining resist.

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