JP2004240818A - Clock generation circuit and integrated circuit equipped therewith - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock generation circuit capable of avoiding a long-term stop of clock output without adding a circuit for oscillating an auxiliary oscillator and normally operating a circuit in a subsequent stage even in the event of a short-period lock releasing of a PPL circuit. <P>SOLUTION: In this clock generation circuit 10, a selector circuit 15 is controlled by a select signal 1f from a selector control circuit 14, so that the selector circuit outputs an input clock 1a instead of a PLL clock 1b when the period of the PLL circuit 11 being in an unlock state exceeds a predetermined value. Accordingly, addition of a circuit for oscillating the auxiliary oscillator is dispensed with, and frequent clock switching as in the past can be avoided to prevent the unstable operation of the circuit in the subsequent stage. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock generation circuit having a PLL (phase locked loop) circuit, and for example, to a clock generation circuit that supplies an operation clock to a logic circuit of an integrated circuit.
[0002]
[Prior art]
As a conventional technique for preventing malfunction of a subsequent circuit when the PLL circuit is out of lock, as a conventional technique, an unlock signal of the PLL circuit is counted, and the unlock signal is output from the PLL circuit during a period in which the unlock signal is active. There is a technique that stops supplying a PLL clock to a subsequent circuit (for example, see Patent Document 1).
[0003]
However, when this conventional technique is used, while the PLL circuit is in the unlocked state, there is a disadvantage that the clock supply to the subsequent stage is cut off and the latter stage circuit is completely stopped.
[0004]
In order to solve this drawback, there is a conventional technique of switching to a clock from a spare oscillator during a period when the PLL circuit is out of lock (for example, see Patent Document 2). In this conventional technique, a clock from a spare oscillator is selected during a period when an unlock signal of a PLL circuit is active, and a PLL clock is selected as a clock to be supplied to a subsequent stage during a period when the unlock signal is non-active. . According to the latter prior art, the clock from the spare oscillator is supplied to the subsequent stage even during the period when the PLL circuit is unlocked, so that the latter circuit is completely stopped. Although the drawback is improved, there is a drawback that a spare oscillator is required and the cost is increased.
[0005]
Further, in the latter prior art, since the clock is switched by the unlock signal itself of the PLL circuit, the clock is switched by the selector circuit at the same time when the unlock signal changes from non-active to active. For this reason, in the case where a short-term unlock state and a return to the locked state occur repeatedly in the PLL circuit for a short period of time due to mild disturbance or the like, clock switching frequently occurs.
[0006]
[Patent Document 1]
JP-A-2-104022 (FIG. 1)
[Patent Document 2]
Japanese Patent Application Laid-Open No. 4-148403 (FIG. 1)
[0007]
[Problems to be solved by the invention]
As described above, the former conventional technique has a disadvantage that the clock supply to the subsequent stage is stopped when the PLL circuit is unlocked in the clock generation circuit including the PLL circuit. However, there is a disadvantage that it is necessary to add a circuit for oscillating a spare oscillator in order to avoid the supply stop of the clock.
[0008]
Therefore, an object of the present invention is to prevent a clock output from being stopped for a long period of time without adding a circuit for oscillating a spare oscillator, and even if a short-term unlocking of a PLL circuit occurs, An object of the present invention is to provide a clock generation circuit capable of achieving a normal operation of a circuit.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a clock generation circuit according to the present invention includes a PLL circuit,
A selector that receives at least an input clock input to the PLL circuit and a PLL clock output from the PLL circuit, and selects and outputs one signal from a plurality of signals including the input clock and the PLL clock. Circuit and
A lock detection circuit that detects whether the PLL circuit is in an unlocked state and outputs an unlock signal indicating whether the PLL circuit is in an unlocked state;
The unlock signal is input from the lock detection circuit, a period during which the unlock signal indicates the unlock state is counted, and a detection signal indicating whether the counted value has reached a predetermined value is output. A counter circuit to
The detection signal is input from the counter circuit, and the unlock signal is input from the lock detection circuit, and the selector circuit is controlled based on a value of the detection signal and a value of the unlock signal. A selector control circuit that outputs the select signal of
The selector circuit is controlled by a select signal from the selector control circuit, and outputs the input clock in place of the PLL clock when a period during which the PLL circuit is in an unlocked state exceeds a predetermined value. It is characterized by.
[0010]
In the clock generation circuit according to the present invention, the selector circuit is controlled by a select signal from the selector control circuit, and when the period during which the PLL circuit is in the unlocked state exceeds a predetermined value, the selector circuit switches to the PLL clock. And outputs the input clock.
[0011]
Therefore, according to the present invention, when the period during which the PLL circuit is in the unlocked state exceeds a predetermined value, the input clock to the PLL circuit is replaced with the PLL clock instead of the conventional spare oscillator. Is output, there is no need to add a circuit for oscillating a spare oscillator. Further, if the period during which the PLL circuit is in the unlocked state does not exceed a predetermined value, switching from the PLL clock to the input clock is not performed, so that frequent clock switching as in the related art can be avoided. In addition, the operation of the subsequent circuit will not be unstable.
[0012]
Therefore, according to the present invention, it is possible to prevent the clock output from stopping for a predetermined period of time without adding a circuit for oscillating a spare oscillator, and even if the PLL circuit is unlocked, Can operate normally.
[0013]
In one embodiment, in addition to the input clock and the PLL clock, the selector circuit receives a fixed logic value, selects a PLL clock, and outputs the selected period. During the period between the time when the input clock is selected and output, the fixed logic value is selected and output.
[0014]
In the clock generation circuit of this embodiment, the fixed logic value is selected and output during a period between the period of selecting and outputting the PLL clock and the period of selecting and outputting the input clock. Therefore, according to this embodiment, as an emergency process when the PLL circuit falls into the unlocked state, a logic value fixed to the subsequent circuit can be output, and the risk of malfunction of the subsequent circuit can be eliminated. .
[0015]
In one embodiment, the operation clock input to the counter circuit is the input clock input to the PLL circuit.
[0016]
In the clock generation circuit of this embodiment, since the operation clock input to the counter circuit is the input clock input to the PLL circuit, an operation clock dedicated to the counter circuit is not required, and the circuit is simplified.
[0017]
In one embodiment, the selector control circuit has a state machine that outputs a state signal based on the detection signal and the unlock signal. Generate a signal.
[0018]
In the clock generation circuit of this embodiment, the selector control circuit can easily generate a select signal for controlling the selector circuit based on the state signal output from the state machine.
[0019]
In one embodiment, the clock generation circuit uses the operation clock input to the state machine as the input clock input to the PLL circuit.
[0020]
In the clock generation circuit of this embodiment, the operation clock input to the state machine is the input clock input to the PLL circuit. Therefore, an operation clock dedicated to the state machine is not required, and the circuit is simplified.
[0021]
Further, an integrated circuit according to one embodiment includes the clock generation circuit and a logic circuit, and uses an output clock output from the clock generation circuit as an operation clock input to the logic circuit.
[0022]
In the integrated circuit of this embodiment, the output clock can be stably supplied to the logic circuit, and an integrated circuit that can perform a stable operation while suppressing a malfunction of the logic circuit can be realized.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail based on the illustrated embodiment.
[0024]
FIG. 1 is a block diagram showing an embodiment of the clock generation circuit of the present invention, and FIG. 2 is a timing chart for explaining the operation of this embodiment.
[0025]
As shown in FIG. 1, a clock generation circuit 10 of this embodiment includes a PLL circuit 11, a lock detection circuit 12, a counter circuit 13, a selector control circuit 14, and a selector circuit 15, and further receives an input clock 1a. It has an input terminal 10A and an output terminal 10G for outputting an output clock 1g output from the selector circuit 15. The output terminal 10G of the clock generation circuit 10 is connected to the clock input terminal 16A of the logic circuit 16.
[0026]
An input clock 1a is input to an input terminal 10A of the clock generation circuit 10, and an input clock 1a is input to a clock input 11A of the PLL circuit 11. The PLL circuit 11 outputs a high-speed clock obtained by multiplying the frequency of the input clock 1a as the PLL clock 1b from the multiplied clock output 11B to the input 1 of the selector circuit 15 and the comparison signal input 12B of the lock detection circuit 12.
[0027]
The lock detection circuit 12 compares the phase of the input clock 1a input to the reference signal input 12A with the phase of the PLL clock 1b input to the comparison signal input 12B, and determines whether the PLL circuit 11 is in the unlocked state. It is determined whether or not it is in the locked state, and an unlock signal 1c indicating the determination result is output from the unlock output 12C. The unlock signal 1c becomes active when the PLL circuit 11 is in an unlocked state and is unlocked. Here, since the unlock signal 1c is a high active signal, it takes a logical value 1 when active.
[0028]
The unlock signal 1c output from the lock detection circuit 12 is input to the enable input 13A of the counter circuit 13 and the condition input 1 of the selector control circuit 14.
[0029]
The counter circuit 13 counts a period in which the unlock signal 1c is active indicating the unlock state, and counts a period in which the PLL circuit 11 is in the unlock state (unlocked state).
[0030]
In this embodiment, the counter circuit 13 is constituted by an 8-bit down counter. In the counter circuit 13, the initial value is F, and when the count value 1h takes the value 0, the underflow signal 1d as a detection signal is activated (see reference numeral 210 in FIG. 2). The initial value of the counter circuit 13 and the number of bits of the counter may be appropriately adjusted by the system.
[0031]
In this embodiment, since the underflow signal 1d is a high active signal, it takes a logical value 1 when active and a logical value 0 when inactive. The unlock signal 1c is input to the enable input 13A of the counter circuit 13. During the period in which the unlock signal 1c is active, the count operation is performed by the input clock 1a connected to the clock input 13B. When the unlock signal 1c becomes non-active, the count value 1h is returned to the initial value F (see reference numeral 220 in FIG. 2).
[0032]
In addition, the selector circuit 15 outputs the PLL clock 1b input to the input 1 and the input clock input to the input 2 according to the truth table shown in FIG. 6 based on the value of the select signal 1f input to the select input 15E. 1a, one of the fixed value '0', which is a logical value input to the input 3, is alternatively derived with respect to the output 15D.
[0033]
The select input 15E of the selector circuit 15 is connected to the select output 14B of the selector control circuit 14, and receives the select signal 1f from the select output 14B. In the selector circuit 15, as described later, when switching between the input 1 and the input 2, that is, when switching between the PLL clock 1 b and the input clock 1 a having different periods, the input signal temporarily passes through the input 3 (fixed value 0). This prevents a subsequent logic circuit from malfunctioning.
[0034]
In the clock generation circuit 10, if the selector circuit 15 directly switches the connection to the output 15D from the input 1 to the input 2, as shown in FIG. 4A, the PLL clock 1b (input 1) and the input clock If the phase is shifted from 1a (input 2), a very short pulse is output as the output clock 1g to the output 15D, and the subsequent logic circuit 16 may malfunction.
[0035]
On the other hand, in this embodiment, by providing the input 3 in the selector circuit 15 and passing the input 3 when switching between the input 1 and the input 2, as shown in FIG. By interposing an output period of a fixed value 0 between the clock output period and the clock output period, generation of an extremely short pulse as shown in FIG. 4A can be prevented, and the above-described malfunction is prevented. However, if the phase of the PLL clock 1b to the input 1 and the phase of the input clock 1a to the input 2 are sufficiently coincident and no malfunction occurs even if the input 1 and the input 2 are switched directly, There is no need to switch via.
[0036]
Next, the selector control circuit 14 will be described. The selector control circuit 14 outputs a select signal 1f for controlling the selector circuit 15, and includes a state machine 141 and a combination circuit 142. The selector control circuit 14 has a condition input 1 and a condition input 2. The condition input 1 receives an unlock signal 1c from the lock detection circuit 12, and the condition input 2 receives an underflow signal from the counter circuit 13. 1d is input. The input clock 1a is input to the clock input 14A of the selector control circuit 14. The state machine 141 receives the unlock signal 1c from the condition input 1, the underflow signal 1d from the condition input 2, and the input clock 1a from the clock input 14A. The unlock signal 1c is input from the condition input 1 to the combination circuit 142, and the state machine output 1e as a state signal is input from the state machine 141.
[0037]
FIG. 3 shows a state transition diagram of the state machine 141, and FIG. 5 shows a truth table of the combinational circuit 142.
[0038]
As shown in FIG. 3, during a lock state in which the unlock signal 1c is non-active '0' and the PLL circuit 11 operates stably, the state machine 141 is in state 0. Therefore, the value of the state machine output 1e is "00". Therefore, from the truth table shown in FIG. 5, the value of the select signal 1f output from the combination circuit 142 to the select output 14B is also "00". Thereby, the selector circuit 15 selects the input 1 according to the truth table shown in FIG. 6, and outputs the PLL clock 1b to the output 15D. This corresponds to a state before time A in the timing chart of FIG.
[0039]
Next, assuming that the unlock signal 1c changes from non-active to active at time A shown in FIG. 2, the combination circuit 142 immediately changes the value of the select signal 1f to "01". As a result, the selector circuit 15 selects the input 3 and the output clock 1g output from the output 15D has the fixed value '0', so that the clock supply to the subsequent logic circuit 16 is stopped. This corresponds to the states of the arrows indicated by reference numerals 202 and 203 in FIG.
[0040]
The state machine 141 is of a synchronous type, and the input clock 1a is input as an operation clock from the clock input 14A. Therefore, at time A, when the unlock signal 1c changes from non-active to active, the state remains at 0. ing. However, at the next rising edge of the input clock 1a (time B), the state machine 141 shifts to state 1. In this state 1, the value of the output 1e of the state machine 141 is "01" as shown by the arrow 201 in FIG. 2, but the value of the select signal 1f is "01" as shown in the truth table of FIG. "And has not changed from the state at time A.
[0041]
At the rise of the input clock 1a at time B in FIG. 2, the state machine 141 shifts to state 1 and, at the same time, the counter circuit 13 starts operating as shown by the arrow 200. Then, at time C in FIG. 2 where the count value of the counter circuit 13 is decremented to 0, the unlock signal 1c is active, and as shown by the arrow 210, the underflow signal 1d becomes active.
[0042]
Since the unlock signal 1c is active at time C in FIG. 2, the state machine 141 shifts to state 2 at the next rising edge of the input clock 1a (that is, time D). The value of the machine output 1e is "11". Further, as indicated by the arrow 212, the value of the select signal 1f also becomes “11”. Thus, the selector circuit 15 selects the input 2 as an alternative, and outputs the input clock 1a as the output clock 1g from the output 15D (see the arrow 213 in FIG. 2).
[0043]
As described above, in this embodiment, the state of unlocking (unlocking) of the PLL circuit 11 is longer than a predetermined period (a period until the count value of the counter circuit 13 is decremented from the initial value F to 0). Only when the period is over or when the locked state cannot be restored, the operation of switching the output clock 1g of the clock generation circuit 10 from the PLL clock 1b to the input clock 1a via the logical value “0” of the input 3 is performed.
[0044]
Therefore, in the present embodiment, for example, when the unlocked state (unlocked) of the PLL circuit 11 occurs for a short period shorter than a sudden predetermined period and returns, the selector circuit 15 outputs the output 15D. From the fixed value 0 to the PLL clock 1b without switching to the input clock 1a.
[0045]
As shown in FIG. 2, in this embodiment, the supply of the output clock 1g composed of the PLL clock 1b interrupted at the time A is started at the time D as the output clock 1g composed of the input clock 1a. Logic circuit 16 resumes operation. This input clock 1a has a lower frequency than the PLL clock 1b. Therefore, the operation speed of the logic circuit 16 to which the input clock 1a is input is lower than that of the case where the PLL clock 1b is input, but there is no risk of malfunction. As described above, it is a great merit to be able to execute appropriate emergency processing when the PLL circuit 11 is out of lock.
[0046]
Next, at time E in FIG. 2, when the PLL circuit 11 is again in the locked state and the unlock signal 1c becomes non-active, the state machine is activated at the next rising edge of the input clock 1a (time F). 141 shifts to state 3, and the value of the select signal 1f becomes "10" as indicated by the arrow 222. As a result, the selector circuit 15 selects the input 3 alternatively and outputs a fixed value 0 from the output 15D (see the arrow 223 in FIG. 2).
[0047]
Further, at time G in FIG. 2, at the next rising edge of the input clock 1a, the state machine 141 unconditionally shifts to state 0, and the value of the select signal 1f becomes "00" as shown by the arrow 230. The selector circuit 15 selects the input 1 alternatively. Thus, the output clock 1g output from the output 15D by the selector circuit 15 becomes the PLL clock 1b again (see the arrow 231 in FIG. 2).
[0048]
As described above, in this embodiment, when the PLL circuit 11 leaves the unlocked state (unlocked) and shifts to the locked state, and when the output clock 1g returns from the input clock 1a to the PLL clock 1b, the input clock 1a The output clock 1g is stopped for one cycle (the period from time F to time G in FIG. 2). Thus, when the output clock 1g returns from the input clock 1a to the PLL clock 1b, by providing a period in which the output clock 1g is stopped, a pulse that is much shorter than the PLL clock 1b is generated, for example. Therefore, a malfunction of the logic circuit 16 at the subsequent stage can be prevented, and a stable operation of the logic circuit 16 can be guaranteed.
[0049]
As described above, according to the clock generation circuit 10 of the present embodiment, even if the PLL circuit 11 is unlocked and becomes unlocked, the output clock 1g is switched from the output clock 1g to the logic circuit via a predetermined clock suspension period. Since the input clock 1a is supplied to the logic circuit 16, the logic circuit 16 at the subsequent stage does not remain stopped.
[0050]
In the above embodiment, the counter circuit 13 is constituted by a down counter and an underflow signal is output as a detection signal. However, when the counter circuit is constituted by an up counter and the count value of the up counter is incremented to a predetermined value. Alternatively, if the unlock signal 1c is active, an overflow signal as a detection signal may be activated.
[0051]
【The invention's effect】
As is clear from the above, according to the clock generation circuit of the present invention, when the period during which the PLL circuit is in the unlocked state exceeds a predetermined value, a conventional spare oscillator is used instead of the PLL clock. In addition, since the input clock to the PLL circuit is output, it is not necessary to add a circuit for oscillating a spare oscillator. Further, if the period during which the PLL circuit is in the unlocked state does not exceed a predetermined value, switching from the PLL clock to the input clock is not performed, so that frequent clock switching as in the related art can be avoided. In addition, the operation of the subsequent circuit will not be unstable.
[0052]
Therefore, according to the present invention, it is possible to avoid stopping the clock output beyond a predetermined period without adding a circuit for oscillating a spare oscillator, and to prevent the PLL circuit from being unlocked within the predetermined period even if the PLL circuit is unlocked. In the case of returning to the locked state in a short period of time, the clock is not switched, so that the subsequent circuit can be operated normally.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of a clock generation circuit of the present invention.
FIG. 2 is a timing chart for explaining the operation of the clock generation circuit of the embodiment.
FIG. 3 is a state transition diagram for explaining the operation of the selector control circuit of the embodiment.
FIG. 4A is a timing chart showing that when the input 3 is not provided to the selector circuit 15 in the clock generation circuit 10 of FIG. 1, a very short pulse is generated in the output clock 1g. 4B is a timing chart showing that when the input 3 is provided to the selector circuit 15 in the clock generation circuit 10 of FIG. 1, a very short pulse is not generated in the output clock 1g.
FIG. 5 is a truth table for explaining the operation of the selector control circuit 14 of FIG. 1;
FIG. 6 is a truth table for explaining the operation of the selector circuit 15 of FIG. 1;
[Explanation of symbols]
Reference Signs List 10 clock generation circuit 11 PLL circuit 12 lock detection circuit 13 counter circuit 14 selector control circuit 141 state machine 142 combination circuit 15 selector circuit 16 logic circuit 1a input clock 1b PLL clock 1c unlock signal 1d underflow signal 1e state machine output 1f select Signal 1g Output clock 1h 13 Count value of counter circuit A Time when unlock signal 1c changes from '0' to '1' Time B Time at which counter circuit 13 starts down-counting C Underflow signal 1d changes from '0' The time D when the output of the select circuit 15 is switched to the input clock 1a. The time E when the unlock signal 1c changes from "1" to "0". The output of the select circuit 15 is input 3 = '. Time G when it is switched to 0 ' Time that has been switched to the power 1 = PLL clock 1b

Claims (6)

A PLL circuit;
A selector that receives at least an input clock input to the PLL circuit and a PLL clock output from the PLL circuit, and selects and outputs one signal from a plurality of signals including the input clock and the PLL clock. Circuit and
A lock detection circuit that detects whether the PLL circuit is in an unlocked state and outputs an unlock signal indicating whether the PLL circuit is in an unlocked state;
The unlock signal is input from the lock detection circuit, a period during which the unlock signal indicates the unlock state is counted, and a detection signal indicating whether the counted value has reached a predetermined value is output. A counter circuit to
The detection signal is input from the counter circuit, and the unlock signal is input from the lock detection circuit, and the selector circuit is controlled based on a value of the detection signal and a value of the unlock signal. A selector control circuit that outputs the select signal of
The selector circuit is controlled by a select signal from the selector control circuit, and outputs the input clock in place of the PLL clock when a period during which the PLL circuit is in an unlocked state exceeds a predetermined value. A clock generation circuit characterized by the above-mentioned. 2. The clock generation circuit according to claim 1,
The selector circuit receives a fixed logical value in addition to the input clock and the PLL clock, and selects a period for selecting and outputting the PLL clock and a period for selecting and outputting the input clock. A clock generation circuit which selects and outputs the fixed logical value during a period between the clocks. 2. The clock generation circuit according to claim 1,
A clock generation circuit, wherein an operation clock input to the counter circuit is an input clock input to the PLL circuit. 2. The clock generation circuit according to claim 1,
The clock generation circuit according to claim 1, wherein the selector control circuit has a state machine that outputs a state signal based on the detection signal and the unlock signal, and generates the select signal based on the state signal. circuit. The clock generation circuit according to claim 4,
A clock generation circuit, wherein an operation clock input to the state machine is an input clock input to the PLL circuit. A clock generation circuit according to claim 1 and a logic circuit,
An integrated circuit, wherein an output clock output from the clock generation circuit is an operation clock input to the logic circuit.

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