JP2008099097A - Clock phase shift apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To hardly cause PLL (Phase Locked Loop) lock failure in a clock phase shifting apparatus which shifts the phase of a clock by using a PLL circuit. <P>SOLUTION: The clock phase shifting apparatus is provided with: a first-stage PLL circuit 201 which inputs an output clock C100 of a crystal oscillator 100; and a second-stage PLL circuit 202 which inputs an output clock C201 of the first-stage PLL circuit. Wherein an output clock C202 of the second-stage PLL circuit is inputted to the first-stage PLL circuit as an input clock to be compared with the output clock of the crystal oscillator, and the output clock C202 of the second-stage PLL circuit is extracted as an output clock to the outside. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a clock phase shift device that shifts the phase of a clock by using a plurality of PLL (Phase Locked Loop) circuits. For example, the PLL is used to satisfy the access timing specifications for a device such as a clock synchronous memory. In a device that needs to shift the phase of the clock using a circuit, when you want to make it difficult for PLL lockout to occur, or to output a reset signal for the required period without operating the entire system until it is locked, etc. The present invention relates to a clock phase shift device that is convenient to apply.

Various systems have been devised for clock phase shift using a conventional PLL circuit. For example, there is a system using two PLL circuits as disclosed in Japanese Patent Laid-Open No. 10-56382 (Patent Document 1).
The method described in Japanese Patent Laid-Open No. 10-56382 is shown in FIG. As shown in FIG. 7, in this method, the second PLL circuit is similarly used immediately after the first PLL circuit is used in a usage method in which the clock obtained by feeding back the usual PLL circuit is inserted into the first PLL circuit. A system is adopted in which the fed back clock is inserted into the second PLL circuit.
This method has an advantage that a stable frequency characteristic can be obtained even when the voltage drops. However, no countermeasure is taken against the ease of occurrence of PLL lock-off, and each PLL circuit having a feedback loop is provided. By using two, there are two feedback loops, and there are two places where there is a possibility of the PLL lock being released, and the likelihood of the PLL lock being released has doubled.

Also, various systems have been devised for the circuit for extending the reset period. For example, there exists a thing of Unexamined-Japanese-Patent No. 5-88785 (patent document 2).
The method described in Japanese Patent Laid-Open No. 5-88785 is shown in FIG. As shown in FIG. 8, this method is a method in which the reset signal generator, the pulse width compensator, and the circuit are separated. This method is not a realistic method because the operation when the clock is not stable is uncertain and the point of what the pulse width compensator is reset is not taken into consideration.

Japanese Patent Laid-Open No. 10-56382 (page 8, FIG. 1) Japanese Patent Laid-Open No. 5-88785 (page 5, FIG. 1)

In a conventional clock phase shifter using a PLL circuit, as countermeasures against the ease of occurrence of PLL lock loss, only the performance of the PLL circuit itself is relied on, and it is particularly considered that the PLL lock loss is less likely to occur. Was not.
For example, in a device or system using a high-speed clock exceeding 100 MHz, for example, when the output voltage fluctuates due to jitter fluctuation or power supply noise of the crystal oscillator output clock, the PLL circuit uses the output clock as the reference frequency on the input side. Since the phase control is performed by feedback, the PLL lock may be lost due to the jitter fluctuation or the power supply noise. If the PLL lock is lost, the PLL output clock frequency is transient. May cause errors such as parity errors when accessing the clock-synchronized memory or other devices using the PLL output clock or accessing the system, so use the PLL circuit to shift the phase of the clock. PLL lock out occurs in clock phase shift device It preferred to Nikuku.

  In addition, in the conventional reset extension circuit that extends the reset period, it is considered that the operation in the period where the clock is not stable is uncertain or how the reset extension circuit itself is reset. Therefore, it is preferable to issue an appropriate reset signal so that the system does not start to operate until the lock is completed.

  The present invention has been made in view of the above-described circumstances. In a clock phase shift device that shifts the phase of a clock using a PLL circuit, it is difficult to cause a PLL lock out and the lock is completed. In the meantime, an object of the present invention is to enable a reset signal to be issued to the entire system for a necessary period so that the system using the PLL output clock does not start to operate.

  A clock phase shift device according to the present invention includes a first-stage PLL circuit that inputs an output clock of a crystal oscillator, and a second-stage PLL circuit that inputs an output clock of the first-stage PLL circuit. The output clock of the two-stage PLL circuit is input to the first-stage PLL circuit as an input clock for comparison with the output clock of the crystal oscillator, and the output clock of the second-stage PLL circuit is taken out as an output clock to the outside. It is what

  The present invention includes a first-stage PLL circuit that inputs an output clock of a crystal oscillator, and a second-stage PLL circuit that inputs an output clock of the first-stage PLL circuit. The second-stage PLL circuit includes: The output clock is input to the first stage PLL circuit as an input clock for comparison with the output clock of the crystal oscillator, and the output clock of the second stage PLL circuit is taken out as an output clock to the outside. In the clock phase shift apparatus that uses and shifts the phase of the clock, there is an effect that it is difficult to cause the PLL lock out.

Embodiment 1 FIG.
Hereinafter, Embodiment 1 of the present invention will be described with reference to FIG. 1 which is a block diagram showing an example of a clock phase shift apparatus using a plurality of PLL circuits.

In describing Embodiment 1 of the present invention with reference to FIG. 1, first, a conventional general clock phase shift device will be described with reference to FIG.
In FIG. 9, a clock generated from the crystal oscillator 100 is input to an FPGA (Field Programmable Gate Array) 200 including a PLL circuit 201 and a flip-flop circuit 203, and the clock and flip-flop output from the PLL circuit 201 are input. Other signals (address signal / data signal / control signal, etc.) output from the circuit 203 are input to the device 300 such as a clock synchronous memory. The FPGA 200 accesses the device 300. However, if the timing specification for accessing the device 300 cannot be satisfied when the FPGA 200 is normally used, the clock phase needs to be shifted.

  As is well known, the FPGA is a device that can rewrite the logic function desired by the user any number of times. The FPGA is composed of CLBs (Configurable Logic Blocks) arranged in a grid on the FPGA, and each CLB is between CLBs. Each CLB is configured by a function generator and a flip-flop capable of generating an arbitrary logical function.

  Next, the operation of the conventional general clock phase shifter shown in FIG. 9 will be described in the case where the clock phase needs to be shifted.

  The FPGA 200 uses the clock C100 input from the crystal oscillator 100 to output an output O203 such as an address signal / data signal from the flip-flop circuit 203, while changing the phase of the output clock O200 of the FPGA 200 to the output clock C100 of the crystal oscillator 100. The output clock C100 of the crystal oscillator 100 is input to the PLL circuit 201.

The PLL circuit 201 outputs the input clock C100 with a slight delay inside the PLL circuit 201.
The clock C201 output from the PLL circuit 201 is output from the FPGA 200 and input to the device 300 such as a clock synchronous memory, for example, and fed back to the PLL circuit 201.

  The PLL circuit 201 compares the clock C100 input from the crystal oscillator 100 with the clock C201 input after feedback. Naturally, immediately after the clock starts to be input, the clock C100 input from the crystal oscillator 100 and the clock C201 input by feedback are out of phase, but the PLL circuit 201 receives the clock input from the crystal oscillator 100. The output clock C201 of the PLL circuit 201 is adjusted by adjusting the output clock C201 of the PLL circuit 201 so as to eliminate the phase shift between the clock C201 fed back and the clock C201 fed back, and the clock C201 fed back from the crystal oscillator 100 and the clock C100 inputted from the crystal oscillator 100. Make the phase the same.

  This adjustment is generally referred to as “shifting the clock phase”, and the state in which this adjustment has been successful is generally referred to as “PLL locked”, while the state in which the adjustment has failed is generally referred to as “PLL locked out”. "

  Note that the time from when the clock is input until the PLL is locked is, for example, several cycles at the clock frequency.

  Next, based on the conventional general clock phase shift device shown in FIG. 9, the example of the clock phase shift device according to the first embodiment of the present invention will be described with reference to FIG. In FIG. 1, the same reference numerals as those in FIG.

  In FIG. 1, a clock C100 generated from the crystal oscillator 100 is input to an FPGA 200 including a first-stage PLL circuit A201, a second-stage PLL circuit B202, a flip-flop circuit 203, and a buffer 204. The clock C204 output from the F and the other signals (address signal / data signal / control signal, etc.) O203 output from the flip-flop circuit 203 are input to the device 300 such as a clock synchronous memory.

  The FPGA 200 accesses the clock synchronous memory 300. However, if the timing specifications for accessing the device 300 cannot be satisfied when the FPGA 200 is normally used, the phase of the clock C204 needs to be shifted.

  Next, the operation of the first embodiment illustrated in FIG. 1 will be described in the case where the clock phase needs to be shifted.

  The FPGA 200 inputs a clock to the PLL circuit A201 in order to shift the clock phase of the clock C100 input from the crystal oscillator 100.

  The first-stage PLL circuit A201 outputs the clock C100 input from the crystal oscillator 100 with an output C201 with some delay inside the first-stage PLL circuit A201.

  The clock C201 output from the first-stage PLL circuit A201 is input to the flip-flop circuit 203, and an output C203 such as an address signal / data signal is output from the FPGA 200, while being input to the second-stage PLL circuit B202. The

  The second-stage PLL circuit B202 outputs the input clock C201 with some delay inside the second-stage PLL circuit B202.

  The clock C202 output from the second-stage PLL circuit B202 is input to the buffer 204, fed back, and input to the first-stage PLL circuit A201.

  The clock C204 output from the buffer 204 is output from the FPGA 200 and input to the device 300 such as a clock synchronous memory, and is fed back and input to the second-stage PLL circuit B202.

  The first-stage PLL circuit A201 compares the clock C100 input from the crystal oscillator 100 with the clock C202 input by feedback from the second-stage PLL circuit B202.

Immediately after the clock C100 starts to be input to the first-stage PLL circuit A201, the phase of the clock C100 input from the crystal oscillator 100 and the clock C202 input by feedback from the second-stage PLL circuit B202 is naturally shifted. However, the first-stage PLL circuit A201 is
The output clock C201 of the first-stage PLL circuit A201 is adjusted so as to eliminate the phase shift between the clock C100 input from the crystal oscillator 100 and the clock C202 fed back from the second-stage PLL circuit B202. The clock C202 fed back from the second-stage PLL circuit B202 and the clock C100 inputted from the crystal oscillator 100 have the same phase.

  The second-stage PLL circuit B202 compares the clock C201 input from the first-stage PLL circuit A201 with the clock C204 input by feedback from the buffer 204.

  In the second-stage PLL circuit B202, immediately after the clock starts to be input, the phase of the clock C201 input from the first-stage PLL circuit 201 and the clock C204 input by feedback from the buffer 204 is naturally shifted. However, the second-stage PLL circuit B202 has a second-stage PLL circuit B202 so as to eliminate a phase shift between the clock C201 input from the first-stage PLL circuit A201 and the clock C204 input by feedback from the buffer 204. The output clock C202 of the PLL circuit B202 is adjusted so that the clock C204 fed back from the buffer 204 and the clock C201 inputted from the first stage PLL circuit A201 have the same phase. In the first embodiment, the clock phase is shifted by the above method.

  In the clock phase shift device illustrated in the first embodiment, the clock phase is shifted over two PLL circuits (the first-stage PLL circuit 201 and the second-stage PLL circuit B202), so that the clock phase shifts. There were two locations where adjustment for shifting could be performed.

  Since the number of places where the adjustment for the phase shift of the clock can be performed is two, the above-described ease of occurrence of the PLL lock-off is two minutes that of the conventional clock phase shift device shown in FIG. It is 1.

  Further, the time required for the above-described PLL lock is, for example, when the time in each of the first-stage PLL circuit A201 and the second-stage PLL circuit B202 is 3 cycles in clock frequency. In the first mode, there are 6 cycles (3 cycles + 3 cycles). However, in the conventional clock phase shift device shown in FIG. 7, the PLL of the first phase comparator (PLL circuit) having the feedback circuit is locked. Since the uncertain output in the absence state is taken into the second phase comparator (PLL circuit) having a feedback circuit, the time until the final output is PLL-locked exceeds 6 cycles and is completely PLL-locked It takes time to do. In other words, at the time when 6 cycles have elapsed, in the conventional clock phase shift device shown in FIG. 7, the PLL lock is released, but in the first embodiment of the present invention, the PLL lock is surely achieved. .

In the first embodiment described above, there is no description about lowering the clock frequency by frequency division. However, there are various cases where the clock frequency used by the device or system is lower or higher than the oscillation frequency of the crystal oscillator. In any case, the above-described first embodiment can be applied.
The output clock C204 is shifted by a predetermined phase from the output clock C100 of the crystal oscillator, but the shift amount may be adjustable so that it can be adjusted as necessary.

Embodiment 2. FIG.
A second embodiment of the present invention will be described below with reference to FIG. 2 showing an example of a clock phase shift device using a plurality of PLL circuits and having a reset signal generation circuit.

  In FIG. 2, a clock C100 generated from the crystal oscillator 100 is input to an FPGA 200 including a first-stage PLL circuit A201, a second-stage PLL circuit B202, a flip-flop circuit 203, and a buffer 204. An output clock C204 and other signals (address signal / data signal / control signal, etc.) O203 are input to a device 300 such as a clock synchronous memory.

  The first-stage PLL circuit A 201 determines its own PLL lock failure and outputs a PLL lock failure notification signal 205 for notifying the PLL lock failure.

  The second-stage PLL circuit B 202 determines whether it is out of its own PLL lock, and outputs a PLL lock out notification signal 206 for notifying the PLL lock out.

  The FPGA 200 outputs a reset signal 207 that resets (initializes) a system (not shown) that uses the clock C204 output from the FPGA 200 and other signals (address signal / data signal / control signal, etc.) O203. This reset signal 207 includes at least one of the PLL unlock notification signal 205 and the PLL unlock notification signal 206 from a logic element 207 such as an OR logic element that inputs the PLL unlock notification signal 205 and the PLL unlock notification signal 206. Output when output.

  The FPGA 200 accesses the device 300. However, if the timing specification for accessing the device 300 cannot be satisfied when the FPGA 200 is normally used, the clock phase needs to be shifted.

  Next, the operation of the second embodiment will be described. In the first and second embodiments, there is an advantage that once the lock is first made, it is difficult for the lock to be released, but the first lock is difficult to perform. Since normal operation cannot be expected until the first lock, the reset is performed so that the FPGA 200 does not access the device 300 such as a clock synchronous memory.

  The PLL unlock notification signal 205 output from the first-stage PLL circuit A 201 becomes significant when unlock occurs, but is also significant before locking. Similarly, the PLL unlock signal 206 output from the second-stage PLL circuit B 202 is significant when unlock occurs, but is significant before locking.

  A signal obtained by taking the logical sum of these unlock signals 205 and 206 by the logic element 207 is used as a reset signal O207 output from the FPGA 200, and the entire system and the FPGA 200 itself are reset. As a result, it is possible to prevent the FPGA 200 from accessing the device 300 before entering the locked state, and malfunctioning of the FPGA 200 and the entire system.

Embodiment 3 FIG.
The third embodiment of the present invention will be described below with reference to FIGS. 10, 3, and 4. FIG. FIG. 10 is a block diagram showing a circuit configuration for resetting a conventional FPGA internal circuit, FIG. 3 is a block diagram showing an example of a circuit configuration for resetting an internal circuit of an FPGA having a plurality of PLL circuits, and FIG. 4 is a block diagram in FIG. It is a figure which compares each part operation example with each part operation | movement in FIG. 10, and shows with a time chart.

  10 and 3, the clock C100 generated from the crystal oscillator 100 is input to the clock loss detection circuit 400 and the FPGA 200 including the internal circuit 208.

  The clock loss detection circuit 400 outputs a clock loss signal O400 that becomes significant after a while after the input clock C100 is not supplied and becomes insignificant while the clock is supplied.

  A reset signal 500 is input to and output from the FPGA 200. The generation factor of the reset signal 500 is an automatic reset due to a power supply drop or an artificial depression of a reset button provided in the system. FIG. 10 shows a conventional method. FIG. 3 shows a system according to the third embodiment.

First, the operation of the conventional method will be described with reference to FIG.
Unless it is a special case, the power supply, the clock C100, the clock loss signal O400, and the reset signal 500 become significant in order from the top shown in FIG.
In other words, when the power is turned on, the power itself begins to be supplied slowly and eventually is supplied completely.
The crystal oscillator 100 starts generating the clock C100 only after the power supply is completely received. The operation is uncertain immediately after the power supply is started. Specifically, the indefinite state is a state where the potential is intermediate between high and low, or a clock that is not originally a frequency to be generated by the crystal oscillator 100 is output.
The clock loss detection circuit 400 outputs a significant signal as the clock loss signal O400 as shown in the figure when the clock C100 is not generated even when power is supplied. That is, as shown, the clock loss signal is low significant. Therefore, this “clock loss signal O400 significant” is a signal indicating that the clock C100 is not generated.
Even if the clock C100 is indeterminate, if the clock signal C100 is detected to change to high, or if a clock with a different frequency is detected, the clock loss signal O400 will be involuntarily shown. And change. Therefore, this “clock loss signal O400 involuntary” is a signal indicating that the clock C100 is generated.
As shown in the figure, the reset signal 500 changes from significant to involuntary after a while after the clock C100 is completely supplied. The reset signal 500 is low significant. This “reset signal 500 significant” means a reset of the internal circuit 208 inside the FPGA 200, that is, an initialization state and a standby state. The output O208 of the internal circuit 208 of the FPGA 200 (the output O203 of the flip-flop circuit 203 in FIG. ) Is not output.
In the conventional system and system shown in FIG. 10, the reset signal 500 resets the internal circuit 208 in the FPGA 200. Therefore, even if the normal clock C100 is supplied, the internal circuit 208 is used until the reset signal 500 becomes involuntary. Could not work. Devices and systems that use the output of the FPGA 200 could not operate.

Next, the operation of the third embodiment will be described with reference to FIG.
Unless it is a special case, the power supply, the clock C100, the clock loss signal O400, and the reset signal 500 become significant in order from the top shown in FIG.
In other words, when the power is turned on, the power itself begins to be supplied slowly and eventually is supplied completely.
The crystal oscillator 100 starts generating the clock C100 only after the power supply is completely received. The operation is uncertain immediately after the power supply is started. Specifically, the indefinite state is a state where the potential is intermediate between high and low, or a clock that is not originally a frequency to be generated by the crystal oscillator 100 is output.
The clock loss detection circuit 400 outputs a significant signal as the clock loss signal O400 as shown in the figure when the clock C100 is not generated even when power is supplied. That is, as shown, the clock loss signal is low significant. Therefore, this “clock loss signal O400 significant” is a signal indicating that the clock C100 is not generated.
Even if the clock C100 is indeterminate, if the clock signal C100 is detected to change to high, or if a clock with a different frequency is detected, the clock loss signal O400 will be involuntarily shown. And change. Therefore, this “clock loss signal O400 involuntary” is a signal indicating that the clock C100 is generated.
As shown in the figure, the reset signal 500 changes from significant to involuntary after a while after the clock C100 is completely supplied. The reset signal 500 is low significant. This “reset signal 500 significant” means a reset of the internal circuit 208 inside the FPGA 200, that is, an initialization state and a standby state. The output O208 of the internal circuit 208 of the FPGA 200 (the output O203 of the flip-flop circuit 203 in FIG. ) Is not output.
In the system and system of the third embodiment illustrated in FIG. 3, the reset signal 500 is not used for resetting the internal circuit 208 of the FPGA 200 as shown in FIG. It may be used for resetting in the FPGA 200 other than the above, or may be output from the FPGA 200 as it is and used for resetting the entire system as necessary.
It is the clock loss signal O400 that is the output of the clock loss detection circuit 400 that resets the internal circuit 208 of the FPGA 200. Therefore, the time when the internal circuit 208 can produce a significant output signal is much earlier than the conventional method and system shown in FIG. 10, as shown in FIG. The operation start time of the device and system using the output O208 of the internal circuit 208 of the FPGA 200 is much earlier than that of the conventional method and system shown in FIG.

Embodiment 4 FIG.
Embodiment 4 of the present invention will be described below with reference to FIG. 5 which is a block diagram showing an example of a specific configuration of a reset generation circuit for generating a reset signal in an FPGA.

In FIG. 5, the clock C100 generated from the crystal oscillator 100 is input to the FPGA 200 including the clock loss detection circuit 400 and the reset generation circuit 211.
The clock loss detection circuit 400 outputs a clock loss signal O400 that becomes significant a while after the input clock is not supplied and becomes insignificant while the clock is supplied.
The reset signal 500 is input to the reset generation circuit 211 in the FPGA 200 and the FPGA 200 itself. The generation factor of the reset signal 500 is a reset due to a power supply drop or an artificial press of a reset button provided in the system.
The reset generation circuit 211 further includes a counter 212, a reset detection circuit 214, and a logic element 216 such as an OR logic element.
The counter 212 outputs a signal 213 indicating that the count has expired.
The reset detection circuit 214 is a circuit that detects that the input reset signal 500 has changed from involuntary to significant. When this is detected, the reset detection signal 215 becomes significant and is output to the counter 212.
The counter 212 is reset when the clock loss signal O400 becomes insignificant or the reset detection signal 215 becomes significant, and starts counting the number of clocks input. When the count reaches the count expiration value, the count expiration signal 213 is reached. Is output.
The reset generation circuit 211 outputs the logical sum of the reset signal 500 and the count expiration signal 213 by the logic element 216 from the FPGA 200 to the outside as the reset output O216.

Next, the operation of the fourth embodiment will be described.
The reset generation circuit 211 starts operation at the same time as the clock loss signal O400 becomes unintentional. Here, the count expiration value of the counter 212 is set to be larger than the actually required count value because the period during which the counter 212 operates includes the first clock uncertain period. The reset generation circuit 211 can reliably generate a reset signal having a length necessary for the system even when the power is turned on or other reset factors by setting the sum of the count expiration signal 213 and the reset signal 500 as the reset output O216. .

Embodiment 5 FIG.
Hereinafter, Embodiment 5 of the present invention will be described with reference to FIG. 6, which is a block diagram showing an example of a connection circuit configuration of a plurality of PLL circuits in an FPGA and a reset generation circuit that operates depending on the output of the PLL circuit. explain.

In FIG. 6, a clock C100 generated by the crystal oscillator 100 is input to the FPGA 200 and the clock loss detection circuit 400.
The clock loss detection circuit 400 outputs a clock loss signal O400 that becomes significant a while after the input clock is not supplied and becomes insignificant while the clock is supplied.
The FPGA 200 includes a first-stage PLL circuit A 201, a second-stage PLL circuit B 202, a flip-flop circuit 203, a buffer 204, and a reset generation circuit 211.
A clock C204 output from the buffer 204 and other signals (address signal / data signal / control signal, etc.) O203 output from the flip-flop circuit 203 are input to a device 300 such as a clock synchronous memory.
The FPGA 200 accesses the device 300, but if the timing specifications for accessing the device 300 cannot be satisfied when the FPGA 200 is normally used, the clock phase needs to be shifted.
The first-stage PLL circuit A201 outputs a PLL unlock signal 205 indicating the PLL unlock of the first-stage PLL circuit A201, and the second-stage PLL circuit B202 releases the PLL lock of the second-stage PLL circuit B202. The PLL unlock signal 206 shown is output.
A signal obtained by logically summing the PLL unlock signal 205 and the PLL unlock signal 206 by a logic element 207 such as an OR logic element is O207, and further, the reset signal 500 and O207 are ORed by a logic element 217 to obtain a signal O217. Has been generated.
The signal O217 is input to the FPGA 200 as a reset signal.
Here, the cause of the generation of the reset signal 500 is a reset due to a power supply drop or an artificial depression of a reset button provided in the system.
The reset generation circuit 211 further includes a counter 212 and a reset detection circuit 214 inside.
The counter 212 outputs a signal 213 indicating that the count has expired.
The reset detection circuit 214 is a circuit that detects that the input reset signal O217 has changed from involuntary to significant. When this is detected, the reset detection signal 215 becomes significant and is output to the counter 212.
The counter 212 is reset when the clock loss signal O400 becomes insignificant or the reset detection signal 215 becomes significant, and starts counting the number of clocks input. When the count reaches the count expiration value, the count expiration signal 213 is reached. Is output.
The reset generation circuit 211 outputs the logical sum of the reset signal O217 and the count expiration signal 213 from the FPGA 200 to the entire system as the reset output O216 from the logic element 216.

Next, the operation of the fifth embodiment will be described when the clock phase needs to be shifted.
The FPGA 200 inputs a clock to the first-stage PLL circuit A201 in order to shift the phase of the clock C100 input from the crystal oscillator 100.
The first-stage PLL circuit A201 outputs an input clock C100 with some delay inside the first-stage PLL circuit A201. The output clock C201 is input to the flip-flop circuit 203 to output an address signal / data signal or the like from the FPGA 200, while being input to the second-stage PLL circuit B202.
The second-stage PLL circuit B202 outputs the input clock C201 as an output C202 with some delay inside the second-stage PLL circuit B202. The clock C202 output from the second-stage PLL circuit B202 is input to the buffer 204, fed back, and input to the first-stage PLL circuit A201.
The clock C204 output from the buffer 204 is output from the FPGA 200 and input to the device 300 such as a clock synchronous memory, and is fed back and input to the second-stage PLL circuit B.
The first-stage PLL circuit A201 compares the clock C100 input from the crystal oscillator 100 with the clock C202 input by feedback from the second-stage PLL circuit B202. Naturally, immediately after the clock C202 starts to be input, the clock C100 input from the crystal oscillator 100 and the clock C202 input by feedback from the PLL circuit B202 are out of phase, but the first-stage PLL circuit A201 has a crystal. The output clock C201 of the first-stage PLL circuit A201 is adjusted to eliminate the phase shift between the clock C100 input from the oscillator 100 and the clock C202 fed back and input from the second-stage PLL circuit B202. The clock C202 fed back from the two-stage PLL circuit B202 and the clock C100 inputted from the crystal oscillator 100 have the same phase.
The second-stage PLL circuit B202 compares the clock C201 input from the first-stage PLL circuit A201 with the clock C204 input by feedback from the buffer 204. Naturally, immediately after the clock C204 starts to be input, the clock C201 input from the first-stage PLL circuit 201 and the clock C204 input by feedback from the buffer 204 are out of phase, but the second-stage PLL circuit. B202 adjusts the output clock C202 of the second-stage PLL circuit B202 so as to eliminate the phase shift between the clock C201 input from the first-stage PLL circuit A201 and the clock C204 fed back from the buffer 204. Thus, the clock C204 fed back from the buffer 204 and the clock C201 input from the first-stage PLL circuit A201 have the same phase.
Although this method has an advantage that it is difficult to cause unlocking once it is first locked, it is difficult to perform the initial locking.
Since normal operation cannot be expected until the lock is made for the first time, a reset is performed so that the FPGA 200 does not access the device 300. A logical sum signal O217 of the signal 0207 obtained by taking the logical sum of the unlock signals 205 and 206 and the reset signal 500 from the outside is generated, and the FPGA 200 is reset as the reset signal.
As a result, it is possible to prevent the FPGA 200 from accessing the device 300 before entering the locked state, and malfunctioning of the FPGA 200 and the entire system.
On the other hand, there is a possibility that the reset signal O217 is a reset having a length shorter than the reset period required by the system. Therefore, the reset signal O217 is input to the reset generation circuit 211.
The reset generation circuit 211 starts operation at the same time as the clock loss signal O400 becomes unintentional. Here, the count expiration value of the counter 212 is set to be larger than the actually required count value because the period during which the counter 212 operates includes the first clock uncertain period. The reset generation circuit 211 uses the sum of the count expiration signal 213, which is the output of the counter 212, and the output O217 of the logic element 217 as a reset output O216, so that it is also necessary for the system when the power is turned on and other reset factors. A length reset signal can be reliably generated.

Embodiments 1 to 5 of the present invention are configured as described above and have the following characteristic points.
Feature 1: By using two PLL circuits that normally use only one PLL circuit for shifting the phase of the clock, and by incorporating two PLL circuits in one loop, unlike the conventional method, Since the number of adjustable locations is two in one loop, the ease of occurrence of PLL lock release is halved compared to the prior art, and PLL lock release is less likely to occur.
Feature 2: Incorporates a reset circuit that outputs a reset signal only for the period required for the entire system so that the system does not operate until locking is completed. This reset circuit outputs a reset even when the clock is unstable. By using a reset circuit that can be used, a reset signal can be output stably for a certain period until the lock is completed or even when the clock is unstable, so that the device can operate more stably.
Feature 3: Two PLL circuits are used, and the clock feedback is made to straddle the two PLL circuits, so that the PLL lock is less likely to occur. In addition, by providing a reset generation circuit in the FPGA and resetting the reset generation circuit with a clock loss signal, it is possible to reliably generate a reset not only when the PLL lock is released but also when the power is turned on.
Feature 1A: In a certain device, a PLL (Phase Locked Loop) circuit in a FPGA (Field Programmable Gate Array), which is a circuit for shifting the phase of the clock with respect to a clock generated by a crystal oscillator in the device, is provided. The two normally used ones are used so that the PLL lock is less likely to occur (Embodiments 1 to 5).
Feature point 2A: The feature point 1A method is less likely to cause a PLL lock release than a conventional method using a single PLL circuit, but it is also less likely to cause a PLL lock. An automatic reset circuit is provided in the FPGA (second embodiment).
Feature 3A: In a device to which a power supply and a reset signal are supplied, it is detected that a clock generated from a crystal oscillator in the device by the supplied power supply detects a stop before the reset is released when the power is turned on. By substituting the clock loss signal, which is a signal to be notified, for the reset signal, the FPGA in the device is initialized and a significant signal is created in the device (Third Embodiment).
Feature point 4A: In the feature point 3A, the reset signal supplied when the power is turned on is held in the apparatus, and the reset period can be extended as necessary (Embodiment 4).
Feature point 5A: In feature point 4A, the power supply is lowered or the reset button provided by the system is manually pressed, or the reset signal with a short period by the automatic reset circuit according to claim 2 is held in the apparatus to extend the reset period. (Embodiment 5).
Feature 1B1: A first-stage PLL circuit that inputs an output clock of the crystal oscillator and a second-stage PLL circuit that inputs an output clock of the first-stage PLL circuit are provided, and the second-stage PLL circuit includes: An output clock is input to the first stage PLL circuit as an input clock to be compared with an output clock of the crystal oscillator, and an output clock of the second stage PLL circuit is taken out as an output clock to the outside.
Feature point 1B2: In the feature point 1B1, the first-stage PLL circuit and the second-stage PLL circuit are provided in the FPGA, and the output of the buffer is sent to the second-stage PLL circuit in the first-stage PLL circuit. It is input as an input clock to be compared with an output clock of the circuit, and an output clock of the second stage PLL circuit is taken out as an output clock to the outside through a buffer in the FPGA.
Feature point 2B: In the feature point 1B1 or feature point 1B2, the FPGA is reset by at least one of the output clock of the first-stage PLL circuit and the output clock of the second-stage PLL circuit.
Feature point 3B: In the feature point 1B1 or the feature point 1B2, a significant signal is generated in the FPGA based on the clock loss signal for detecting the stop of the output clock of the crystal oscillator.
Feature point 4B: At the feature point 3B, a reset signal is generated based on the output of a counter that operates depending on the clock loss signal.
Feature point 5B: At feature point 1B1 or feature point 1B2, stop of at least one of the output clock of the first stage PLL circuit and the output clock of the second stage PLL circuit and the output clock of the crystal oscillator is detected. The reset signal is generated based on the output of the counter that operates depending on the clock loss signal.

  In addition, in each figure of FIGS. 1-10, the same code | symbol shows the same or equivalent part.

1 is a block diagram showing an example of a clock phase shift device using a plurality of PLL circuits, showing Embodiment 1 of the present invention. FIG. It is a figure which shows Embodiment 2 of this invention, and is a block diagram which shows the example of the clock phase shift apparatus which used the several PLL circuit and had the reset signal generation circuit. It is a figure which shows Embodiment 3 of this invention, and is a block diagram which shows the example of the circuit structure which resets the internal circuit of FPGA which has several PLL circuits. It is a figure which shows Embodiment 3 of this invention, and is a figure which compares each part operation example in FIG. 3, and each part operation | movement in FIG. 10 with a time chart. It is a figure which shows Embodiment 4 of this invention, and is a block diagram which shows the example of a concrete structure of the reset generation circuit which produces | generates a reset signal in FPGA. It is a figure which shows Embodiment 5 of this invention, and is a block diagram which shows the example of a connection circuit structure of the reset generation circuit which act | operates depending on the output of the several PLL circuit and the said PLL circuit in FPGA. It is a block diagram which shows the conventional clock phase shift apparatus (it describes in patent document 1) using a PLL circuit. FIG. 11 is a block diagram showing a conventional reset signal generation circuit (described in Patent Document 2). It is a block diagram which shows the connection circuit structure of clock synchronous memory which receives FPGA which is the application object of the conventional PLL circuit, and its output. It is.

Explanation of symbols

100 crystal oscillator,
200 FPGA,
201 PLL circuit of the first stage,
202 second stage PLL circuit,
203 flip-flop circuit,
204 buffers,
212 counter,
402 Clock loss detection circuit.

Claims (6)

  A first-stage PLL circuit for inputting an output clock of the crystal oscillator and a second-stage PLL circuit for inputting an output clock of the first-stage PLL circuit are provided, and the output clock of the second-stage PLL circuit is the above-mentioned A clock phase shift device that is inputted to the first stage PLL circuit as an input clock to be compared with the output clock of the crystal oscillator, and the output clock of the second stage PLL circuit is taken out as an output clock to the outside.   2. The clock phase shifter according to claim 1, wherein the first-stage PLL circuit and the second-stage PLL circuit are provided in an FPGA, and an output of the buffer is supplied to the second-stage PLL circuit. A clock that is input as an input clock to be compared with an output clock of a stage PLL circuit, and an output clock of the second stage PLL circuit is taken out as an output clock to the outside through a buffer in the FPGA Phase shift device.   3. The clock phase shifter according to claim 1, wherein the FPGA is reset by at least one of an output clock of the first-stage PLL circuit and an output clock of the second-stage PLL circuit. A clock phase shift device characterized by the above.   3. The clock phase shift device according to claim 1, wherein a significant signal is generated in the FPGA based on a clock loss signal for detecting a stop of an output clock of the crystal oscillator. Clock phase shift device.   5. The clock phase shift device according to claim 4, wherein the reset signal is generated based on an output of a counter that operates depending on a clock loss signal.   3. The clock phase shift apparatus according to claim 1, wherein at least one of an output clock of the first stage PLL circuit and an output clock of the second stage PLL circuit, and an output clock of the crystal oscillator. A clock phase shift device, wherein a reset signal is generated based on an output of a counter that operates in dependence on a clock loss signal that detects a stop of the clock.

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