JP2005039808A - Dll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a delay circuit does not necessarily be normally actuated in starting operation. <P>SOLUTION: The DLL circuit comprises a delay circuit 5 which outputs an output signal obtained by incurring time delay in an input signal corresponding to a control signal, an initialization circuit 6 which outputs an initialization input signal and an initialization output signal as initial values predetermined by an initialization signal, and passes through the input and output signals and output them when they are turned into a predetermined state after the initialization signal is canceled, a phase comparator circuit 7 which outputs a phase delay signal and a phase advance signal as the initial values predetermined by the initialization signal by the initial value of the delay circuit or the incorporated initialization circuit, and outputs the relationship of the input and output signals as the phase delay signal and the phase advance signal after the initialization signal is canceled, a charge pump circuit 8 and a low-pass filter circuit 9 for outputting a control signal as an initial value predetermined by the initialization signal and outputting the control signal according to the phase delay signal and the phase advance signal after the initialization signal is canceled. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a delay circuit, and more particularly to a DLL circuit.

  DLL (Delay Locked Loop) circuits are widely used in general digital electronic circuits. The DLL circuit outputs an output signal in which a time delay as a phase difference designed in advance with respect to an input signal is generated, and a control signal is output as an internal signal. The DLL circuit outputs a digital signal having an arbitrary phase difference with respect to the input signal, extracts an internal signal having an arbitrary phase between the input signal and the output signal from the delay circuit, and transfers the control signal to another delay circuit. By applying this, it is possible to control another input / output signal called a replica (replication) method, or to realize a delay circuit having different operation specifications.

  In order to perform such operations, DLL circuits are widely used in digital signal processing circuits. As a realization method, it is often manufactured by an LSI (Large Scale IC) circuit having features such as a small area and low power consumption.

  A configuration example of a conventional DLL circuit is shown in FIG. A delay circuit 1 for applying an input signal from the outside and outputting an output signal in which a time delay is generated according to a control signal to the applied input signal; and a phase relationship between the input signal and the output signal And a phase comparison circuit 2 for outputting as a phase advance signal, a charge pump circuit 3 for outputting the control signal in accordance with the phase delay signal and the phase advance signal, and an LPF (Low Pass Filter) circuit 4.

  Next, an example of normal operation of the DLL circuit will be described with reference to FIG. As an input signal to the DLL circuit, generally, a repetitive digital periodic waveform, for example, a clock signal frequently used in the digital circuit is applied to the delay circuit. The reason why the input signal in FIG. 5 is not a normal square wave in the initial stage is that, for example, a ring oscillation circuit frequently used as a clock generation circuit mounted on an LSI circuit is in the middle of starting immediately after the power to the LSI circuit is turned on. The state is shown. The applied input signal generates a time delay when passing through the delay circuit, and outputs it as an output signal from the delay circuit. The time delay of the delay circuit is controlled by a control signal that is an internal signal of the DLL circuit.

  The phase comparison circuit receives the input signal and output signal of the delay circuit. The phases of the applied input signal and output signal are compared, and if the output signal is relatively delayed from the input signal, the delayed signal is output for a longer time than the advanced signal. On the other hand, if the output signal is relatively advanced than the input signal, the advanced phase signal is output for a longer time than the delayed phase signal. In any case, the difference between the length of the delayed signal and the length of the advanced signal coincides with the phase difference between the input signal and the output signal. Therefore, if the phase of the input signal and the output signal completely match, the difference in length between the delayed signal and the advanced signal is zero.

  The charge pump circuit is applied with the late phase signal and the advanced phase signal of the phase comparison circuit. When the length of the phase advance signal is longer than the length of the slow phase signal, the control signal is lowered only during the difference in length. Conversely, when the length of the phase advance signal is shorter than the length of the slow phase signal, the control signal is raised by the difference in length. When the control signal decreases, the time delay generated by the delay circuit becomes larger. On the contrary, when the control signal rises, the time delay generated by the delay circuit becomes smaller. The above negative feedback control is repeated, and the operation is automatically performed so that the phase difference between the input signal and the output signal becomes zero.

  A more detailed configuration example of FIG. 1 is shown in FIGS. FIG. 2 is a detailed configuration example of the delay circuit. Pn type MOSFETs 11, 12,..., 1n are combined with Nch type MOSFETs 21, 22,. The input signal is first applied to the first stage inverter circuit composed of the Pch type MOSFET 11 and the Nch type MOSFET 21, which continues from the second stage and is cascade-connected to the nth stage. The output of the nth stage becomes the output signal of the delay circuit. In this configuration example, n must be an even number depending on the operation example of the phase comparison circuit. Separate Nch MOSFETs 31, 32,..., 3n are connected to the source side of the Nch MOSFET, and their gates are connected in common and a control signal is applied. If the control signal rises, the drain current increases in any of the Nch-type MOSFETs 31, 32,..., 3n, so that the operating current of each inverter circuit also increases and the delay time becomes short. On the other hand, if the control signal is lowered, the drain currents of all the Nch MOSFETs 31, 32,..., 3n are reduced, so that the operating current of each inverter circuit is also reduced and the delay time is lengthened.

  FIG. 3 is a detailed configuration example of the phase comparison circuit. When the phase of the comparison signal is delayed from the reference signal, the delayed signal is output for a longer time than the advanced signal in accordance with the phase angle. If the phase of the comparison signal is ahead of the reference signal, the reverse operation is performed. In the example of FIG. 2, the input signal is connected to the reference signal, and the output signal is connected to the comparison signal. This circuit is a circuit that has been widely used in the past in PLL (Phase Locked Loop) circuits and DLL circuits.

  FIG. 4 is a detailed configuration example of the charge pump circuit and the LPF circuit. The resistor 62 and the Nch type MOSFET 63 constitute a pseudo constant current circuit of (power supply voltage = VDD−threshold voltage of the Nch type MOSFET) / resistance value. The Nch-type MOSFET 63 forms an input side, and 64 and 69 form an output side. The constant current output generated by the Nch type MOSFET 64 is input to a current mirror circuit in which the Pch type MOSFET 65 is the input side and 66 is the output side. If the constant values of these circuits are appropriately designed, the constant current values output from the Nch type MOSFET 69 and the Pch type MOSFET 66 are the same. Using the Nch-type MOSFET 68 and the Pch-type MOSFET 67 as the switch means, respectively, when the leading phase signal and the retarding phase signal become the H value, they are outputted from the charge pump circuit.

Since the current output from the charge pump circuit is pulsed as shown in FIG. 5, it passes through a simple LPF circuit composed of a resistor 71 and a capacitor 72 and is output as a DC control signal, which is a delay circuit. Applied to
kyoon Jeong et al., "Design of PLL-Based Clock Genaration Ciruits", IEEE J. Solid-State Circ., vol. SC-22, pp. 255-261, April 1987 Young el al., "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors", IEEE J. Solid-State Circ., Vol. SC-27, pp. 1599-1607, Nov. 1992. F. Bitting, "A 30-128 MHz Frequency Synthesizer Standard Cell", Proc. CICC, pp. 24.1.1-24.1.6, May 1992. Mijuskovic, "Cell-Based Fully Integrated CMOS Frequency Synthesizers", IEEE J. Solid-State Circ., Vol. SC-29, pp. 271-279, March 1994 Novof et al., "Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and +/- 50ps Jitter", ISSCC Dig. Tech. Papers, pp. 112-113, Feb. 1995

  In the conventional DLL circuit, since the initial state in which the circuit operates is not necessarily uniquely specified, there is a problem that the control circuit diverges and the delay circuit does not operate normally. This operation state will be described with reference to FIG.

  An input signal is applied to a conventional delay circuit, for example, in an indefinite and unstable starting state immediately after power is applied to the entire circuit system. Then, in some cases, the output signal may become indefinite and unstable according to this. That is, these indefinite and unstable signals are applied to the conventional phase comparison circuit. Further, in the conventional phase comparison circuit, the initial startup state of the circuit is not necessarily specified uniquely, and the delayed phase signal and the advanced phase signal may be unstable and unstable. Originally, even if the input signal of the delay circuit is small, it must always generate a time delay and become an output signal, but it may be detected by mistake due to an indefinite and unstable state of the phase comparison circuit. There is a possibility that the processing result equivalent to the case where the phase of the output signal is advanced from the input signal from the start state of the circuit, that is, the phase advance signal is output for a longer time than the phase delay signal.

  In this case, the feedback control of the entire DLL circuit is configured as a positive feedback instead of a negative feedback which is the original operation principle. Therefore, the entire DLL circuit does not converge to a normal state, and the control signal rises or falls too much, and the entire circuit does not perform a normal operation. FIG. 6 shows the change to such a state.

  Furthermore, there is a cause of a state where normal operation is not performed. Even in the case where the delay circuit and the phase comparison circuit are not in the above-described erroneous state and become originally desirable values, the initial value of the control signal is not necessarily uniquely specified in principle. Then, even when the entire DLL circuit is designed with the output signal delayed by exactly one cycle from the input signal, the output signal from the input signal is just two cycles or just three cycles depending on the initial value of the control signal. There is a possibility that the feedback control of the entire DLL circuit is started as a state that is delayed by as much as possible. In this case, even when the feedback control is in the original negative feedback state, for example, assuming that the delay circuit has a characteristic of delaying the phase by exactly one cycle, the output terminal is shifted from a position shifted every ¼ cycle in the middle. Even if the signal is taken out, the output actually deviates every 2/4 period or deviates every 3/4 period, and the normal operation is not performed.

  Therefore, the present invention aims to solve such a conventional problem.

  In order to solve the above problems, an aspect of the present invention is a DLL circuit. This DLL circuit compares the phase of the input signal and the output signal, and outputs the phase difference of the delay circuit that outputs the output signal with a time delay to the input signal according to negative feedback control. An initialization circuit for setting an initial state of the circuit in at least one of a circuit, a circuit that performs negative feedback control so as to eliminate a phase difference, a delay circuit, a phase comparison circuit, and a circuit that performs negative feedback control; .

  The initialization circuit may set the output of the phase comparison circuit in a state where the phase of the input signal is relatively advanced from the phase of the output signal. Further, the delay time of the delay circuit may be set to a substantially minimum.

  There may be further provided a circuit for controlling the output signal to be input to the phase comparison circuit before the input signal.

  Another embodiment of the present invention is also a DLL circuit. The DLL circuit includes a delay circuit that is applied after an input signal is released after an initialization signal is released, and that outputs an output signal in which a time delay is generated in accordance with a control signal. An initialization output signal is output as a predetermined initial value by the initialization signal, and when the input signal and the output signal are in a predetermined state after the initialization signal is released, initialization is performed to pass through each of them. Circuit and an initial value of the delay circuit or a built-in initialization circuit outputs a delayed signal and a advanced signal as an initial value predetermined by the initialization signal, and the input signal after the initialization signal is released And a phase comparison circuit that outputs the phase relationship between the output signal as the delayed phase signal and the advanced phase signal, and the control signal has an initial value determined in advance by the initialization signal Output Te, and a charge pump circuit and a low-pass filter to output the control signal in accordance with the slow signal after cancellation of the initialization signal and the phase advance signal.

  In this DLL circuit, the circuit that initializes the operation sets the control signal so that the delay circuit has the minimum delay time, and the phase comparison circuit operates from the state in which the length of the advanced phase signal is output longer than the delayed phase signal. The initialization input signal and the initialization output signal are controlled so as to start and the initial state of the phase comparison circuit is set.

  The initial value of the initialization signal is the H value, and changes to the L value after the initialization state is canceled. The initial values of the initialization input signal and the initialization output signal are both L values, and the lag signal and the advance signal The initial value may be an L value, and the initial value of the control signal may be an H value.

  The delay circuit may output an output signal in which a time delay corresponding to the control signal is generated with respect to the applied input signal.

  The delay circuit may reduce the time delay between the input signal and the output signal as the control signal increases.

  The initialization circuit may transmit the input signal as it is as the initialization input signal and the output signal as it is as the initialization output signal when the input signal has the L value and the output signal becomes the H value for the first time.

  In the phase comparison circuit, the phase advance signal may be longer than the phase delay signal as the phase advance of the initialization output signal is greater than that of the initialization input signal.

  In the charge pump circuit and the low-pass filter circuit, the control signal may rise in proportion to the time in which the length of the delayed phase signal is longer than that of the advanced phase signal.

  ADVANTAGE OF THE INVENTION According to this invention, the DLL circuit which can avoid abnormal operation | movement can be provided.

  7 to 14 show specific embodiments of the present invention. FIG. 7 is a diagram showing a configuration example of the operation initialization DLL circuit of the present invention. 8 to 14 show more detailed embodiments of the components shown in FIG.

  The DLL circuit of the present invention requires input of an initialization signal, for example, a signal called a power-on reset. An initialization signal is a signal that generates an input signal.For example, a stable initial state after an unstable and unstable start-up state immediately after the entire circuit system including the clock generation circuit is turned on is terminated to other circuits. It is a signal to be transmitted. Specifically, after the power supply to the entire circuit system is turned on, a signal indicating that the entire circuit has become stable is output by detecting that a certain time has elapsed or that the circuit has reached a certain state. In this embodiment, it is assumed that the initialization signal initially has an H value, and the logic changes to an L value when the entire circuit becomes stable and the initialization is released.

  FIG. 8 shows a detailed configuration example of the delay circuit with an initialization function of the DLL circuit of the present invention. The delay circuit may be used in a conventional DLL circuit, and is not particularly limited, and does not hinder circuit operation specifications and design freedom. The logic of the initialization signal is inverted and the input signal that has passed through the AND circuit is applied. As a result, a sufficiently stable input signal is applied to the delay circuit, and both the input signal and the output signal applied to the initialization circuit are specified to the L value.

  FIG. 9 shows a detailed configuration example of the initialization circuit of the DLL circuit of the present invention. Since the initialization signal has an H value after the operation of the circuit starts, the output Q of the RS flip-flop 91 has an L value, and both the initialization input signal and the initialization output signal have an L value. Further, the logic circuit composed of the AND circuit 94 and the inverter circuit 95 causes the output Q to become the H value only when the output signal becomes the H value and the input signal becomes the L value. As it passes through the initialization circuit, it becomes an initial input signal and an initial output signal, respectively. Since the value no longer changes once the initialization signal has become the L value, the output Q of the RS flip-flop 91 remains permanently at the H value.

  FIG. 10 shows a detailed configuration example of the phase comparison circuit of the DLL circuit of the present invention. The initialization input signal is connected to the reference signal, and the initialization output signal is connected to the comparison signal. The phase comparison circuit according to the present invention is not limited to the example of FIG. 10, and the initial values of the reference signal and the comparison signal are both L and the initial value of the delayed signal and the advanced signal is determined by the initialization signal. Any material having an L value may be used. Here, an example of a specific initialization function in the phase comparison circuit shown in FIG. 10 is shown. The circuit diagram of FIG. 10 has the same configuration as the circuit diagram shown in FIG. 3, and only an entry of a value “H” or “L” indicating an initialization state is added. If both the reference signal and the comparison signal have an L value due to the operation of the logic circuit, the nodes n3 and n8 both have the L value, and the entire circuit converges to the initial value shown in FIG.

  In both the NAND circuit 43 that outputs the node n3 and the NAND circuit 48 that outputs the node n8, if the initialization signal is at the L value while the initialization signal is at the H value, the initialization signal is at the L value. FIG. 11 shows a specific example of a circuit that becomes a general two-input NAND circuit. A Pch type MOSFET 101 and an Nch type MOSFET 102 for setting initial values are added to the Pch type MOSFETs 103 and 104 and the Nch type MOSFETs 105 and 106 constituting a general two-input NAND circuit. With this configuration, the above-described operation is performed.

  By the above initialization function, the phase comparison circuit controls the initialization input signal and the initialization output signal so as to start operation from a state in which the phase comparison circuit outputs the phase advance signal longer than the phase delay signal, and the phase comparison circuit. The initial state of is set.

  FIG. 12 shows a detailed embodiment of the charge pump circuit with operation initialization function and the LPF circuit of the present invention. In this embodiment, the initialization function is implemented by adding an inverter 111 and a Pch type MOSFET 123 to the LPF circuit in addition to the conventional charge pump circuit and LPF circuit. Since the initialization signal is initially at the H value, the gate input of the Pch-type MOSFET 123 becomes the L value and the drain-source is turned on. Thereby, the value of the control signal becomes the H value. When the initialization signal becomes the L value, the gate input of the Pch type MOSFET 123 becomes the H value, which is irrelevant to the operation.

  When the value of the control signal at the time of initialization becomes the H value, referring to FIG. 2, the delay circuit excluding the initialization function, that is, the gate inputs of the Nch MOSFETs 31, 32,. Therefore, the drain currents of the Nch-type MOSFETs 31, 32,..., 3n are maximum, the operating current of each inverter circuit is also maximum, and the delay time is minimum. That is, the control signal is set so that the delay circuit has the minimum delay time.

  FIG. 13 shows another preferred detailed configuration example in which the delay circuit 5 with the initialization function and the initialization circuit 6 of the DLL circuit of the present invention are combined. Since the initial value of the initialization signal is initially an H value, when the input signal is applied, all of the nodes m2, m3, and m4 have an L value and m5 has an H value. Then, the node m6 also has an L value, and the node m7 also has an L value. As a result, the nodes m8 and m9 also become L values, and therefore the input to the phase comparison circuit 7 with the initialization function satisfies both conditions.

  Next, since the initialization signal changes to the L value for canceling the initialization, the node m2 becomes the H value, and the input signal is input to the delay circuit 1. On the other hand, there is a moment when the node m5 becomes the L value and the node m4 takes the H value for the first time by the output signal from the delay circuit 5, so that the node m6 becomes the H value. As a result, an output signal appears at the node m9. The node m7 becomes the H value only at the moment when the input signal rises from the L value to the H value after the node m6 becomes the H value, so that the input signal appears at the node m8.

  Since the circuit operates in the above order, the input to the phase comparison circuit 7 with the initialization function is always performed in the order of the output signal and the input signal. The phase comparison circuit 7 with the initialization function for these two types of signals is used. The operating condition will be satisfied. By using the circuit of FIG. 13, the operation sequence of the circuit is guaranteed at any stage of the operation initialization and the operation start, so that the operation of the entire DLL circuit is also guaranteed.

  FIG. 14 shows a more preferred configuration example of the charge pump circuit 3 of the DLL circuit of the present invention. This circuit can be used by replacing only the charge pump circuit portion as it is in the charge pump circuit 8 and LPF 9 with the initialization function shown in FIG. In the charge pump circuit that constitutes the DLL circuit, the time relationship between the phase advance signal and the phase delay signal that are the input signals is the same as the integral value relationship of the current that is the output signal, that is, both must be linearly proportional. is there. However, since the circuit shown in FIG. 12 uses the Nch type MOSFET 119 for on / off switching of the phase advance signal and the Pch type MOSFET 118 for on / off switching of the slow phase signal, this ideal relationship may not be established. . This is because it is impossible to consistently match the characteristics of the input voltage and the output current due to the on / off switching of the Nch MOSFET and the Pch MOSFET.

  The circuit of FIG. 14 uses an equivalent circuit for on / off switching of both the advanced phase signal and the delayed phase signal. Furthermore, an equivalent current mirror circuit output stage using an Nch-type MOSFET is used for the circuit that determines both the output current when the leading phase signal is on and the output current when the lagging phase signal is on. Can be matched.

  In the circuit of FIG. 14, an analog switch circuit in which Nch type MOSFETs 150 and 151 and Pch type MOSFETs 156 and 157 are arranged in parallel is used for both on / off control of the phase advance signal and the phase delay signal. Since this is performed in a current mirror circuit using Nch type MOSFETs, only Nch type MOSFETs 150 and 151 may be used.

  The embodiment disclosed above is merely a detailed example for disclosing a specific technique, and the scope of the present invention is not limited to this embodiment. For example, all initialization values and initialization signal H values and L values in the embodiment are inverted, and all Pch MOSFETs and Nch MOSFETs constituting the DLL circuit are symmetrical with respect to the power supply (VDD and VSS). The inverted circuit performs the same operation. The specific configurations of the delay circuit, the initialization circuit, the phase comparison circuit, the charge pump circuit, and the LPF circuit are not limited to this embodiment, and the means of the present invention can be applied to other circuits having equivalent functions. And within the scope of the present invention.

It is a figure which shows the structural example of the conventional DLL circuit. FIG. 2 is a diagram illustrating a detailed configuration example of a delay circuit included in the DLL circuit illustrated in FIG. 1. FIG. 2 is a diagram illustrating a detailed configuration example of a phase comparison circuit configuring the DLL circuit illustrated in FIG. 1. FIG. 2 is a diagram illustrating a detailed configuration example of a charge pump circuit and an LPF configuring the DLL circuit illustrated in FIG. 1. FIG. 2 is a diagram illustrating a normal operation example of the DLL circuit illustrated in FIG. 1. FIG. 2 is a diagram illustrating an example of an abnormal operation of the DLL circuit illustrated in FIG. 1. It is a figure which shows the structural example of the DLL circuit of this invention. It is a figure which shows the detailed structural example of the delay circuit with an initialization function which comprises the DLL circuit of this invention shown in FIG. It is a figure which shows the detailed structural example of the initialization circuit which comprises the DLL circuit of this invention shown in FIG. It is a figure which shows the detailed structural example of the phase comparison circuit with an initialization function which comprises the DLL circuit of this invention shown in FIG. It is a figure which shows the further detailed structural example of the phase comparison circuit with an initialization function which comprises the DLL circuit of this invention shown in FIG. It is a figure which shows the detailed structural example of the charge pump circuit with an initialization function and LPF which comprise the DLL circuit of this invention shown in FIG. It is a figure which shows another detailed structural example which combined the delay circuit with an initialization function and the initialization circuit which comprise the DLL circuit of this invention shown in FIG. FIG. 8 is a diagram showing another configuration example of the charge pump circuit constituting the DLL circuit of the present invention shown in FIG. 7.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Delay circuit 2 Phase comparison circuit 3 Charge pump circuit 4 LPF circuit 5 Delay circuit with initialization function 6 Initialization circuit 7 Phase comparison circuit with initialization function 8 Charge pump circuit with initialization function 9 LPF circuit with initialization function 11, 12, ..., 1n, 65, 66, 67, 101, 103, 104, 116, 117, 118, 123, 152, 153, 154, 155, 156, 157 Pch type MOSFET
21, 22, ... 2n, 31, 32, ... 3n, 63, 64, 68, 69, 102, 105, 106, 114, 115, 119, 11A, 144, 145, 146, 147, 148, 149, 150, 151 Nch type MOSFET
41, 42, 50, 51, 54, 55, 61, 82, 95, 111, 112, 130, 158, 159 Inverter circuit 43, 44, ..., 48, 49, 52, 53 NAND circuit 62, 71, 113, 121, 141, 142, 143 Resistance 72, 122 Capacity 81, 92, 93, 94, 131, 132, 133 AND circuit 91, 136 RS flip-flop circuit 134, 135 D flip-flop circuit

Claims (11)

A delay circuit that outputs an output signal that causes a time delay to the input signal according to negative feedback control; and
A phase comparison circuit that compares the phase of the input signal and the output signal and outputs the phase difference;
A circuit for performing the negative feedback control so as to eliminate the phase difference;
An initialization circuit that sets an initial state of the circuit in at least one of the delay circuit, the phase comparison circuit, and the circuit that performs the negative feedback control;
A DLL circuit comprising:   The DLL circuit according to claim 1, wherein the initialization circuit sets the output of the phase comparison circuit in a state where the phase of the input signal is relatively advanced from the phase of the output signal.   The DLL circuit according to claim 1, wherein the initialization circuit sets a delay time of the delay circuit to a substantially minimum.   4. The DLL circuit according to claim 1, further comprising a circuit that controls the phase comparison circuit to input the output signal before the input signal. A delay circuit that is applied after the initialization signal is released and outputs an output signal in which a time delay is generated according to the control signal to the applied input signal;
An initialization input signal and an initialization output signal are output as initial values predetermined by the initialization signal, and when the input signal and the output signal are in a predetermined state after the initialization signal is released, respectively. An initialization circuit that passes through and outputs,
An initial value of the delay circuit or an initializing circuit included therein outputs a delayed signal and a leading signal as an initial value predetermined by the initializing signal, and the input signal and the output after the initialization signal is released A phase comparison circuit for outputting a phase relationship of signals as the delayed phase signal and the advanced phase signal;
A charge pump circuit and a low-pass filter circuit, wherein the control signal is output as an initial value predetermined by the initialization signal, and outputs the control signal in accordance with the delayed signal and the advanced signal after the initialization signal is released; ,
A DLL circuit comprising:   The initialization signal has an H value as an initial value, and changes to an L value after cancellation of the initialization state. The initial values of the initialization input signal and the initialization output signal are both L values, and the delay signal and 6. The DLL circuit according to claim 5, wherein an initial value of the phase advance signal is an L value, and an initial value of the control signal is an H value.   6. The DLL circuit according to claim 5, wherein the delay circuit outputs the output signal in which a time delay corresponding to the control signal is generated with respect to the applied input signal.   6. The DLL circuit according to claim 5, wherein the delay circuit reduces a time delay between the input signal and the output signal as the control signal increases.   When the input signal has an L value and the output signal becomes the H value for the first time, the initialization circuit uses the input signal as it is as the initialization input signal and the output signal as it is as the initialization output signal. The DLL circuit according to claim 5, wherein the DLL circuit transmits the DLL circuit.   6. The DLL circuit according to claim 5, wherein the phase comparison circuit has a length of the phase advance signal that is longer than the phase delay signal as the phase advance of the initialization output signal is greater than that of the initialization input signal. . 6. The DLL circuit according to claim 5, wherein in the charge pump circuit and the low-pass filter circuit, the control signal rises in proportion to a time in which the length of the delayed phase signal is longer than that of the advanced phase signal.

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