JP2004228390A - Cell arrangement method for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the chip area by optimizing the arrangement of cells to minimize a channel region. <P>SOLUTION: Compaction is executed for the chip in a way that the height of cells configuring a cell row, and a minimum interval between the adjacent cells is to be a maximum cell interval H1. Since the compaction is executed for the entire chip, and the wiring region is reduced, the chip area is decreased. Further, since the compaction is executed for the chip, the compaction keeping all the cell interval of the two cell rows the same, and thereafter the channel region is decreased, the compaction is executed for the entire chip, and the wiring region is reduced, then the chip area is reduced without a limit that the height of the chip cell rows is constant. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly, to a cell arrangement method for minimizing a cell arrangement area.
[0002]
[Prior art]
A conventional method for arranging cells of a semiconductor integrated circuit will be described with reference to FIGS.
[0003]
FIG. 8A is a conventional cell configuration diagram having a power supply line at an end of the cell, and FIG. 8B is a conventional power supply change cell configuration diagram having a power supply line at a central portion of the cell. 9) is a cell layout diagram using a conventional cell having a power supply line at the cell end, and FIG. 9B is a cell layout diagram using a conventional power supply change cell.
[0004]
In order to shorten the development period, a conventional semiconductor integrated circuit has a power supply line P1 on the upper side and a ground line G1 on the lower side as shown in FIG. (Referred to simply as a cell), as shown in FIG. 9A, the arrangement / wiring process is performed so as to connect the power supply wiring P1 and the ground wiring G1. At this time, the arrangement area of the cells is defined as a row R, and the area between the cells is distinguished from the channel area where the wiring process is performed.
[0005]
Further, in such a cell configuration, since the cell height is fixed and the area efficiency of the cell is limited, as shown in FIG. 8B, the power supply wiring P2 and the ground wiring G2 are provided at the center of the standard cell. A power supply change cell having a configuration in which wiring is carried out in parallel at a certain interval in the horizontal direction is also used. With this configuration, each logic cell has an optimum width and height without being limited by the height of the cell, and as a result, the cell can be configured with a minimum area. When this power supply change cell is arranged, as shown in FIG. 9B, the power supply wiring P2 and the ground wiring G2 are connected at the center of the cell, and the signal wiring processing is performed in the channel region C1 between the cells. (For example, see Patent Document 1).
[0006]
[Patent Document 1]
JP-A-64-17445 (FIG. 1)
[0007]
[Problems to be solved by the invention]
However, in recent years, miniaturization of semiconductor integrated circuits has progressed, and the number of wiring layers used has also been increasing, so that wiring congestion has been resolved and high integration has become possible. Therefore, in the conventional cell arrangement method, there is a problem that the necessity of a channel region occupied only by the wiring layer is reduced, and this region hinders a reduction in chip area.
[0008]
In order to solve the above problems, it is an object of the present invention to provide a method for arranging cells in a semiconductor integrated circuit, in which the cell arrangement is optimized so as to minimize the channel region, and the chip area is reduced.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, according to a first aspect of the present invention, there is provided a method of arranging cells of a semiconductor integrated circuit, wherein a first-layer power supply wiring and a first-layer grounding wiring are arranged in parallel in a horizontal direction at regular intervals around a center. The method of arranging the standard cells, the step of roughly arranging the standard cells, the step of selecting an arbitrary first cell row among all the cell rows, and the step of selecting the standard cells constituting the first cell row. Replacing a standard cell such that the difference in height is equal to or less than the maximum cell spacing value; and providing an interval between a second cell row adjacent to one of the upper and lower sides of the first cell row and the first cell row. Shortening the distance between the first cell row and the second cell row so that is less than or equal to the cell maximum spacing value, and the number of one or more cell rows within a range in which standard cells can be replaced The channel area to And performing compaction of reduction.
[0010]
3. The method for arranging cells of a semiconductor integrated circuit according to claim 2, wherein said standard cells are arranged in parallel in a horizontal direction at predetermined intervals around a first layer power supply wiring and a first layer ground wiring. A step of roughly arranging cells, a step of selecting arbitrary first and second cell rows vertically adjacent from all the cell rows, and a step of selecting the first cell row and the second cell row Replacing the standard cells so that the intervals between the first cell rows and the second cell rows are equal to or smaller than a maximum cell interval value. Reducing the interval between the second cell rows, and performing compaction for optimizing the channel region for an arbitrary cell row within a range where standard cells can be replaced.
[0011]
According to a third aspect of the present invention, in the method of arranging cells of a semiconductor integrated circuit according to any one of the first and second aspects, the minimum unit constituting a cell row is set between strap power supplies. The compaction is performed for each minimum unit cell row.
[0012]
According to a fourth aspect of the present invention, in the method of arranging cells of a semiconductor integrated circuit according to any one of the first and second aspects, the compaction is performed in units of cell columns divided into arbitrary widths. Each of the divided cell rows subjected to compaction is connected by using a spacer cell having a configuration in which the first-layer power supply wiring and the first-layer ground wiring are bent at a certain interval.
[0013]
According to a fifth aspect of the present invention, in the method of arranging cells of a semiconductor integrated circuit according to the fourth aspect, the width of the first-layer power supply wiring and the first-layer ground wiring of the spacer cell is expanded to a cell frame. A substrate contact is made to the first layer power supply wiring and the first layer ground wiring.
[0014]
By the above method, the cell arrangement can be optimized so as to minimize the channel region, and the chip area can be reduced.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
The cell arrangement method of the semiconductor integrated circuit according to the first embodiment of the present invention will be described with reference to FIGS.
[0016]
FIG. 1 is a flowchart of a method for arranging cells of a semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 2A shows a schematic arranging step in the method of arranging cells of a semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 2B is a layout diagram showing a process of adjusting the cell height of a cell column in the cell arrangement method of the semiconductor integrated circuit according to the first embodiment of the present invention, and FIG. 2C is a diagram showing an embodiment of the present invention. FIG. 9 is a layout chart showing a compaction step in the cell arrangement method of the semiconductor integrated circuit in the first embodiment.
[0017]
First, an outline of a cell arrangement method of a semiconductor integrated circuit according to the first embodiment will be described with reference to FIG.
First, power supply change cells are roughly arranged (S1), and it is determined whether or not channel region optimization processing has been performed for all cell columns (S2). Next, when there is a cell row for which the channel region optimization processing has not been performed, one of the cell rows is selected (S3), and the layout is corrected so that the cell heights of the selected cell rows are aligned. (S4). Finally, compaction is performed to reduce the width of the channel region so that the minimum value of the width of the channel region between the selected cell column and its adjacent cell column becomes the maximum value of the cell interval (S5). The above process is repeated for an arbitrary cell column.
[0018]
Next, a method for optimizing the channel region will be described in detail with reference to FIG.
First, as shown in FIG. 2A, after the schematic arrangement and the power supply connection of the power supply change cell are performed, the maximum cell interval value H1 previously input as the arrangement information before the arrangement is read, and the maximum width Wmax of the channel region is determined. It is detected whether there is a location larger than the cell interval maximum value H1. If there is no location larger than the cell interval maximum value H1, the arrangement step is terminated. If there is a location greater than the cell interval maximum value H1, a cell row B1 having a location greater than the cell interval maximum value H1 is selected, and the difference between the cell heights in the cell row B1 is determined by the cell maximum interval value. In order to arrange the power supply change cells which are equal to or less than H1, the cell having the largest number of the same cells is set as the reference cell M1, and the height of all the cells constituting the cell row B1 is set to the height of the reference cell M1. Then, the power supply changing cell is replaced from the periphery of the cell row B1 so as to be less than the height of the reference cell M1 plus the maximum cell interval value H1 (FIG. 2B). . Next, a cell interval between a cell K1 having the highest cell height and a reference cell M1 in a cell row adjacent to one side of the cell row B1 having the same height is set to a cell interval maximum value H1. Compaction for shortening the channel region C1 is performed (FIG. 2C). Similarly, compaction is performed so that the cell interval with the highest cell in the cell row adjacent to the other side of the cell row B1 having the same height becomes the maximum cell interval value H1. Next, a step of detecting a portion larger than the cell interval maximum value H1 is executed again, and this step is repeated for an arbitrary cell row within a range in which cells can be replaced.
[0019]
As described above, by making the heights of the cells constituting the cell row uniform and setting the minimum distance between the adjacent cell rows to the maximum cell interval H1, the compaction can be performed on the entire chip and the wiring area can be reduced. The chip area can be reduced.
(Embodiment 2)
A cell arrangement method for a semiconductor integrated circuit according to the second embodiment of the present invention will be described with reference to FIGS.
[0020]
FIG. 3 is a flowchart of a method for arranging cells of a semiconductor integrated circuit according to the second embodiment of the present invention. FIG. 4A shows a schematic arrangement step of the method for arranging cells of a semiconductor integrated circuit according to the second embodiment of the present invention. FIG. 4B is a layout diagram showing a process of aligning cell intervals in the cell arrangement method of the semiconductor integrated circuit according to the second embodiment of the present invention, and FIG. 4C is a diagram showing a process according to the second embodiment of the present invention. FIG. 4 is a layout diagram illustrating a compaction step of a cell arrangement method of a semiconductor integrated circuit.
[0021]
First, an outline of a cell arrangement method of a semiconductor integrated circuit according to the second embodiment will be described with reference to FIG.
First, power supply change cells are roughly arranged (S11), and it is determined whether or not channel region optimization processing has been performed for all cell columns (S12). Next, when there is a cell column for which the channel region optimization processing has not been performed, one cell column adjacent to the cell column is selected (S13), and a cell column between the two selected cell columns is selected. The arrangement is corrected so that the cell intervals become the same (S14). Finally, compaction is performed to reduce the width of the channel region so that the minimum value of the width of the channel region between the two selected cell columns becomes the maximum value of the cell interval (S15). The above process is repeated for an arbitrary cell column.
[0022]
Next, a method for optimizing the channel region will be described in detail with reference to FIG.
First, as shown in FIG. 4A, after the schematic arrangement and the power supply connection of the power supply change cell are performed, the cell interval maximum value H2 input in advance as the arrangement information before the arrangement is read, and the maximum width Wmax of the channel region is determined. It is detected whether there is a location larger than the cell interval maximum value H2. If there is no location larger than the cell interval maximum value H2, the arrangement step is terminated. If there is a portion larger than the cell interval maximum value H2, two cell columns B2 of a cell column having a portion larger than the cell interval maximum value H2 and a cell column adjacent thereto are selected. Next, the longest cell interval is set as a reference cell interval W2 so that all the cell intervals between the cell columns B2 are equal to each other so that the cell intervals of the respective cells are uniform with respect to the two selected cell columns B2. The cell arrangement is corrected so as to be equal to or larger than the reference cell interval W2 and equal to or smaller than the cell interval obtained by adding the maximum cell interval value H2 to the reference cell interval W2 (FIG. 4B). Next, compaction for shortening the channel region C2 is performed on the cell row B2 having the same cell interval so that the cell interval becomes the maximum cell interval value H2 (FIG. 4C). Next, a step of detecting a portion larger than the maximum value of the cell interval is executed again, and this step is repeated for an arbitrary cell row as long as the cell can be replaced.
[0023]
In this way, by shortening the channel region after making all the cell intervals of the two cell columns the same, compaction can be performed on the entire chip and the wiring region can be reduced, so that the height of the chip cell column is constant. The chip area can be reduced without any limitation.
[0024]
FIG. 5 is a configuration diagram showing a cell arrangement with respect to a cell column between strap lines in the cell arrangement method of the semiconductor integrated circuit of the present invention.
In FIG. 5, a strap power supply line SP1 for drawing power inside and a strap ground line SG1 for drawing ground potential inside have a configuration in which the minimum cell column unit D1 is between the strap lines.
[0025]
As shown in this configuration, by implementing the invention of the first embodiment of the present invention and the invention of the second embodiment with respect to a cell row between strap wirings, a conventional cell having a wide range traversing the entire chip can be obtained. Since the layout correction can be performed not only in the columns but also in a narrower range, the chip area can be reduced with a small layout change from the schematic layout. (Embodiment 3)
The cell arrangement method of the semiconductor integrated circuit according to the third embodiment of the present invention will be described with reference to FIG.
[0026]
FIG. 6A is a layout diagram illustrating a schematic arrangement step of a cell arrangement method of a semiconductor integrated circuit according to the third embodiment of the present invention, and FIG. 6B is a cell arrangement of the semiconductor integrated circuit according to the third embodiment of the present invention. FIG. 6 (c) is a layout diagram showing a spacer cell replacing step of the cell arrangement method of the semiconductor integrated circuit according to the third embodiment of the present invention.
[0027]
As shown in FIG. 6A, according to the cell arranging method of the semiconductor integrated circuit device according to the third embodiment of the present invention, the first-layer power supply wiring P2 and the first-layer ground wiring G2 in the cell are arranged at a certain interval. The spacer cell R1 having the bent wiring is arranged at a place where the power supply connection of the cell is not in a straight line.
[0028]
Hereinafter, the cell arrangement method will be described in detail.
First, a cell group in which a plurality of bending values U1 of the spacer cell R1 are prepared is registered in a library. Next, as shown in FIG. 6B, the power supply of the power supply change cell is connected after the general arrangement. Next, the cell column range width E1, which has been input in advance as the arrangement information before the arrangement, is read, and the cell column is divided for each cell column range width in order to make the cell column range width the minimum unit of the cell column. . Next, the maximum cell interval value that has been input as arrangement information before arrangement is read, and it is detected whether or not there is a location where the maximum width of the channel region is larger than the maximum cell interval value. If there is no location larger than the cell interval maximum value, the arrangement step is terminated. If there is a portion larger than the maximum cell interval, two cell columns, that is, a cell column having a portion larger than the maximum cell interval and a cell column adjacent thereto are selected. Next, the longest cell interval is set as a reference cell interval so that all the cell intervals between the cell columns are equal to the reference cell so that the cell interval of each cell is constant with respect to the two selected cell columns. The cell arrangement is corrected so as to be equal to or more than the interval and equal to or less than the cell interval obtained by adding the maximum cell interval value to the reference cell interval. Next, compaction for shortening the channel region is performed on the cell row having the same cell interval so that the cell interval becomes the maximum value of the cell interval. Next, the step of detecting a portion larger than the cell interval maximum value is executed again. Finally, since the power supply is disconnected for each cell row range width E1, a spacer cell suitable for each bending value is selected from the library at the disconnected location, and the cell is replaced (FIG. 6C). .
[0029]
As described above, compaction is performed for an arbitrary cell column width, and the power supply wiring is connected to the power supply of those cell columns by using a bent spacer, whereby compaction can be performed on the entire chip and the height of the cell column can be increased. The chip area can be reduced without the limitation that the size is constant, and the layout change from the general layout is minimized.
[0030]
Further, in the substrate contact cell in the conventional cell configuration (FIG. 8A), the substrate contact can be made only by the width of the power supply wiring P1 and the ground wiring G1, whereas the embodiment of the present invention shown in FIG. As shown in the configuration diagram showing the substrate contact in Embodiment 3, the first layer power supply wiring P2 and the first layer ground wiring G2 are extended to the upper and lower sides of the spacer cell R5, and the substrate contact T1 is spread over the expanded portion. Can have.
[0031]
As described above, by setting the power supply region on the spacer cell, the number of substrate contacts can be increased without waste compared to the conventional substrate contact cell, and the effect of stabilizing the ground potential and preventing latch-up can be improved.
[0032]
【The invention's effect】
In the cell arrangement of a semiconductor integrated circuit, compaction is performed on the entire chip by equalizing the height of the cells constituting a cell row and performing compaction so that the minimum distance between adjacent cell rows is the maximum value of the cell interval. As a result, the wiring area can be reduced, so that the chip area can be reduced.
[0033]
In addition, by performing compaction for shortening the channel region after making all the cell intervals of the two cell columns the same, compaction can be performed on the entire chip and the wiring region can be reduced, so that the height of the chip cell column is reduced. The chip area can be reduced without the restriction of being constant.
[0034]
In addition, by performing the compaction on the cell row between the strap wirings, not only the conventional wide cell row traversing the entire chip but also the layout correction can be executed in a narrower range. The chip area can be reduced with a small change in arrangement.
[0035]
Furthermore, compaction can be performed for an arbitrary cell column width, and the power supply wiring can be connected to the power supply of those cell columns using a bent spacer, so that compaction can be performed on the entire chip and the height of the cell column can be reduced. The chip area can be reduced without the restriction of being constant and minimizing the layout change from the schematic layout.
[Brief description of the drawings]
FIG. 1 is a flowchart of a method for arranging cells of a semiconductor integrated circuit according to a first embodiment of the present invention; FIG. 2 (a) shows a schematic arranging step in a method of arranging cells of a semiconductor integrated circuit according to a first embodiment of the present invention; Layout diagram (b) Layout diagram showing the process of aligning the cell heights of the cell columns in the cell arrangement method of the semiconductor integrated circuit according to the first embodiment of the present invention (c) Cell arrangement of the semiconductor integrated circuit according to the first embodiment of the present invention FIG. 3 is a layout diagram showing a compaction step in the method. FIG. 3 is a flowchart of a cell arrangement method of a semiconductor integrated circuit according to a second embodiment of the present invention. FIG. 4 (a) A cell of a semiconductor integrated circuit according to a second embodiment of the present invention. Layout diagram (b) showing a schematic arrangement step of the arrangement method: a step of aligning cell intervals in the cell arrangement method of the semiconductor integrated circuit according to the second embodiment of the present invention FIG. 5 (c) is a layout diagram showing a compaction process of a method for arranging cells of a semiconductor integrated circuit according to a second embodiment of the present invention. FIG. 5 is a diagram showing a cell array between strap lines in a method for arranging cells of a semiconductor integrated circuit according to the present invention. FIG. 6A is a layout diagram illustrating a schematic arrangement step of a cell arrangement method of a semiconductor integrated circuit according to a third embodiment of the present invention. FIG. 6B is a layout diagram illustrating a semiconductor integrated circuit according to a third embodiment of the present invention. FIG. 7 (c) is a layout diagram illustrating a spacer cell replacement step in the cell arrangement method of the semiconductor integrated circuit according to the third embodiment of the present invention. FIG. 8 (a) is a conventional cell configuration having a power supply wiring at an end of a cell, and FIG. FIG. 9 (a) is a conventional cell arrangement diagram using a cell having a power supply line at a cell end, and FIG. 9 (b) is a conventional power supply change cell using a cell having a power supply line at a cell end. Cell layout diagram used [Description of symbols]
B1: Selected cell column B2: Selected cell column C1: Channel region C2: Channel region D1: Minimum cell column unit E1: Cell column range width G1: Ground line G2: Ground line H1: Cell interval maximum value H2: Cell interval maximum value K1: Cell M1 having the highest cell height: Reference cell P1: Power supply wiring P2: Power supply wiring R: Row R1: Spacer cell R5: Spacer cell SP1: Strap power supply wiring SG1: Strap ground wiring T1: Substrate Contact U1: bent value W2: reference cell interval Wmax: maximum channel region width

Claims (5)

In the method of arranging standard cells arranged in parallel in a horizontal direction at a fixed interval around a first layer power supply wiring and a first layer ground wiring,
A step of roughly arranging the standard cells;
Selecting an arbitrary first cell column among all cell columns;
Replacing the standard cells such that the difference in height between the standard cells constituting the first cell row is equal to or less than the maximum cell interval value;
The first cell row and the second cell are arranged such that an interval between the second cell row adjacent to one of the upper and lower sides of the first cell row and the first cell row is equal to or less than a maximum cell interval value. A step of shortening a column interval, and performing compaction for optimizing a channel region for one or more cell columns within a range where standard cells can be replaced. Placement method. In the method of arranging standard cells arranged in parallel in a horizontal direction at a fixed interval around a first layer power supply wiring and a first layer ground wiring,
A step of roughly arranging the standard cells;
Selecting an arbitrary first cell row and second cell row vertically adjacent to each other among all the cell rows;
Replacing the standard cells so that the intervals between the first cell row and the second cell row are constant,
Reducing the distance between the first cell row and the second cell row so that the distance between the first cell row and the second cell row is equal to or less than the maximum cell gap value; A method for arranging cells in a semiconductor integrated circuit, comprising: performing compaction for optimizing a channel region for an arbitrary cell row within a range where cells can be replaced. 3. The method according to claim 1, wherein the compaction is performed between strap power supplies, and the compaction is performed for each of the minimum unit cell rows. A spacer cell having a configuration in which the compaction is performed in units of cell columns divided into arbitrary widths, and the first-layer power supply wiring and the first-layer ground wiring are bent at a certain interval between the divided cell columns in which the compaction is performed. 3. The method for arranging cells of a semiconductor integrated circuit according to claim 1, wherein the connection is performed by using the following. 5. The method according to claim 4, wherein a width of the first layer power supply wiring and the first layer ground wiring of the spacer cell is increased to a cell frame, and a substrate contact is made to the first layer power supply wiring and the first layer ground wiring. Cell arrangement method for a semiconductor integrated circuit.

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