JP2004214386A - Field effect transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that an FET forming process is complicated, deterioration of yield due to complication is anticipated, and carrier mobility is deteriorated by thinning a strain Si layer, in a method using an SGOI (SiGe on insulator) substrate. <P>SOLUTION: The field effect transistor is provided with a semiconductor region formed on a substrate, a first conductivity type channel region formed in the semiconductor region, a gate insulating film which is formed on the channel region and contains at least a metal oxide layer composed of crystalline substance different in lattice interval from the substrate, a gate electrode formed on the gate insulating film, and a second conductivity type source/drain region formed in the semiconductor region on both sides of the gate electrode. The lattice interval at least in the channel region of the substrate is characterized by being modulated. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a field-effect transistor (FET) having a MIS (Metal-Insulator-Semiconductor) structure and a method for manufacturing the same.
[0002]
[Prior art]
Transistors have been improved in performance by increasing the fineness of MOS (Metal-Oxide-Semiconductor) type FETs. However, as the manufacturing process has evolved, the performance improvement due to the pursuit of fineness has begun to fade. The miniaturization of a transistor is to simultaneously reduce the size of each portion of a MOSFET such as the thickness of a gate insulating film and a gate length in a length direction and a lateral direction, but the size is approaching an atomic size. Therefore, the limit of the effect of miniaturization is beginning to be seen.
[0003]
For example, conventionally used SiO 2 ₂ In a gate insulating film composed of, a tunnel current starts to flow directly in a region having a thickness of 2 nm or less, so that a gate leak current cannot be suppressed and problems such as an increase in power consumption cannot be avoided. For this reason, SiO ₂ Using a material (high dielectric substance) having a higher dielectric constant than the gate insulating film, ₂ It is necessary to increase the physical film thickness and suppress the leak current while suppressing the reduced film thickness (hereinafter also referred to as EOT (Equivalent Oxide Thickness)).
[0004]
However, when a high dielectric gate insulating film is used, SiO 2 ₂ As compared with the case of (1), there is a big problem that the carrier mobility is reduced due to the increase of the interface state density and the impurity scattering in the high dielectric film, and the characteristics of the transistor are deteriorated. In order to compensate for such a decrease in carrier mobility, a transistor using strained Si for a channel layer has been developed.
[0005]
The strained Si transistor increases the carrier mobility of the channel layer by utilizing the effect that the crystal lattice of Si is distorted by being affected by the lattice spacing of another crystal in contact with the crystal. By forming a silicon crystal serving as a channel layer serving as a carrier transfer path of a transistor on a silicon germanium (SiGe) layer, the Si crystal of the channel layer in contact with the SiGe layer is distorted, and higher carrier mobility is realized. it can. However, in order to form an SGOI (SiGe on Insulator) substrate serving as the substrate, SiGe is deposited on a SOI (Si on Insulator) substrate, then SiGe is oxidized, Ge is concentrated by oxidation, and then an oxide film is peeled off. It is necessary to go through a complicated process of epitaxially growing Si thereon (for example, see Non-Patent Document 1). Another method of producing strained Si using SiGe is known in order to improve the mobility of a transistor by giving a tensile internal stress or lattice strain to a channel layer (for example, Patent Document 1). reference).
[0006]
As described above, since the FET forming process becomes complicated and complicated, it is expected that the yield of the process will be reduced and problems such as an increase in cost will be caused. Further, as the strained Si layer becomes thinner, the effect of scattering due to Ge diffused from the SiGe layer becomes remarkable, and the carrier mobility deteriorates.
[0007]
Note that in order to improve the mobility of the transistor by giving a tensile internal stress or lattice strain to the channel layer, an undercoat insulating film provided below the channel layer, or silicon oxide or silicon nitride as a material of the gate insulating film. Is known to be used (for example, see Patent Document 2).
[0008]
In addition, SiO 2 is formed on the channel layer. ₂ It is known that an ultra-thin gate insulating film can be realized by epitaxially growing a single-crystal Ce oxide film directly bonded to a Si substrate without forming an amorphous layer such as a non-patent document. 2). However, Non-Patent Document 2 does not disclose that the channel layer is made of strained Si.
[0009]
[Non-patent document 1]
T. Mizuno et al. , IEDM, p. 934 (1999)
[Non-patent document 2]
Y. Nishikawa et al. , Jpn. J. Appl. Phys. 41, 2480 (2002)
[Patent Document 1]
JP 2001-284558 A
[Patent Document 2]
JP-A-2002-176061
[0010]
[Problems to be solved by the invention]
As described above, as the transistor performance improvement due to the pursuit of fineness begins to fade, it is necessary to introduce a new device into the transistor structure itself, such as a strained Si transistor.
[0011]
However, in the method using the conventional SGOI substrate, the FET formation process is complicated and complicated, and it is expected that the yield will be reduced and the cost will be increased. In addition, there is a problem that the effect of scattering by Ge diffused from the SiGe layer becomes remarkable and carrier mobility is deteriorated.
[0012]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a field effect transistor capable of greatly improving transistor characteristics and a method of manufacturing the same.
[0013]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a field effect transistor comprising: a semiconductor region formed on a substrate; a first conductivity type channel region formed on the semiconductor region; A gate insulating film including at least a metal oxide layer made of a different crystalline material, a gate electrode formed on the gate insulating film, and a source of the second conductivity type formed in the semiconductor region on both sides of the gate electrode A drain region, wherein a lattice spacing of at least a channel region of the substrate is modulated.
[0014]
In addition, a field effect transistor according to a second aspect of the present invention includes a semiconductor region formed on a substrate, a first conductivity type channel region formed on the semiconductor region, and a region formed between the substrate and the channel region. An insulating film including at least a crystalline metal oxide layer having a lattice spacing different from that of the substrate, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film, A source / drain region of the second conductivity type formed in the semiconductor region on both sides of the gate electrode, wherein the lattice spacing of at least the channel region of the substrate is modulated.
[0015]
The metal oxide layer may be composed of a rare earth oxide containing at least one or more rare earth elements.
[0016]
The metal oxide layer may include one or more metal elements of Ce, Dy, Y, Gd, La, and Pr.
[0017]
The metal oxide layer may have a composition ratio between metal and oxygen smaller than a stoichiometric ratio.
[0018]
Note that the lattice spacing of the metal oxide layer may be different from the lattice spacing when the composition ratio of metal and oxygen is stoichiometric.
[0019]
Note that a crystalline rock salt structure metal oxide may be provided between the metal oxide layer and the channel region.
[0020]
The rock salt structure metal oxide may contain one or more metal elements of Mg, Ca, Sr, and Ba.
[0021]
Further, a field effect transistor according to a third aspect of the present invention includes a semiconductor region formed on a substrate, a first conductivity type channel region formed on the semiconductor region, and a region formed between the substrate and the channel region. A first insulating film including at least a first metal oxide layer made of crystalline material having a different lattice spacing from the substrate; and a second insulating film formed on the channel region and made of crystalline material having a different lattice spacing from the substrate. A gate insulating film including at least a metal oxide layer, a gate electrode formed on the gate insulating film, and a second conductivity type source / drain region formed in the semiconductor region on both sides of the gate electrode. Wherein the lattice spacing of at least the channel region of the substrate is modulated.
[0022]
Further, in the method of manufacturing a field effect transistor according to the fourth aspect of the present invention, an insulating film containing at least a crystalline metal oxide is formed on a substrate, and an oxygen composition ratio in the metal oxide is determined by a stoichiometric ratio. And a step of forming a gate electrode on the insulating film and a source / drain region on the substrate on each side of the gate electrode, respectively.
[0023]
In the step of reducing the oxygen composition ratio from the stoichiometric ratio, it is preferable that at least one of heat treatment, laser irradiation, electron beam irradiation, and electromagnetic wave irradiation is performed on the insulating film.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0025]
(1st Embodiment)
FIG. 1 shows a sectional configuration of the MISFET according to the first embodiment of the present invention. In the MISFET according to this embodiment, a channel region 5 is formed on the surface of a semiconductor substrate 1 made of Si, and a source region 11a and a drain region 11b having different conductivity types from the channel region 5 are formed on both sides of the channel region 5. It has a configuration. A gate insulating film 7 including at least a crystalline metal oxide film is formed on channel region 5. Since the lattice spacing of the metal oxide film forming the gate insulating film 7 is different from that of Si, Si in the channel region 5 receives stress from the gate insulating film 7 and a strained Si layer is formed. On the gate insulating film 7, a gate electrode 9 made of polysilicon is formed. That is, in the present embodiment, the lattice spacing of Si in the channel region 5 is configured to be different from the lattice spacing of Si in the semiconductor substrate 1. Here, in the case of an n-channel MISFET, the lattice constant of the metal oxide film is made larger than that of Si, and the lattice spacing of Si in the channel layer 5 is increased by tensile stress. Thereby, the mobility of electrons in the channel layer 5 can be increased. On the other hand, in the case of a p-channel MISFET, the lattice constant of the metal oxide film is made larger or smaller than that of Si, and the lattice spacing of Si in the channel layer 5 is changed by tensile stress or compressive stress. Thereby, the mobility of holes in the channel layer 5 can be increased.
[0026]
Next, the method for fabricating the MISFET according to the present embodiment will be described with reference to FIGS. 2 and 3 taking an n-channel MISFET as an example.
[0027]
First, as shown in FIG. 2A, after an element isolation region 2 is formed on a silicon substrate 1 having a (001) plane orientation, for example, a 50 nm thick SiO 2 is formed. ₂ The film 4 is coated on the entire surface. Subsequently, the SiO ₂ By performing ion implantation of boron element through the film 4, a steep impurity profile is formed in the region 5 serving as a channel. Subsequently, the SiO ₂ After the film 4 is removed by etching with an ammonium fluoride solution, dilute hydrofluoric acid treatment is performed to terminate the Si surface of the channel region 5 with hydrogen.
[0028]
Next, the silicon substrate 1 is introduced into an electron beam evaporation apparatus. The substrate temperature is set to, for example, 500 ° C., and Pr ₆ O ₁₁ Using metal oxide Pr as a deposition source ₂ O ₃ Is deposited to a thickness of 5 nm to form a metal oxide film 7a (see FIG. 2B). At this time, the oxygen partial pressure was 1 × 10 ^-7 By precisely controlling Torr, Pr ₂ O ₃ The orientation of the metal oxide film 7a made of was increased to improve the crystallinity. At this time, Si on the surface of the channel layer 5 is oxidized, and the channel layer 5 and Pr ₂ O ₃ Between the metal oxide films 7a made of ₂ The layer 7b was formed. That is, the insulating film 7 is made of SiO 2 having a thickness of 0.5 nm. ₂ Layer 7b and Pr with a thickness of 5 nm ₂ O ₃ It has a laminated structure composed of the layer 7a (see FIG. 2B).
[0029]
From the X-ray diffraction evaluation, Pr ₂ O ₃ The layer 7a was a polycrystalline film oriented in the (001) plane direction, and the lattice constant was 5.52 ° (the lattice constant was 1.7% larger than Si). The half width of X-ray diffraction is narrow, Pr ₂ O ₃ It was confirmed that the layer 7a was a film with high crystallinity strongly oriented to (001).
[0030]
Next, a polysilicon film 9 serving as a gate electrode is deposited on the entire surface by using a CVD (Chemical Vapor Deposition) method (see FIG. 2C).
[0031]
Subsequently, as shown in FIG. 3A, the polysilicon film 9 and the gate insulating film 7 are patterned by using an anisotropic etching method such as an RIE (Reactive Ion Etching) method, and are formed on the channel region 5. A gate insulating film 7 and a gate electrode 9 are formed. Thereafter, by performing ion implantation and a heat process using the gate electrode 7 as a mask, source / drain regions 11a and 11b into which impurities are introduced are formed.
[0032]
Next, the SiO ₂ The film 13 is deposited on the entire surface (see FIG. 3B). Subsequently, as shown in FIG. 3C, a contact hole is opened on the source / drain regions 11a and 11b and the gate electrode 9, and a metal such as Al is deposited to form a metal film on the entire surface. The source / drain electrodes 15a and 15b and the gate connection 15c are formed, and the n-channel MISFET is completed.
[0033]
Next, characteristics of the gate insulating film of the n-channel MISFET having the structure shown in FIGS. 2 and 3 will be described in detail. Normally, even when the metal oxide used as the insulating film is crystalline, the lattice constant does not affect the Si of the channel layer 5. However, this time, we are strongly oriented in the plane orientation (001) and have high crystallinity Pr. ₂ O ₃ It has been found that by forming the layer 7a, tensile stress is applied to Si of the channel layer 5, and the lattice constant changes.
[0034]
FIG. 4 is an enlarged view of the insulating film 7 and the channel region 5 in the n-channel MISFET having the structure shown in FIGS. ₂ O ₃ Layer 7a, SiO ₂ FIG. 9 is a schematic diagram illustrating a cross-sectional structure of a layer 7b and a channel region 5. FIG. 5 shows a change in lattice constant obtained from an electron beam diffraction image measured using a transmission electron microscope (hereinafter, TEM (Transparent Electron Microscope)). What is measured here is the lattice constant in the direction parallel to the interface. The measurement point was Pr, as shown in FIG. ₂ O ₃ Layer 7a, SiO ₂ Si near the interface between the layer 7b and the silicon substrate, Si on the silicon substrate 50 nm away from the interface, and Si on the semiconductor substrate 1 250 nm away from the interface. The change in lattice constant is shown with reference to the lattice spacing of Si 250 nm away from the interface. As can be seen from FIG. ₂ O ₃ Although the lattice constant of the layer 7a is increased by + 1.7% as compared with the Si layer 250 nm away from the interface, this result indicates that the metal oxide Pr obtained from X-ray diffraction ₂ O ₃ Of the lattice constant. Furthermore, this Pr ₂ O ₃ It was found that Si at the interface was distorted by being pulled by the layer 7a, and the change in lattice constant was + 0.5%. Even in Si 50 nm away from the interface, the lattice constant changes, and the lattice constant is increased by + 0.4%.
[0035]
From this result, it can be seen that the lattice spacing of the Si layer in the channel region 5 can be changed by using the insulating film containing a metal oxide having a high crystallinity with a different lattice spacing from Si as the gate insulating film 7. Indicated. It is considered that by increasing the crystallinity, the elastic constant of the metal oxide increases, that is, the crystal is hardened qualitatively. For this reason, it is considered that the lattice constant of the metal oxide greatly affects Si, and lattice deformation occurs even at a depth of 50 nm from the interface.
[0036]
Next, according to this embodiment, crystalline Pr having a different lattice spacing from Si is used. ₂ O ₃ A transistor having a gate insulating film 7 including a layer and a transistor having amorphous SiON as a gate insulating film as a comparative example were manufactured, and characteristics of the present embodiment and a comparative example were compared. FIG. ₂ A transistor of a comparative example having a gate insulating film made of SiON having an equivalent thickness (EOT) of 1.5 nm; ₂ O ₃ / SiO ₂ 5 shows the Id-Vg characteristics of the transistor of the present embodiment having an insulating film having a stacked structure.
[0037]
The S factor of the n-channel MISFET of the comparative example having the gate insulating film made of SiON is 92 mV / decade, and this value is ₂ Is considerably deteriorated as compared with a normal n-channel MOSFET having a gate insulating film. This is because nitrogen diffuses near the interface with the channel region and the interface state density increases.
[0038]
On the other hand, Pr ₂ O ₃ The S-factor of the n-channel MISFET of this embodiment having the gate insulating film including the layer is 75 mV / decade, which indicates that the n-channel MISFET is greatly improved. Further, it can be seen that the current driving force of the present embodiment is also improved as compared with the comparative example. This is because the electron mobility is improved by applying tensile strain to the Si layer of the channel layer, and furthermore, the SiO layer is formed at the interface with the channel layer. ₂ This is because the interface state density could be reduced by the presence of.
[0039]
As described above, according to this embodiment, tensile stress can be applied to Si in the channel region by using an insulating film containing a metal oxide having a different lattice spacing from that of Si as a gate insulating film. By increasing the degree, the transistor characteristics can be significantly improved. Further, it is not necessary to go through a complicated process of depositing SiGe on the SOI to generate strained Si, then oxidizing and concentrating Ge, and epitaxially growing Si thereon. For this reason, a conventional Si substrate or SOI substrate can be used as the substrate, and the cost can be significantly reduced.
[0040]
(2nd Embodiment)
Next, a p-channel MISFET according to a second embodiment of the present invention will be described. The p-channel MISFET according to this embodiment has substantially the same configuration as the MISFET according to the first embodiment shown in FIG. 1, but a metal having a smaller lattice constant than Si is used to apply compressive stress to Si of the channel layer 5. Oxide film, for example, Dy ₂ O ₃ Is used. The manufacturing method is substantially the same as the method shown in FIGS. The channel layer 5 is formed by ion implantation of an arsenic element. Dy ₂ O ₃ The metal oxide film 7a was formed using an electron beam evaporation method. Dy ₂ O ₃ Using Dy as a deposition source ₂ O ₃ Is deposited to a thickness of 5 nm and Dy ₂ O ₃ A metal oxide film 7a made of is formed. At this time, the oxygen partial pressure was 1 × 10 ^-7 By precisely controlling Torr, Dy ₂ O ₃ And the crystallinity was improved. Further, Si on the surface of the channel layer 5 is oxidized, and the channel layer 5 and Dy ₂ O ₃ Between the metal oxide film 7a made of ₂ The layer 7b is formed. That is, the insulating film 7 is made of SiO 2 having a thickness of 0.5 nm. ₂ Layer 7b and Dy having a thickness of 5 nm ₂ O ₃ It has a laminated structure composed of the layer 7a.
[0041]
From the X-ray diffraction evaluation, Dy ₂ O ₃ The layer 7a was a polycrystalline film oriented in the (001) plane direction, and had a lattice constant of 5.33 ° (a lattice constant 1.8% smaller than Si). The half-width of X-ray diffraction is narrow, Dy ₂ O ₃ It was confirmed that the layer was a film with high crystallinity strongly oriented in the plane direction (001). In addition, as a result of lattice constant evaluation using electron beam diffraction, Dy which is strongly oriented in the plane direction (001) and has high crystallinity is obtained. ₂ O ₃ It was confirmed that by forming the layer 7a, compressive stress was applied to Si of the channel layer 5, and the lattice constant was reduced. Dy ₂ O ₃ The change in the lattice constant of the layer 7a is -1.8%. ₂ O ₃ It was found that Si at the interface was distorted accompanying the layer 7a, and the change in lattice constant was -0.5%. Even in Si 50 nm away from the interface, the lattice constant changed, and the lattice constant changed by -0.4%. This result indicates that the lattice spacing of the Si layer in the channel region can be reduced by using an insulating film containing a metal oxide having a smaller lattice spacing and higher crystallinity than Si as the gate insulating film.
[0042]
Dy according to the present embodiment ₂ O ₃ A transistor having a gate insulating film 7 including the layer 7a and a transistor having a gate insulating film made of amorphous SiON as a comparative example were manufactured, and characteristics of the present embodiment and a comparative example were compared. Both are SiO ₂ A p-channel MISFET according to a comparative example having a gate insulating film made of SiON having an equivalent thickness (EOT) of 1.5 nm; ₂ O ₃ / SiO ₂ Comparing the Id-Vg characteristics of the p-channel MISFET according to the present embodiment having the gate insulating film having the laminated structure, the S factor in the comparative example having the SiON gate insulating film is 120 mV / decade, ₂ Is considerably deteriorated as compared with a normal p-channel MOSFET having a gate insulating film. This is because nitrogen diffuses near the interface with the channel layer and the interface state density increases.
[0043]
On the other hand, Dy ₂ O ₃ The S-factor of the p-channel MISFET having the gate insulating film including the layer according to the present embodiment is 100 mV / decade, which is a significant improvement. Further, it was confirmed that the current driving force of the present embodiment was improved as compared with the comparative example. This is because the mobility of holes is improved by applying compressive stress to the Si layer of the channel layer, and furthermore, the SiO layer is formed at the interface with the channel layer. ₂ This is because the interface state density could be reduced by the presence of.
[0044]
As described above, according to this embodiment, even in the p-channel MISFET, the transistor characteristics can be significantly improved by using the insulating film containing the metal oxide having a different lattice spacing from Si as the gate insulating film. .
[0045]
In the first or second embodiment, Pr is used as the crystalline metal oxide. ₂ O ₃ Or Dy ₂ O ₃ As an example, the crystalline metal oxide is SrTiO ₃ , SrZrO ₃ , Sr (TiZr) O ₃ , SrCeO ₃ For example, an oxide having a perovskite structure may be used. Further, oxides having a rock salt structure such as MgO, CaO, SrO, and BaO, Al ₂ O ₃ MgAl with spinel structure ₂ O ₄ However, the same effect can be obtained. Although the crystalline metal oxide was shown to be a polycrystal in which the crystal orientation was oriented, it was confirmed that the use of the single crystal metal oxide caused a larger change in the lattice constant. Although the case where an electron beam evaporation method was used as a method for forming a crystalline metal oxide was shown, other film formation methods such as a CVD method, a sputtering method, and a molecular beam epitaxy (MBE) method were used. You may.
[0046]
Note that among the crystalline metal oxides, rare earth elements (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) It is more preferable to use a rare earth oxide containing at least one or more elements selected from among them. This is because the rare earth oxide can easily increase the crystallinity by controlling the film forming conditions, and can effectively change the lattice spacing of Si. Among them, it is confirmed that when an oxide containing at least one of Ce, Dy, Y, La, Pr, and Gd is used, a film having high crystallinity can be realized, and a particularly high effect can be obtained. Was.
[0047]
Which metal oxide is selected from the crystalline metal oxides described above depends on whether one wants to apply tensile stress or compressive stress to Si. In the case of manufacturing an n-channel MISFET, a metal oxide having a larger lattice constant than Si is selected because electron mobility is improved in Si to which a tensile stress is applied.
[0048]
On the other hand, in the case of manufacturing a p-channel MISFET, the mobility of holes is improved under either tensile or compressive stress, so that a metal oxide having a different lattice constant from Si may be selected. The lattice constant of the metal oxide is selected according to the stress to be applied. When a desired lattice constant and stress cannot be achieved with a metal oxide containing only one type of metal element, a metal oxide containing two or more types of metal elements may be used. For example, it contains two elements of Eu and Dy (Eu _x Dy _1-x ) ₂ O ₃ By using, the change of the lattice constant of the metal oxide with respect to Si can be arbitrarily changed between 0 and -1.8%.
[0049]
(Third embodiment)
Next, an n-channel MISFET according to a third embodiment of the present invention will be described.
[0050]
Although the n-channel MISFET according to the present embodiment has substantially the same configuration as the MISFET according to the first embodiment shown in FIG. 1, in the present embodiment, an oxygen composition ratio is set in order to apply tensile stress to Si of the channel layer. Use a metal oxide having a lower stoichiometric ratio, for example, a Ce oxide. The method of manufacturing the n-channel MISFET according to the present embodiment is almost the same as the method shown in FIGS. As the substrate, Si having a (111) plane orientation is used, and the channel region is formed by ion implantation of boron element. Ce oxide is formed using the MBE method. After dilute hydrofluoric acid treatment is performed on the Si surface in the channel region to terminate with hydrogen, the substrate is introduced into an MBE apparatus. The substrate temperature is set to, for example, 700 ° C., and 0.6 monolayer evaporation of Ce is performed using metal Ce as an evaporation source. ₃ Alternatively, an insulating film made of Ce oxide is formed with a thickness of 5 nm by supplying oxygen gas. The oxygen partial pressure during film formation was 1 × 10 ^-8 Torr. By using such a film forming method, SiO ₂ Without forming an amorphous layer such as this, a single crystal Ce oxide film directly bonded to Si and oriented in the (111) plane direction can be epitaxially grown. The present inventors have already reported that an extremely thin gate insulating film can be realized by using this method (Y. Nishikawa et al., Jpn. J. Appl. Phys. 41, 2480 (2002)). Note that this document does not describe that Si is distorted, and it has become clear from the knowledge of the present inventors that Si is distorted.
[0051]
Next, the characteristics of the gate insulating film of the n-channel MISFET according to the third embodiment will be described in detail. FIG. 7 is an enlarged view of the gate insulating film 8 made of Ce oxide and the channel region, and is a schematic diagram of a cross-sectional structure of the Ce oxide layer 8 and the channel region 5 made of silicon. FIG. 8 shows a change in lattice constant obtained from an electron diffraction image measured using a TEM. What is measured here is the lattice constant in the direction parallel to the interface. As shown in FIG. 7, the measurement points are the gate insulating film 8 made of Ce oxide, Si near the Ce oxide / Si interface, Si 50 nm away from the interface, and Si 250 nm away from the interface. The change in lattice constant is shown with reference to the lattice spacing of Si 250 nm away from the interface. The lattice constant of Ce oxide is about + 0.8% larger than that of Si. In addition, Si at the interface is distorted by + 0.75%. Further, it was found that the lattice constant also changed in Si 50 nm away from the interface, which was a large value of + 0.65%. CeO ₂ Is directly bonded to Si, and since the difference in lattice constant affects the Si layer more directly, the Si layer is greatly distorted, and the change in lattice constant is CeO. ₂ It can be seen that the size is almost the same as that of the layer 8.
[0052]
CeO, a bulk Ce oxide ₂ Is reported to be 5.411 °. That is, CeO is compared with the lattice constant of Si (5.430 °). ₂ Should have a small lattice constant. However, the experimental results of the present inventors show that CeO ₂ The tendency was completely opposite to the reported value of the lattice constant of Ce oxide, and it was found that the lattice constant of Ce oxide was larger than that of Si as shown in FIG. As a result of investigating these causes in detail, a new finding was obtained that a change in the oxygen composition ratio in the Ce oxide causes a change in the lattice constant.
[0053]
FIG. 9 shows a Ce oxide (CeO). _x 2) shows the relationship between the oxygen composition ratio and the lattice constant. The oxygen composition ratio was measured by the energy dispersive X-ray fluorescence method (EDX). When the oxygen composition ratio is a stoichiometric ratio (x = 2.0), the lattice constant is 5.411 °, and the conventional Ce oxide (CeO ₂ ) Is consistent with the reported value of the lattice constant. On the other hand, it was found that when the oxygen composition ratio was smaller than the stoichiometric ratio and x <2.0, the lattice constant was large. As described above, it is considered that the lattice constant of the Ce oxide greatly changes depending on the oxygen composition ratio because the Ce oxide is a crystal having strong ionic bonds.
[0054]
FIGS. 10A and 10B are schematic diagrams of oxygen vacancies in Ce oxide. When the oxygen at the lattice position in the crystal escapes, the lattice position of the Ce atom bonded to the released oxygen is displaced from the original lattice position by being pulled by the bond to another oxygen. As a result, it is considered that the average distance between the lattices increases and the lattice constant increases.
[0055]
The lattice constant of the Ce oxide shown in this embodiment is + 0.8% as compared with that of Si, and it was found from the characteristic graph of FIG. 9 that the oxygen composition ratio was 1.77. The decrease in the oxygen composition ratio is caused by the fact that the oxygen partial pressure during MBE deposition is 1 × 10 ^-8 This is because Torr is set low. By controlling the oxygen partial pressure, the oxygen composition ratio of the Ce oxide can be changed. ^-7 When the pressure was Torr, the oxygen composition ratio was 1.89.
[0056]
Next, the characteristics of an n-channel MISFET having a crystalline Ce oxide film having a lattice spacing different from that of Si as a gate insulating film and an n-channel MISFET having a gate insulating film made of amorphous SiON were compared. FIG. ₂ SiON and Ce oxides (CeO 2) having an equivalent film thickness (EOT) of 1 nm and different oxygen composition ratios _1.77 , CeO _1.89 , CeO _2.00 4) shows the Id-Vg characteristics of an n-channel MISFET having ()) as a gate insulating film.
[0057]
The S-factor of an n-channel MISFET having a gate insulating film made of amorphous SiON is 92 mV / decade, ₂ Is deteriorated as compared with a normal n-channel MISFET using a gate insulating film made of This is because nitrogen has diffused into the interface with the channel region, and the interface state density has increased.
[0058]
Focusing on the Ce oxide, it can be seen that as the oxygen composition ratio decreases, the S-factor decreases and the current driving force improves. When the oxygen composition ratio is x = 2.0, which is the stoichiometric ratio, the S factor is 120 mV / decade, which is further deteriorated compared to the case of SiON. This is considered to be because the electron mobility is lowered due to impurity scattering (for example, diffusion of boron from the gate electrode) in the Ce oxide. However, as the oxygen composition ratio decreased, the S factor decreased, and when x = 1.77, the S factor was improved to 61 mV / decade. This is because, as the oxygen composition ratio decreases, the lattice spacing of Ce oxide increases, so that the lattice spacing of Si in the channel also increases, thereby improving the electron mobility. This is considered to be because the decrease in electron mobility due to impurity scattering in the Ce oxide is compensated for, and the improvement in electron mobility due to the effect of distortion contributes more.
[0059]
Note that CeO is used as a crystalline metal oxide. ₂ Has been described, but the same effect can be obtained if the crystal has high ionic bondability. That is, SrTiO ₃ , SrZrO ₃ , Sr (TiZr) O ₃ , SrCeO ₃ For example, an oxide having a perovskite structure may be used. Further, oxides having a rock salt structure such as MgO, CaO, SrO, and BaO, Al ₂ O ₃ MgAl with spinel structure ₂ O ₄ May be.
[0060]
Although the case where the crystalline Ce oxide is a single crystal is shown, the same effect can be obtained also in the case of a polycrystal in which the crystal orientation is oriented. Although the case where the MBE method is used as a method for forming a crystalline metal oxide is described, other film formation methods such as a CVD method, a sputtering method, and an electron beam evaporation method may be used. Among the crystalline metal oxides, rare earth elements having strong ionic bonding properties (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, It is more preferable to use a rare earth oxide containing at least one or more elements selected from Yb and Lu). Among them, it is confirmed that when an oxide containing at least one of Ce, Dy, Y, La, Pr, and Gd is used, precise control of the oxygen composition ratio can be realized, and a particularly high effect can be obtained. Was done.
[0061]
In the first and second embodiments, the MISFET is formed on a Si substrate having a plane orientation of (001), and in the third embodiment, a MISFET is formed on a silicon substrate having a plane orientation of (111). 001) and (111). Further, the silicon substrate on which the MISFET is formed may have a plane orientation of (110) or may have an angle slightly deviated from the plane orientation.
[0062]
(Fourth embodiment)
Next, a p-channel MISFET according to a fourth embodiment of the present invention will be described. The p-channel MISFET according to the present embodiment has substantially the same configuration as the MISFET according to the second embodiment. However, in the present embodiment, in order to more effectively strain Si in the channel layer, a crystalline metal oxide It is characterized in that a metal oxide having a rock salt structure is sandwiched between an object and a channel layer. The manufacturing method is almost the same as the method shown in FIGS.
[0063]
The channel region is formed by ion implantation of an arsenic element. SrO as a rock salt structure metal oxide and Dy as a metal oxide film ₂ O ₃ And these two types of metal oxides were formed by the MBE method. After dilute hydrofluoric acid treatment is performed on the Si surface in the channel region to terminate with hydrogen, the substrate is introduced into an MBE apparatus. The substrate temperature is set to, for example, 300 ° C., and after depositing two atomic layers of Sr using metal Sr as an evaporation source, oxygen gas is supplied to form an SrO layer.
[0064]
Next, for example, by setting the substrate temperature to 700 ° C. and supplying metal Dy and oxygen gas, ₂ O ₃ A layer is formed to a thickness of 5 nm. The oxygen partial pressure during film formation is 1 × 10 ^-7 Torr. By forming a two atomic layer film of SrO on Si, SiO 2 as shown in the second embodiment is formed. ₂ Dy without any layer formation ₂ O ₃ A layer was formed. This is because SrO prevents diffusion of oxygen. That is, the insulating film is composed of two atomic layers of SrO and Dy. ₂ O ₃ The laminated structure has a layer thickness of 5 nm. Dy formed by such a method ₂ O ₃ It was confirmed from the X-ray diffraction evaluation that the orientation was high and the crystallinity was good. Dy ₂ O ₃ The layer was a polycrystalline film oriented in the (001) plane direction, and the lattice constant was found to be 5.33 ° (the lattice constant was 1.8% smaller than Si).
[0065]
As a result of lattice constant evaluation using electron beam diffraction, it was confirmed that compressive stress was applied to Si of the channel layer and the lattice constant was reduced. Dy ₂ O ₃ Was -1.8%, and the change in the lattice constant of Si near the interface was -0.8%. Even in Si 50 nm away from the interface, the lattice constant changed, and the lattice constant changed by -0.7%. The amount of change in the lattice constant of Si is about twice as large as that in the second embodiment in which the SrO layer is not used. Amorphous SiO ₂ Since no layer was formed, the difference in lattice spacing in the metal oxide film was more directly added to the Si layer, and the lattice constant of SrO was 5.12 ° and Dy. ₂ O ₃ This is because the effect of applying a compressive stress is further increased because the size is smaller than that. Here, the thickness of the SrO layer is 2 atomic layers, but it has been found that the thickness of the SrO layer is desirably in the range of 1 to 3 atomic layers. Since substances such as SrO and MgO are unstable in the air, if the thickness is further increased, the crystallinity changes over time and the characteristics deteriorate. On the other hand, when the thickness is smaller than one atomic layer, the effect of suppressing diffusion of oxygen cannot be obtained, and SiO ₂ This is because a layer is generated.
[0066]
The SrO layer and Dy described above ₂ O ₃ The characteristics of a transistor having a gate insulating film including a layer and a transistor having amorphous SiON as a gate insulating film were compared. Both are SiO ₂ A gate insulating film made of SiON having an equivalent thickness (EOT) of 1.5 nm; ₂ O ₃ Comparison of the Id-Vg characteristics of p-channel MISFETs each having a gate insulating film having a / SrO stacked structure reveals that the S factor of the gate insulating film made of SiON is 120 mV / decade. ₂ Is considerably deteriorated as compared with that of a normal p-channel MOSFET having a gate insulating film. This is because nitrogen diffuses near the interface with the channel layer and the interface state density increases.
[0067]
On the other hand, Dy ₂ O ₃ The S-factor of the p-channel MISFET having the gate insulating film including the / SrO layer according to the present embodiment is 90 mV / decade, which is a significant improvement. In addition, it was confirmed that the current driving force of the present embodiment was improved as compared with the case of SiON. This is because the hole mobility is further improved by applying a larger compressive stress to the Si layer of the channel layer.
[0068]
As described above, according to the present embodiment, it has been clarified that the effect of using a metal oxide having a different lattice spacing from Si is further enhanced by inserting a metal oxide having a rock salt structure.
[0069]
In this embodiment, the case where SrO is used has been described, but a metal oxide having another rock salt structure may be used. In particular, when a metal oxide film having a rock salt structure of SrO, MgO, CaO, and BaO is used, the effect of suppressing oxygen diffusion is remarkable, and the transistor characteristics can be significantly improved.
[0070]
When it is desired to apply tensile stress to Si, it is preferable to use BaO which is a metal oxide having a rock salt structure having a larger lattice constant than Si. When compressive stress is to be applied to Si, it is desirable to use SrO, MgO, and CaO, which are rock-salt metal oxides having a smaller lattice constant than Si. However, since the change in the lattice constant in the Si layer is mainly determined by the crystalline metal oxide having a large film thickness formed on the Si layer, for example, SrO having a lattice constant smaller than that of Si Has a larger lattice constant than Si ₂ O ₃ In the structure in which Si is stacked, Si in the channel region receives a tensile stress, so that the metal oxide having the rock salt structure and the crystalline metal oxide can be arbitrarily combined.
[0071]
(Fifth embodiment)
FIG. 12 shows a sectional configuration of the MISFET according to the fifth embodiment of the present invention. In the MISFET according to this embodiment, an insulating film 3 containing at least a crystalline metal oxide having a different lattice spacing from Si is embedded in a semiconductor substrate 1 made of Si. A channel region 5 is formed in the semiconductor substrate 1, and a source region 11 a and a drain region 11 b having different conductivity types from the channel region 5 are formed in the semiconductor substrate 1 on both sides of the channel region 5. Further, a gate insulating film 7 is formed on the channel region 5. Si in the channel region 5 receives a stress from the metal oxide to form a strained Si layer. On the gate insulating film 7, a gate electrode 9 made of polysilicon is formed.
[0072]
When the MISFET according to the present embodiment is an n-channel MISFET, the lattice constant of the insulating film 3 made of a metal oxide is made larger than that of Si, and the lattice spacing of Si in the channel layer 5 is expanded by tensile stress. This makes it possible to increase the mobility of electrons in the channel layer. On the other hand, when the MISFET according to the present embodiment is a p-channel MISFET, the lattice constant of the metal oxide is made larger or smaller than that of Si, and the lattice spacing of Si in the channel layer is changed by tensile stress or compressive stress. . This makes it possible to increase the mobility of holes in the channel layer.
[0073]
Next, the method for fabricating the n-channel MISFET according to the present embodiment will be explained with reference to FIGS.
[0074]
First, the surface of the silicon substrate 1 having the (001) plane orientation is subjected to dilute hydrofluoric acid treatment, and the surface of the silicon substrate 1 is terminated with hydrogen. Subsequently, as shown in FIG. 13A, the silicon substrate 1 is introduced into a sputtering apparatus, the substrate temperature is set to, for example, 600 ° C., and La ₂ O ₃ Metal oxide La on the silicon substrate 1 using ₂ O ₃ Is deposited to a thickness of 10 nm to form an insulating film 3. At this time, the oxygen partial pressure was 5 × 10 ^-7 By precisely controlling Torr, La ₂ O ₃ And the crystallinity was improved. Further, Si on the surface of the silicon substrate 1 is oxidized, and the silicon substrate 1 and the metal oxide La ₂ O ₃ Between the insulating films 3a made of ₂ Layer 3b was formed. From the X-ray diffraction evaluation, La ₂ O ₃ The layer 3a was a polycrystalline film oriented in the (001) direction, had a lattice constant of 5.70 °, and was found to have a lattice constant 5.0% larger than that of Si. The half width of X-ray diffraction is narrow, La ₂ O ₃ It was confirmed that the layer 3a was a highly crystalline film that was strongly oriented in the plane direction (001).
[0075]
Next, a channel layer 5 made of Si having a thickness of 100 nm is formed by a CVD method (see FIG. 13B). At this time, the metal oxide La ₂ O ₃ 1 nm thick SiO 2 is provided between the insulating film 3a made of ₂ Layer 3c was formed. That is, the insulating film 3 is made of SiO 2 having a thickness of 2 nm. ₂ Layer 3b, La with a thickness of 10 nm ₂ O ₃ Layer 3a, 1 nm thick SiO ₂ It has a laminated structure composed of the layer 3c.
[0076]
Next, element isolation regions 2 are formed on both sides of the channel layer 5, and then, for example, a 50 nm thick SiO 2 is formed. ₂ The film 4 is coated on the entire surface. Subsequently, the SiO ₂ By performing ion implantation of boron element through the film 4, a steep impurity profile is formed in the channel layer 5 (see FIG. 13C). After that, the SiO ₂ After the film 4 is removed by etching with an ammonium fluoride solution, the silicon surface of the channel layer 5 is treated with diluted hydrofluoric acid and terminated with hydrogen.
[0077]
Next, by performing thermal oxidation, SiO 2 ₂ A gate insulating film 7 made of, for example, 3 nm is formed. Subsequently, a polysilicon film 9 serving as a gate electrode is deposited on the entire surface by using the CVD method (see FIG. 13D).
[0078]
Subsequently, as shown in FIG. 14A, the polysilicon film 9 and the gate insulating film 7 are patterned using, for example, an anisotropic etching method such as an RIE method, and the gate insulating film 7 and the gate insulating film 7 are formed on the channel layer 5. A gate electrode 9 is formed. Thereafter, ion implantation and a heat process are performed using the gate electrode 9 as a mask to form the source / drain regions 11a and 11b into which impurities are introduced (see FIG. 14A).
[0079]
Next, the SiO ₂ Is deposited on the entire surface (see FIG. 14B). Subsequently, as shown in FIG. 14C, contact holes are formed on the source / drain regions 11a and 11b and the gate electrode, and a metal film such as Al is deposited on the entire surface by depositing a metal such as Al. The source / drain electrodes 15a and 15b and the gate electrode 15c are formed, and an n-channel MISFET is completed (see FIG. 14C).
[0080]
Next, characteristics of the channel layer 5 of the n-channel MISFET having the structure shown in FIGS. 13 and 14 will be described in detail. FIG. ₂ Layer 3b / La ₂ O ₃ Layer 3a / SiO ₂ FIG. 3 is an enlarged view of an insulating film 3 having a layered structure of a layer 3c and a channel layer 5, schematically showing a cross-sectional structure. FIG. 16 shows a change in lattice constant obtained from an electron diffraction image measured using a TEM. What is measured here is the lattice constant in the direction parallel to the interface. The measurement point was, as shown in FIG. ₂ Si layer, 250 nm away from the interface between layer 3b and Si substrate 1, La ₂ O ₃ Layer 3a, Si channel layer 5 and SiO ₂ Si layer near the interface with layer 3c, Si layer 50 nm away from this interface, Si layer 100 nm away from this interface (SiO ₂ 3) shows Si) near the interface between the gate insulating film 7 and the channel layer 5.
[0081]
FIG. ₂ The change of the lattice constant is shown with reference to the lattice spacing of Si at a position 250 nm away from the interface between the layer 3b and the Si substrate 1. La ₂ O ₃ The lattice constant of the layer 3a is increased by 5.0% as compared with the reference Si layer. This result shows that the metal oxide La obtained from the X-ray diffraction ₂ O ₃ Of the lattice constant. Channel layer 5 and SiO ₂ Si of the channel layer 5 near the interface with the layer 3c is La ₂ O ₃ Distortion is + 1.0% accompanying the layer 3a. Further, it was found that the lattice constant of Si at a position 50 nm away from this interface also changed, and was distorted by + 0.8%. In addition, the channel layer 5 at a position 100 nm away from this interface (that is, SiO 2 ₂ It was confirmed that Si in the Si) near the interface between the gate insulating film 7 and the channel layer 5 was also distorted by + 0.6%. This result indicates that the lattice spacing of the Si layer in the channel region 5 can be increased by burying an insulating film containing a metal oxide having a larger lattice spacing and higher crystallinity than Si in the substrate.
[0082]
According to the present embodiment, crystalline La having a different lattice spacing from Si ₂ O ₃ The characteristics of a transistor in which an insulating film including a layer is embedded in a silicon substrate 1 and the characteristics of a strained SGOI transistor as a comparative example are compared. FIG. 17 shows a cross-sectional structure of a strained SGOI transistor as a comparative example manufactured by a known method. In this strained SGOI transistor, in order to form strained Si, a SiGe layer 104 is deposited on an SOI substrate including a silicon substrate 101, a SiGe layer 102, an insulating film 103, and a silicon layer (not shown), and then oxidized to form Ge. Concentrate. This enrichment results in the formation of SiO on the Ge enriched SiGe layer 104. ₂ A complicated process such as stripping the film and then epitaxially growing the Si layer 105 on the SiGe layer 104 is required. Thereby, the Si layer 105 becomes strained Si. SiO on the Si layer 105 ₂ A source region 109a and a drain region 109b are formed by forming a gate insulating film 107 and a gate electrode 108 made of, and introducing impurities into the Si layer 105 and the SiGe layer 104 on both sides of the gate electrode 108.
[0083]
On the other hand, in the method according to the present embodiment, a Si substrate can be used as the substrate, and a significant cost reduction can be achieved. FIG. 18 shows a 3 nm SiO ₂ An n-channel MISFET according to a comparative example of an SGOI structure having a gate insulating film; ₂ O ₃ FIG. 9 compares the Id-Vg characteristics of the n-channel MISFET according to the present embodiment manufactured by embedding the layer.
[0084]
The S factor of the n-channel MISFET according to the comparative example having the strained SGOI structure is 75 mV / decade.
[0085]
On the other hand, La ₂ O ₃ The S-factor of the n-channel MISFET according to the present embodiment in which the layer is buried is 70 mV / decade, and it is confirmed that the n-channel MISFET is not only inferior to the comparative example having the strained SGOI structure but is improved. In addition, it can be seen that the current driving force of the present embodiment is also improved as compared with the comparative example. This is because sufficient tensile strain can be applied to the Si layer of the channel layer, thereby improving the mobility of electrons, and further avoiding the decrease in mobility due to Ge diffusion observed when using an SGOI substrate. It depends.
[0086]
As described above in detail, according to the present embodiment, tensile stress can be applied to Si in the channel region by burying an insulating film containing a metal oxide having a different lattice spacing from Si in the substrate. Further, according to the present embodiment, it is possible to improve the transistor characteristics by increasing the electron mobility without going through a complicated process such as using a conventional strained SGOI.
[0087]
In the fifth embodiment, the crystalline metal oxide forming the insulating film 3a is La ₂ O ₃ As an example, the crystalline metal oxide is SrTiO ₃ , SrZrO ₃ , Sr (TiZr) O ₃ , SrCeO ₃ For example, an oxide having a perovskite structure may be used. Further, oxides having a rock salt structure such as MgO, CaO, SrO, and BaO, Al ₂ O ₃ MgAl with spinel structure ₂ O ₄ However, the same effect can be obtained. Although the crystalline metal oxide was shown to be a polycrystal in which the crystal orientation was oriented, it was confirmed that the use of the single crystal metal oxide caused a larger change in the lattice constant.
[0088]
Although the case where a sputtering method is used as a method for forming a crystalline metal oxide is described, another film formation method such as a CVD method, an electron beam evaporation method, or an MBE method may be used. .
[0089]
Note that among the crystalline metal oxides, rare earth elements (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) It is more preferable to use a rare earth oxide containing at least one or more elements selected from among them. This is because the rare earth oxide can easily increase the crystallinity by controlling the film formation conditions, and can effectively change the lattice spacing of Si. Among them, it was confirmed that when an oxide containing at least one of Ce, Dy, Y, La, Pr, and Gd was used, a film having high crystallinity could be realized, and a particularly high effect was obtained. .
[0090]
In the fifth embodiment, the case of the n-channel MISFET has been described, but the same method can be applied to the p-channel MISFET. Which metal oxide is selected from the crystalline metal oxides described above depends on whether one wants to apply tensile stress or compressive stress to Si. In the case of manufacturing an n-channel MISFET, a metal oxide having a larger lattice constant than Si is selected because electron mobility is improved in Si to which a tensile stress is applied. On the other hand, in the case of manufacturing a p-channel MISFET, the mobility of holes is improved under either tensile or compressive stress, so that a metal oxide having a different lattice constant from Si may be selected.
[0091]
The lattice constant of the metal oxide is selected according to the stress to be applied. When a desired lattice constant and stress cannot be achieved with a metal oxide containing only one type of metal element, a metal oxide containing two or more types of metal elements may be used. For example, it contains two elements of Eu and Dy (Eu _x Dy _1-x ) ₂ O ₃ , The change of the lattice constant of the metal oxide with respect to Si can be arbitrarily changed between 0 and -1.8%.
[0092]
(Sixth embodiment)
Next, an n-channel MISFET according to a sixth embodiment of the present invention will be described. The n-channel MISFET according to the present embodiment has a configuration similar to that of the n-channel MISFET according to the fifth embodiment shown in FIG. 12, but in the present embodiment, an insulating material is used to apply a tensile stress to Si of the channel layer. As the film 3, a metal oxide having a composition ratio of metal and oxygen smaller than the stoichiometric ratio, for example, a Ce oxide is embedded in the substrate.
[0093]
The method of fabricating the n-channel MISFET in this embodiment is almost the same as the method shown in FIGS. 13 and 14, but uses a silicon substrate having a (111) plane orientation as the substrate. Ce oxide is formed using the MBE method. After dilute hydrofluoric acid treatment is performed on the Si surface of the substrate to terminate it with hydrogen, it is introduced into an MBE apparatus. The substrate temperature is set to, for example, 700 ° C., and 0.6 monolayer evaporation of Ce is performed using metal Ce as an evaporation source. ₃ Alternatively, an insulating film made of Ce oxide is formed to a thickness of 5 nm by supplying oxygen gas. The oxygen partial pressure during film formation was 1 × 10 ^-8 Torr. By using such a film forming method, SiO ₂ A single crystal Ce oxide film directly bonded to Si and oriented in the (111) direction can be epitaxially grown without forming an amorphous layer such as that described above. Hereinafter, steps similar to those shown in FIGS. 13B to 14B are performed to complete an n-channel MISFET.
[0094]
The composition ratio of metal and oxygen of the Ce oxide formed by the above method was 1.77, and the lattice constant was + 0.8% as compared with Si. As described in the third embodiment, the decrease in the oxygen composition ratio of the Ce oxide is caused by the fact that the oxygen partial pressure during MBE film formation is 1 × 10 ^-8 This is because Torr is set low. By controlling the oxygen partial pressure, the composition ratio between the metal and oxygen of the Ce oxide can be changed. ^-7 When the pressure is Torr, the composition ratio is 1.89, and the change in the lattice constant is almost 0%. The strain in the Si channel layer formed on the Ce oxide having the composition ratio x = 1.77 was + 0.75%. The strain in the Si channel layer formed on the Ce oxide having the composition ratio x = 1.89 was almost 0%.
The characteristics of the transistor according to the present embodiment in which a crystalline Ce oxide having a different lattice spacing from Si and embedded in a Si substrate is compared with the characteristics of a strained SGOI transistor as a comparative example.
[0095]
FIG. 19 shows 3 nm SiO 2 ₂ An n-channel MISFET having an SGOI structure having a gate insulating film and a Ce oxide (CeO _1.77 , CeO _1.89 , CeO _2.00 7) is a comparison of the Id-Vg characteristics of an n-channel MISFET manufactured by embedding the above. The S factor in the strained SGOI n-channel MISFET is 75 mV / decade. Focusing on the Ce oxide, it can be seen that as the composition ratio of metal and oxygen decreases, the S factor decreases and the current driving force improves. When the composition ratio of metal and oxygen is stoichiometric, x = 2.0, the S factor is degraded to 120 mV / decade. At this time, the lattice constant of the Ce oxide is smaller than that of Si, and compressive strain is applied to Si of the channel layer, so that the mobility of electrons decreases and the S factor deteriorates. As the composition ratio decreased, the S factor increased, and at x = 1.77, decreased to 61 mV / decade. This is because, as the composition ratio of metal and oxygen decreases, the lattice spacing of Ce oxide increases, and the lattice spacing of Si in the channel also increases, thereby improving the electron mobility. It has been confirmed that the S-factor of the n-channel MISFET in which the Ce oxide having the composition ratio x = 1.77 is buried is not only inferior to the strained SGOI but is improved. Also, it can be seen that the current driving force is improved as compared with the case of the strained SGOI. This is because sufficient tensile strain can be applied to the Si layer of the channel layer, thereby improving the mobility of electrons, and further avoiding the decrease in mobility due to Ge diffusion observed when using an SGOI substrate. It depends.
[0096]
Note that CeO is used as a crystalline metal oxide. ₂ Has been described, but the same effect can be obtained if the crystal has high ionic bondability. That is, SrTiO ₃ , SrZrO ₃ , Sr (TiZr) O ₃ , SrCeO ₃ For example, an oxide having a perovskite structure may be used. Further, oxides having a rock salt structure such as MgO, CaO, SrO, and BaO, Al ₂ O ₃ And MgAl2O with spinel structure ₄ May be. Although the case where the crystalline Ce oxide is a single crystal is shown, the same effect can be obtained also in the case of a polycrystal in which the crystal orientation is oriented.
[0097]
In this embodiment, the case where the MBE method is used as a method of forming a crystalline metal oxide is described. However, the film forming method may be another method such as a CVD method, a sputtering method, or an electron beam evaporation method. A method may be used. Among the crystalline metal oxides, rare earth elements having strong ionic bonding properties (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, It is more preferable to use a rare earth oxide containing at least one or more elements selected from Yb and Lu). Among them, when an oxide containing at least one of Ce, Dy, Y, La, Pr, and Gd is used, precise control of the composition ratio of metal and oxygen can be realized, and a particularly high effect can be obtained. It was confirmed.
[0098]
In the fifth embodiment, the MISFET is formed on a Si substrate having a plane orientation of (001), and in the sixth embodiment, a MISFET is formed on a silicon substrate having a plane orientation of (111). Any of (111) may be used. Further, the silicon substrate on which the MISFET is formed may have a plane orientation of (110) or may have an angle slightly deviated from the plane orientation.
[0099]
Further, in the fifth and sixth embodiments, it is also effective to interpose a rock-salt structure metal oxide between the crystalline metal oxide and the channel layer in order to more effectively strain Si in the channel layer. There is. The effect is the same as that described in detail in the fourth embodiment. By sandwiching a metal oxide having a rock salt structure, an amorphous SiO 2 is formed at the interface with the crystalline oxide. ₂ Since the layer is not formed, the difference in lattice spacing in the metal oxide film is added more directly to the Si channel layer. The thickness of the rock salt structure oxide used is preferably in the range of 1 to 3 atomic layers. Since substances such as SrO and MgO are unstable in the air, if the thickness is further increased, the crystallinity changes over time and the characteristics deteriorate. On the other hand, when the thickness is smaller than one atomic layer, the effect of suppressing diffusion of oxygen cannot be obtained, and amorphous SiO 2 ₂ This is because a layer is generated. Among oxides having a rock salt structure, in particular, when a metal oxide film having a rock salt structure of SrO, MgO, CaO, and BaO is used, the effect of suppressing oxygen diffusion is remarkable, and transistor characteristics can be significantly improved. It is.
[0100]
When it is desired to apply tensile stress to Si, it is desirable to use BaO which is a rock-salt metal oxide having a larger lattice constant than Si. When compressive stress is to be applied to Si, it is desirable to use SrO, MgO, and CaO, which are rock-salt metal oxides having a smaller lattice constant than Si. However, since the change of the lattice constant in the Si layer is mainly determined by the crystalline metal oxide having a large film thickness, for example, SrO having a smaller lattice constant than Si is interposed, and the Big Pr ₂ O ₃ In the structure in which Si is stacked, Si in the channel region receives a tensile stress, so that the metal oxide having the rock salt structure and the crystalline metal oxide can be arbitrarily combined.
[0101]
(Seventh embodiment)
FIG. 20 shows a sectional configuration of the MISFET according to the seventh embodiment of the present invention. In the MISFET according to this embodiment, an insulating film 3 containing a crystalline metal oxide having a different lattice spacing from Si is embedded in a semiconductor substrate 1 made of Si. A channel region 5 is formed in the semiconductor substrate 1, and a source region 11 a and a drain region 11 b having different conductivity types from the channel region 5 are formed in the semiconductor substrate 1 on both sides of the channel region 5. A gate insulating film 7 containing at least a crystalline metal oxide having a different lattice spacing from Si is formed on the channel region 5. The channel region 5 receives a stress from the metal oxide included in the insulating film 3 and the metal oxide included in the gate insulating film 7 to form a strained Si layer. On the gate insulating film 7, a gate electrode 9 made of polysilicon is formed.
[0102]
Next, the method for fabricating the p-channel MISFET according to the present embodiment will be explained with reference to FIGS. First, dilute hydrofluoric acid treatment is performed on the surface of the Si substrate 1 having the (001) plane orientation, and the surface of the Si substrate 1 is terminated with hydrogen. Subsequently, the Si substrate 1 is introduced into an electron beam evaporation apparatus, the substrate temperature is set to, for example, 700 ° C., and Y ₂ O ₃ Metal oxide Y on Si substrate 1 using ₂ O ₃ Is deposited to a thickness of 10 nm to form a metal oxide Y. ₂ O ₃ Is formed. At this time, the oxygen partial pressure was 5 × 10 ^-7 By precisely controlling Torr, Y ₂ O ₃ The crystallinity was improved by increasing the orientation of the layer 3a. Further, Si on the surface of the Si substrate 1 is oxidized, and the Si substrate 1 and the metal oxide Y ₂ O ₃ Between the layer 3a and a layer of SiO having a thickness of 1 nm, ₂ The layer 3b was formed (see FIG. 21A). From the X-ray diffraction evaluation, Y ₂ O ₃ The layer 3a was a polycrystalline film oriented in the plane direction (001), and had a lattice constant of 5.30 ° (later 2.4% smaller than Si). The half width of X-ray diffraction is narrow, and Y ₂ O ₃ It was confirmed that the layer 3a was a highly crystalline film that was strongly oriented in the plane direction (001).
[0103]
Next, a Si channel layer 5 having a thickness of 100 nm is formed by a CVD method (see FIG. 21B). At this time, the metal oxide Y ₂ O ₃ Between the layer 3a and the channel layer 5, a 1-nm thick SiO ₂ Layer 3c was formed. That is, the insulating film 3 is made of SiO 1 having a thickness of 1 nm. ₂ Layer 3b, Y having a thickness of 10 nm ₂ O ₃ Layer 3a, 1 nm thick SiO ₂ It has a laminated structure composed of the layer 3c (see FIG. 21B).
[0104]
Next, element isolation regions 2 are formed on both sides of the channel layer 5, and thereafter, for example, a 50 nm-thick SiO 2 film is formed. ₂ The film 4 is coated on the entire surface. Subsequently, the SiO ₂ By performing ion implantation of boron element through the film 4, a steep impurity profile is formed in the channel layer 5 (see FIG. 21C). After that, the SiO ₂ After the film 4 is removed by etching with an ammonium fluoride solution, the Si surface of the channel layer 5 is treated with diluted hydrofluoric acid and terminated with hydrogen.
[0105]
Next, the Si substrate 1 is introduced into an electron beam evaporation apparatus, the substrate temperature is set to, for example, 700 ° C., and Y ₂ O ₃ Metal oxide Y on the channel layer 5 using ₂ O ₃ Is deposited to a thickness of 10 nm to form a gate insulating film 7. At this time, the oxygen partial pressure was 5 × 10 ^-7 By precisely controlling Torr, Y ₂ O ₃ The crystallinity was improved by increasing the orientation of the layer 7a. From the X-ray diffraction evaluation, Y ₂ O ₃ The layer 7a was a polycrystalline film oriented in the (001) plane direction, and the lattice constant was 5.30 ° (later 2.4% smaller than Si). The half width of X-ray diffraction is narrow, and Y ₂ O ₃ It was confirmed that the layer 7a was a highly crystalline film strongly oriented in the plane direction (001). At this time, the metal oxide La contained in the gate insulating film 12 is ₂ O ₃ Between the layer 7a and the channel layer 5, a 1-nm thick SiO ₂ The layer 7b was formed. That is, the gate insulating film 7 is formed of a 1 nm-thick SiO 2 film. ₂ Layer 7b and 10 nm thick La ₂ O ₃ It has a laminated structure composed of the layer 7a (see FIG. 21D).
[0106]
Next, a polysilicon film 9 serving as a gate electrode is deposited on the entire surface by CVD (see FIG. 22A). Subsequently, as shown in FIG. 22B, the polysilicon film 9 and the gate insulating film 7 are patterned by using an anisotropic etching method such as an RIE method, and the gate insulating film 7 is formed on the channel layer 5. A gate electrode 9 is formed. Thereafter, by performing ion implantation and a heat process using the gate electrode 9 as a mask, the source / drain regions 11a and 11b into which impurities are introduced are formed.
[0107]
Next, the SiO ₂ The film 13 is deposited on the entire surface (see FIG. 23A). Subsequently, as shown in FIG. 23B, contact holes are formed on the source / drain regions 11a and 11b and the gate electrode 9, and a metal such as Al is deposited to form a metal film on the entire surface. The source / drain electrodes 15a and 15b and the gate connection part 15c are formed, and the p-channel MISFET is completed.
[0108]
Next, the characteristics of the channel layer of the p-channel MISFET according to the present embodiment having the structure shown in FIGS. 21 to 23 will be described in detail. FIG. ₂ Layer 3c / Y ₂ O ₃ Layer 3a / SiO ₂ An insulating film 3 having a layered structure of a layer 3b, a channel layer 5, and Y ₂ O ₃ Layer 7a / SiO ₂ FIG. 3 is an enlarged view of a gate insulating film 7 having a layered structure of a layer 7b, and schematically shows a cross-sectional structure. FIG. 25 shows a change in lattice constant obtained from an electron diffraction image measured using a TEM. What is measured here is the lattice constant in the direction parallel to the interface. The measurement points are as shown in FIG. ₂ Si at a position 250 nm away from the interface between the layer 3 b and the Si substrate 1, Y in the insulating film 3 ₂ O ₃ Layer 3a, Si channel layer 5 and SiO ₂ A Si channel layer near the interface with the layer 7b, a Si channel layer at a distance of 50 nm from this interface, a Si channel layer at a position 100 nm away from this interface (Si near the gate insulating film 7 / Si channel layer 5 interface), Y in the gate insulating film 7 ₂ O ₃ This is the layer 7a. SiO ₂ The change of the lattice constant is shown with reference to the lattice spacing of Si at a position 250 nm away from the interface between the layer 3b and the Si substrate 1. Y in insulating film 3 ₂ O ₃ The change in the lattice constant of layer 3a is -2.4%, which is consistent with the result obtained from X-ray diffraction. Si channel layer 5 and SiO ₂ Si of the channel layer 5 near the interface with the layer 7b is Y ₂ O ₃ Distortion is -1.0% accompanying the layer 7a. Further, the lattice constant of the Si layer at a position 50 nm away from this interface also changes by -1.0%. Further, it was confirmed that Si in the channel layer (Si in the vicinity of the interface between the gate insulating film 7 and the Si channel layer 5) at a position 100 nm away from this interface was also distorted by -1.0%. Y in the gate insulating film 7 ₂ O ₃ The change in the lattice constant of the layer 7a is also -2.4%, which is consistent with the result obtained from the X-ray diffraction. The major feature here is that the insulating film 3 containing a crystalline metal oxide having a different lattice spacing from Si is buried in the Si substrate 1, and further, a crystalline metal oxide having a different lattice spacing from Si is provided. By using the gate insulating film 7 containing Si, it is possible to give uniform distortion to Si of the channel layer 5. In other words, Si in the channel layer receives the same stress from the two crystalline metal oxides provided above and below, so that a uniform strain is generated in the depth direction.
[0109]
According to the present embodiment, crystalline Y having a different lattice spacing from Si ₂ O ₃ The insulating film including the layer is buried in the Si substrate, and the crystalline Y ₂ O ₃ Characteristics of a transistor including a layer in a gate insulating film and a transistor having a strained SGOI structure as a comparative example are compared. FIG. 26 shows the Id-Vg characteristics of the p-channel MISFET according to the present embodiment and the p-channel MISFET according to the comparative example. The S factor of the strained SGOI p-channel MISFET according to the comparative example is 81 mV / decade. On the other hand, according to the present embodiment, Y ₂ O ₃ The S-factor of the p-channel MISFET using the layer was 70 mV / decade, and it was confirmed that the p-channel MISFET was not only inferior to the comparative example but also improved. Further, it can be seen that in the present embodiment, the current driving force is also improved as compared with the case of the strained SGOI. This is because the sufficient and uniform compressive strain can be applied in the depth direction to the Si layer of the channel layer, and the mobility of holes is improved. Further, it is considered that the SGOI substrate is used. This is because the decrease in mobility due to the Ge diffusion is avoided.
[0110]
In the seventh embodiment, the crystalline metal oxide forming the insulating films 3a and 7 is Y ₂ O ₃ As an example, the crystalline metal oxide is SrTiO ₃ , SrZrO ₃ , Sr (TiZr) O ₃ , SrCeO ₃ For example, an oxide having a perovskite structure may be used. Further, oxides having a rock salt structure such as MgO, CaO, SrO, and BaO, Al ₂ O ₃ MgAl with spinel structure ₂ O ₄ However, the same effect can be obtained.
[0111]
Although the crystalline metal oxide was shown to be polycrystalline in which the crystal orientation was oriented, it was confirmed that the use of a single crystal metal oxide caused a larger change in the lattice constant. Although the case where an electron beam method is used as a method for forming a crystalline metal oxide is described, another film formation method such as a CVD method, a sputtering method, or an MBE method may be used.
[0112]
Note that among the crystalline metal oxides, rare earth elements (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) It is more preferable to use a rare earth oxide containing at least one or more elements selected from among them. This is because the rare earth oxide can easily increase the crystallinity by controlling the film formation conditions, and can effectively change the lattice spacing of Si. Among them, it was confirmed that when an oxide containing at least one of Ce, Dy, Y, La, Pr, and Gd was used, a film having high crystallinity could be realized, and a particularly high effect was obtained. .
[0113]
In the seventh embodiment, both the crystalline metal oxide having a different lattice spacing from Si embedded in the substrate and the crystalline metal oxide having a different lattice spacing from Si contained in the gate insulating film have Y ₂ O ₃ Although the same metal oxide is not necessarily used for both, it is possible to arbitrarily select from the above-mentioned metal oxides according to the required direction and amount of strain.
[0114]
Further, in the seventh embodiment, the case of the p-channel MISFET has been described, but the same effect can be obtained for the n-channel MISFET. Which metal oxide is selected from the crystalline metal oxides described above depends on whether one wants to apply tensile stress or compressive stress to Si. In the case of manufacturing an n-channel MISFET, a metal oxide having a larger lattice constant than Si is selected because electron mobility is improved in Si to which a tensile stress is applied. On the other hand, in the case of manufacturing a p-channel MISFET, the mobility of holes is improved under either tensile or compressive stress, so that a metal oxide having a different lattice constant from Si may be selected.
[0115]
The lattice constant of the metal oxide is selected according to the stress to be applied. When a desired lattice constant and stress cannot be achieved with a metal oxide containing only one type of metal element, a metal oxide containing two or more types of metal elements may be used. For example, it contains two elements of Eu and Dy (Eu _x Dy _1-x ) ₂ O ₃ By using, the change of the lattice constant of the metal oxide with respect to Si can be arbitrarily changed between 0 and -1.8%.
[0116]
Further, in the seventh embodiment, Y is applied to apply stress to Si of the channel layer. ₂ O ₃ However, it is also possible to use a metal oxide in which the composition ratio of metal and oxygen is smaller than the stoichiometric ratio. As described above in detail, as the crystalline metal oxide, a crystal having high ionic bond may be selected. That is, SrTiO ₃ , SrZrO ₃ , Sr (TiZr) O ₃ , SrCeO ₃ For example, an oxide having a perovskite structure can be used. Further, oxides having a rock salt structure such as MgO, CaO, SrO, and BaO, Al ₂ O ₃ MgAl with spinel structure ₂ O ₄ May be. The crystalline metal oxide may be a single crystal or a polycrystal in which the crystal orientation is oriented. As a method for forming a crystalline metal oxide, an MBE method can be used, and as a film forming method, a method such as a CVD method, a sputtering method, or an electron beam evaporation method can be used. Among the crystalline metal oxides, rare earth elements having strong ionic bonding properties (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, It is more preferable to use a rare earth oxide containing at least one or more elements selected from Yb and Lu). Among them, when an oxide containing at least one of Ce, Dy, Y, La, Pr, and Gd is used, precise control of the composition ratio of metal and oxygen can be realized, and a particularly high effect can be obtained. It was confirmed.
[0117]
The same metal oxide must be used for both the crystalline metal oxide having a different lattice spacing from Si embedded in the substrate and the crystalline metal oxide having a different lattice spacing from Si contained in the gate insulating film. It is also possible to use a metal oxide in which the composition ratio of metal and oxygen is stoichiometric, and use a metal oxide in which the oxygen composition ratio is smaller than the stoichiometric ratio, as in is there. The metal oxide can be arbitrarily selected from the above-described metal oxides according to the required direction and amount of strain.
[0118]
In the seventh embodiment, the Si substrate having the plane orientation of (001) is used, but the plane orientation may be any of (001), (111), and (110). Further, the angle may be slightly deviated from the plane orientation.
[0119]
Further, in the seventh embodiment, a crystalline metal oxide buried in a Si substrate or a crystalline metal oxide contained in a gate insulating film in order to more effectively strain Si in the channel layer; It is also effective to sandwich a metal oxide having a rock salt structure between the channel layer and the channel layer. The effect is the same as that described in detail in the fourth embodiment. By sandwiching a metal oxide having a rock salt structure, an amorphous SiO 2 is formed at the interface with the crystalline oxide. ₂ Since the layer is not formed, the difference in lattice spacing in the metal oxide film is added more directly to the Si channel layer. The thickness of the rock salt structure oxide used is preferably in the range of 1 to 3 atomic layers. Since substances such as SrO and MgO are unstable in the air, if the thickness is further increased, the crystallinity changes over time and the characteristics deteriorate. On the other hand, when the thickness is smaller than one atomic layer, the effect of suppressing diffusion of oxygen cannot be obtained, and amorphous SiO 2 ₂ This is because a layer is generated. Among oxides having a rock salt structure, in particular, when a metal oxide film having a rock salt structure of SrO, MgO, CaO, and BaO is used, the effect of suppressing oxygen diffusion is remarkable, and transistor characteristics can be significantly improved. It is. When it is desired to apply tensile stress to Si, it is preferable to use BaO which is a metal oxide having a rock salt structure having a larger lattice constant than Si. When compressive stress is to be applied to Si, it is desirable to use SrO, MgO, and CaO, which are rock-salt metal oxides having a smaller lattice constant than Si. However, since the change of the lattice constant in the Si layer is mainly determined by the crystalline metal oxide having a large thickness, for example, the SrO having a smaller lattice constant than Si is sandwiched between the metal oxides, and the lattice constant of the SrO is smaller than that of Si. Big Pr ₂ O ₃ In the structure in which Si is stacked, Si in the channel region receives a tensile stress, so that the metal oxide having the rock salt structure and the crystalline metal oxide can be arbitrarily combined. In addition, a crystalline metal oxide having a different lattice spacing from Si embedded in the substrate, a crystalline metal oxide having a different lattice spacing from Si contained in the gate insulating film, and a rock salt structure both at the interface with the channel layer. It is not necessary to sandwich the metal oxide of the above, and the effect can be obtained with either one.
[0120]
(Eighth embodiment)
Next, a method of manufacturing the field-effect transistor according to the eighth embodiment of the present invention will be described with reference to FIGS.
[0121]
First, as shown in FIG. 27A, an element isolation region 2 is formed on a silicon substrate 1 having a (111) plane orientation, and then, for example, a 50 nm thick SiO 2 is formed. ₂ The film 4 is coated on the entire surface. Subsequently, the SiO ₂ By performing ion implantation of both boron and indium elements through the film 4, a sharp impurity profile is formed in the channel region 5. After that, the SiO ₂ After the film 4 is removed by etching with an ammonium fluoride solution, dilute hydrofluoric acid treatment is performed on the surface to terminate the Si surface in the channel region with hydrogen.
[0122]
Next, the silicon substrate 1 is introduced into a laser ablation device. The substrate temperature is set to, for example, 500 ° C., and CeO ₂ Is used as an evaporation source, a metal oxide made of Ce oxide is formed to a thickness of 5 nm to form a metal oxide layer 7 (see FIG. 27B). At this time, the Ce oxide (CeO _x ) Was the stoichiometric ratio (x = 2.0), and the lattice constant was 5.41 °.
[0123]
Next, only the Ce oxide layer 7 on the channel region 5 was irradiated with a laser (see FIG. 27C). When the oxygen composition ratio was measured after laser irradiation, the oxygen composition ratio was reduced to x = 1.77, and the lattice constant was increased to 5.48 °. This is because the laser irradiation caused oxygen deficiency and reduced the oxygen composition ratio. By such a method, the Ce oxide layer 7A having a large lattice constant can be formed only on the channel region 5 (see FIG. 27C). In the example of laser irradiation in the step of FIG. 27C, an effect of reducing the oxygen composition ratio can be obtained by using heat treatment, electron beam irradiation, or electromagnetic wave irradiation. It was confirmed that + 0.8% strain was applied to Si of the channel layer 5 by increasing the lattice constant of the Ce oxide layer 7A. Subsequently, a polysilicon film 9 serving as a gate electrode is deposited on the entire surface by using the CVD method (see FIG. 27D).
[0124]
Next, as shown in FIG. 28A, the polysilicon film 9 and the insulating films 7 and 7A are patterned by using an anisotropic etching method such as an RIE method, and a gate insulating film 7A is formed on the channel region 5. And a gate electrode 9 are formed. Thereafter, by performing ion implantation and a heat process using the gate electrode 9 as a mask, the source / drain regions 11a and 11b into which impurities are introduced are formed.
[0125]
Next, the SiO ₂ The film 13 is deposited on the entire surface (see FIG. 28B). Subsequently, as shown in FIG. 28C, contact holes are formed on the source / drain regions 11a and 11b and the gate electrode 9, and a metal such as Al is deposited to form a metal film on the entire surface. The source / drain electrodes 15a and 15b and the gate connection part 15c are formed, and the MISFET is completed (see FIG. 28C).
[0126]
As described above, according to the present embodiment, since strained Si can be formed in the channel region, it is possible to significantly improve the transistor characteristics. Also, strained Si can be easily formed by laser irradiation or the like.
[0127]
(Ninth embodiment)
Next, a method for manufacturing the field effect transistor according to the ninth embodiment of the present invention will be described with reference to FIGS.
[0128]
First, as shown in FIG. 29A, dilute hydrofluoric acid treatment is performed on the surface of the silicon substrate 1 having the (111) plane orientation, and the surface of the silicon substrate 1 is terminated with hydrogen. Next, the silicon substrate 1 is introduced into a laser ablation device. The substrate temperature is set to, for example, 500 ° C., and CeO ₂ Is used as an evaporation source to form a metal oxide layer 3 made of Ce oxide to a thickness of 10 nm (see FIG. 29A). At this time, the Ce oxide (CeO _x ) Was a stoichiometric ratio (x = 2.0), and the lattice constant was 5.41 °.
[0129]
Next, the Ce oxide layer 3 was irradiated with a laser (see FIG. 29B). After the laser irradiation, the oxygen composition ratio of the Ce oxide layer 3A was measured. As a result, the oxygen composition ratio x was reduced to 1.77, and the lattice constant was increased to 5.48 °. This is because the laser irradiation caused oxygen deficiency and reduced the oxygen composition ratio. By such a method, the Ce oxide layer 3A having a large lattice constant can be manufactured. Here, an example in which laser irradiation is performed has been described, but an effect of reducing the oxygen composition ratio can be obtained by using heat treatment, electron beam irradiation, or electromagnetic wave irradiation.
[0130]
Next, the Si channel layer 5 is formed to a thickness of, for example, 100 nm by using the CVD method (see FIG. 29C). At this time, it was confirmed that Si of the channel layer 5 was strained by + 0.8% because of the lattice constant of the Ce oxide layer 3.
[0131]
Next, element isolation regions 2 are formed on both sides of the Si channel layer 5 (see FIG. 29D). Subsequently, for example, a 50 nm thick SiO ₂ The film 4 is coated on the entire surface (see FIG. 29D). After that, the SiO ₂ By performing ion implantation of boron element through the film 4, a sharp impurity profile is formed in the channel region 5. Subsequently, the SiO ₂ After the film 4 is removed by etching with an ammonium fluoride solution, the surface of the Si channel layer 5 is treated with diluted hydrofluoric acid, and the surface is terminated with hydrogen.
[0132]
Next, by thermal oxidation, SiO 2 ₂ A gate oxide film 7 made of, for example, 3 nm is formed. Subsequently, a polysilicon film 9 serving as a gate electrode is deposited on the entire surface by using the CVD method (see FIG. 30A). Subsequently, as shown in FIG. 30B, the polysilicon film 9 and the gate insulating film 7 are patterned by using an anisotropic etching method such as RIE, for example, so that the gate insulating film 7 A gate electrode 9 is formed. Thereafter, by performing ion implantation and a heat process using the gate electrode 9 as a mask, source / drain regions 11a and 11b into which impurities are introduced are formed (see FIG. 30B).
[0133]
Next, the SiO ₂ The film 13 is deposited on the entire surface (see FIG. 30C). Subsequently, contact holes are formed on the source / drain regions 11a and 11b and the gate electrode 9, and a metal such as Al is deposited to form a metal film on the entire surface, thereby forming the source / drain electrodes 15a and 15b and the gate connection. The portion 15c is formed, and the MISFET is completed (see FIG. 30C).
[0134]
As described above, according to the present embodiment, since strained Si can be formed in the channel region, it is possible to significantly improve the transistor characteristics. Also, strained Si can be easily formed by laser irradiation or the like.
[0135]
(Tenth embodiment)
Next, a method for manufacturing the field-effect transistor according to the tenth embodiment of the present invention will be described with reference to FIGS.
[0136]
First, dilute hydrofluoric acid treatment is performed on the surface of a silicon substrate having a (111) plane orientation, and the surface of the silicon substrate is terminated with hydrogen. Next, the silicon substrate 1 is introduced into a laser ablation device. The substrate temperature is set to, for example, 500 ° C., and CeO ₂ Is used as an evaporation source to form a metal oxide layer 3 made of Ce oxide to a thickness of 10 nm (see FIG. 31A). At this time, the Ce oxide (CeO _x ) Was the stoichiometric ratio (x = 2.0), and the lattice constant was 5.41 °.
[0137]
Next, the Ce oxide layer 3 was irradiated with a laser (see FIG. 31B). After the laser irradiation, the oxygen composition ratio of the Ce oxide layer 3A was measured. As a result, the oxygen composition ratio x was reduced to 1.77, and the lattice constant was increased to 5.48 °. This is because the laser irradiation caused oxygen deficiency and reduced the oxygen composition ratio. By such a method, a Ce oxide 3A having a large lattice constant can be manufactured. Here, an example in which laser irradiation is performed has been described, but an effect of reducing the oxygen composition ratio can be obtained by using heat treatment, electron beam irradiation, or electromagnetic wave irradiation.
[0138]
Next, as shown in FIG. 31C, a Si channel layer 5 is formed with a thickness of, for example, 100 nm by using the CVD method. Subsequently, element isolation regions 2 are formed on both sides of the Si channel layer 5. Subsequently, for example, a 50 nm thick SiO ₂ The film 4 is coated on the entire surface (see FIG. 31C). After that, the SiO ₂ By performing ion implantation of both boron and indium elements through the film 4, a sharp impurity profile is formed in the channel region 5. Subsequently, the SiO ₂ After the film 4 is removed by etching with an ammonium fluoride solution, dilute hydrofluoric acid treatment is performed to terminate the Si surface of the channel layer 5 with hydrogen.
[0139]
Next, the substrate is introduced into the laser ablation device. The substrate temperature is set to, for example, 500 ° C., and CeO ₂ Is used as an evaporation source to form a metal oxide layer 7 of Ce oxide with a thickness of 5 nm (see FIG. 31D). At this time, the Ce oxide (CeO _x ) Was a stoichiometric ratio (x = 2.0), and the lattice constant was 5.41 °.
[0140]
Next, as shown in FIG. 32A, only the Ce oxide layer 7 on the channel region 5 was irradiated with laser. After the laser irradiation, when the oxygen composition ratio of the Ce oxide layer 7A was measured, the oxygen composition ratio x was reduced to 1.77, and the lattice constant was increased to 5.48 °. This is because the laser irradiation caused oxygen deficiency and reduced the oxygen composition ratio. By such a method, the Ce oxide layer 7A having a large lattice constant can be formed only on the channel region 5 (see FIG. 32A). Although an example in which laser irradiation is performed is described here, an effect of reducing the oxygen composition ratio can be obtained by using heat treatment, electron beam irradiation, or electromagnetic wave irradiation. It was confirmed that + 1.0% strain was uniformly applied to Si of the channel layer 5 by increasing the lattice constants of the Ce oxide layer 3A and the Ce oxide layer 7A.
[0141]
Next, a polysilicon film 9 serving as a gate electrode is deposited on the entire surface by using a CVD method (see FIG. 32B). Subsequently, as shown in FIG. 32C, the polysilicon film 9 and the Ce oxide layers 7 and 7A are patterned by using an anisotropic etching method such as an RIE method to form a gate insulating layer on the channel region 5. The film 7A and the gate electrode 9 are formed. Thereafter, by performing ion implantation and a heat process using the gate electrode 9 as a mask, the source / drain regions 11a and 11b into which impurities are introduced are formed. Next, the SiO ₂ A film 13 is deposited on the entire surface. Subsequently, contact holes are formed on the source / drain regions 11a and 11b and the gate electrode 9, and a metal such as Al is deposited to form a metal film on the entire surface, thereby forming the source / drain electrodes 15a and 15b and the gate connection. The portion 15c is formed, and the MISFET is completed (see FIG. 32C).
[0142]
As described above, according to the present embodiment, since strained Si can be formed in the channel region, it is possible to significantly improve the transistor characteristics. Also, strained Si can be easily formed by laser irradiation or the like.
[0143]
(Eleventh embodiment)
Next, a method for manufacturing the field-effect transistor according to the eleventh embodiment will be described with reference to FIGS. In the present embodiment, a method for manufacturing a MISFET having an n-type channel and a p-type channel region will be described.
[0144]
First, as shown in FIG. 33A, an element isolation region 2 is formed on a silicon substrate 1 having a (111) plane orientation. ₂ The film 4 is coated on the entire surface. Subsequently, the SiO ₂ By performing ion implantation of boron element and arsenic element through the film 4, a steep impurity profile is formed in the region 5a used as a p-type channel and the region 5b used as an n-type channel. Subsequently, the SiO ₂ After the film 4 is removed by etching with an ammonium fluoride solution, dilute hydrofluoric acid treatment is performed to terminate the Si surfaces of the channel regions 5a and 5b with hydrogen.
[0145]
Next, Dy ₂ O ₃ The insulating film 7 containing an oxide is ₂ O ₃ Was formed using an electron beam evaporation method as an evaporation source. Dy ₂ O ₃ Layer 7a was deposited to a thickness of 5 nm. At this time, the oxygen partial pressure was 1 × 10 ^-7 By precisely controlling Torr, Dy ₂ O ₃ The crystallinity was improved by increasing the orientation of the layer 7a. Further, Si on the surface of the channel layer is oxidized, and the channel layers 5a and 5b and Dy ₂ O ₃ 0.5 nm thick SiO 2 is provided between the oxide layer 7a and the oxide layer 7a. ₂ The layer 7b was formed. That is, the gate insulating film 7 is made of a 0.5 nm thick SiO 2 film. ₂ Layer 7b and a 5 nm thick Dy ₂ O ₃ It has a laminated structure composed of the layer 7a. From the X-ray diffraction evaluation, Dy ₂ O ₃ The layer 7a was a polycrystalline film oriented in the (001) direction, and had a lattice constant of 5.33 ° (a lattice constant smaller than Si by 1.8%). The half-width of X-ray diffraction is narrow, Dy ₂ O ₃ It was confirmed that the layer 7a was a film with high crystallinity strongly oriented to (001). As a result of lattice constant evaluation using electron beam diffraction, Dy is strongly oriented to (001) and has high crystallinity. ₂ O ₃ It was confirmed that by forming the layer 7a, compressive stress was applied to Si of the channel layer 5, and the lattice constant was reduced. Dy ₂ O ₃ The change in the lattice constant of the layer 7a is -1.8% as compared with the lattice constant of Si, and this Dy ₂ O ₃ It was found that Si at the interface was distorted accompanying the layer 7a, and the change in the lattice constant of Si at this interface was -0.5%. The lattice constant also changed in Si at a position 50 nm away from the interface, and the lattice constant changed by -0.4%.
[0146]
Next, only the gate insulating film 7 on the n-type channel layer 5b is selectively irradiated with laser, ₂ O ₃ Was changed to obtain a gate insulating film 7A containing Dy oxide having Dy: O = 2.0: 2.5. At this time, the lattice constant of the Dy oxide having Dy: O = 2.0: 2.5 was 0.7% larger than the lattice constant of Si. This is because, as described above, the oxygen at the lattice position in the crystal escapes, and the lattice position of the Dy atom bonded to the escaped oxygen is pulled by the bond with another oxygen, thereby deviating from the original lattice position. This is because the lattice is displaced, and as a result, the average distance between the lattices increases, and the lattice constant increases. Further, the lattice constant of Si in the n-type channel layer 5b was increased by + 0.3%. This is because, by making the lattice spacing of Dy oxide having Dy: O = 2.0: 2.5, which is strongly oriented to (001) and high in crystallinity, larger than that of Si, tensile stress is applied to Si of the channel layer. Is added to increase the lattice constant. From this result, by using an insulating film containing a metal oxide having a smaller lattice spacing than Si and having high crystallinity as a gate insulating film and performing local laser irradiation, the p-type channel has a compressive strain, an n-type A tensile strain can be generated in the channel, and the performance of the CMOS can be greatly improved.
[0147]
Next, a polysilicon film 9 serving as a gate electrode is deposited on the entire surface by using the CVD method (see FIG. 33D). Subsequently, as shown in FIG. 34A, the polysilicon film 9 and the gate insulating films 7 and 7A containing Ce oxide are patterned by using an anisotropic etching method such as RIE to form a channel region 5a. 5b, a gate insulating film 7 and a gate electrode 9a, and a gate insulating film 7A and a gate electrode 9b are formed. Thereafter, using the gate electrodes 9a and 9b as masks, ion implantation of boron element and arsenic element and a heating step are performed to form source / drain regions 11a, 11b, 12a, and 12b into which impurities are introduced. (See FIG. 34 (a)).
[0148]
Next, the SiO ₂ The film 13 is deposited on the entire surface (see FIG. 34B). Subsequently, as shown in FIG. 34C, contact holes are formed on the source / drain regions 11a, 11b, 12a, 12b and the gate electrodes 9a, 9b, and a metal such as Al is deposited to form a metal film. By forming them on the entire surface, the source / drain electrodes 15a, 15b, 16a, 16b and the gate connection parts 15c, 16c are formed, and the MISFET is completed (see FIG. 34C).
[0149]
As described above, the transistor according to the present embodiment having the n-type channel and the p-type channel and modulating the lattice constant of the Dy oxide on the n-type channel side, and the amorphous SiO 2 as a comparative example ₂ Were compared with a transistor having a strained SGOI structure having a gate insulating film. FIG. 35 shows the comparison result.
[0150]
As shown in FIG. ₂ SiO with an equivalent thickness (EOT) of 8 nm ₂ CMOSFET (hereinafter also referred to as SGOI CMOS) having a gate insulating film made of ₂ Dy oxide / SiO with converted thickness (EOT) of 8 nm ₂ The power supply voltage dependence of the gate delay time of the CMOSFET (hereinafter, also referred to as a lattice local modulation type CMOS) according to the present embodiment having an insulating film having a laminated structure was compared. It can be seen that the lattice local modulation type CMOS is lower than the SGOI type CMOS over the entire voltage range, and that the delay time can be reduced by using the lattice local modulation type CMOS. This is because the mobility of only electrons is improved and the mobility of holes is not significantly improved because the SGOI type applies tensile strain to both the n-type and the p-type. This is because the tensile strain is applied to the mold and the compressive strain is applied to the p-type, so that the mobility of both electrons and holes is significantly improved.
[0151]
As described above, according to the present embodiment, not only the n-channel MISFET and the p-channel MISFET but also the composite CMOS thereof includes the metal oxide whose lattice spacing changes with Si by controlling the oxygen composition. By using an insulating film as a gate insulating film, characteristics can be significantly improved. Further, the same effect can be obtained by performing the above method on a metal oxide buried in a substrate. Furthermore, it is possible to further improve the performance by burying a metal oxide whose lattice spacing changes with Si by controlling the oxygen composition in a substrate and using the metal oxide as a gate insulating film in combination. is there.
[0152]
Further, in the eighth to eleventh embodiments, examples in which a Ce oxide and a Dy oxide are used to apply a stress to Si of the channel layer have been described. As the substance, a crystal having a high ionic bond may be selected. That is, SrTiO ₃ , SrZrO ₃ , Sr (TiZr) O ₃ , SrCeO ₃ For example, an oxide having a perovskite structure can be used. Further, oxides having a rock salt structure such as MgO, CaO, SrO, and BaO, Al ₂ O ₃ MgAl with spinel structure ₂ O ₄ May be. The crystalline metal oxide may be a single crystal or a polycrystal in which the crystal orientation is oriented.
[0153]
As a method for forming a crystalline metal oxide, an MBE method can be used, and as a film forming method, a method such as a CVD method, a sputtering method, or an electron beam evaporation method can be used. Among the crystalline metal oxides, rare earth elements having strong ionic bonding properties (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, It is more preferable to use a rare earth oxide containing at least one or more elements selected from Yb and Lu). Among them, it is confirmed that when an oxide containing at least one of Ce, Dy, Y, La, Pr, and Gd is used, precise control of the oxygen composition ratio can be realized, and a particularly high effect can be obtained. did.
[0154]
In the case as shown in the eleventh embodiment, both the crystalline metal oxide having a different lattice spacing from Si embedded in the substrate and the crystalline metal oxide having a different lattice spacing from Si contained in the gate insulating film are used. It is not necessary to use the same metal oxide for both. It is also possible to use a metal oxide whose oxygen composition ratio is a stoichiometric ratio on one side and a metal oxide whose oxygen composition ratio is smaller than the stoichiometric ratio on the other side. The metal oxide can be arbitrarily selected according to the required direction and amount of strain.
[0155]
In the eighth to eleventh embodiments, a Si substrate having a plane orientation of (111) is used, but the plane orientation may be any of (001), (111), and (110). Further, the angle may be slightly deviated from the plane orientation.
[0156]
Further, in the eighth to eleventh embodiments, the crystalline metal oxide embedded in the Si substrate or the crystalline metal oxide contained in the gate insulating film is used to more effectively distort the Si of the channel layer. It is also effective to sandwich a metal oxide having a rock salt structure between the object and the channel layer. The effect is the same as that described in detail in the fourth embodiment. By sandwiching a metal oxide having a rock salt structure, an amorphous SiO 2 is formed at the interface with the crystalline oxide. ₂ Since the layer is not formed, the difference in lattice spacing in the metal oxide film is added more directly to the Si channel layer. The thickness of the rock salt structure oxide used is preferably in the range of 1 to 3 atomic layers. Since substances such as SrO and MgO are unstable in the air, if the thickness is further increased, the crystallinity changes over time and the characteristics deteriorate. On the other hand, when the thickness is smaller than one atomic layer, the effect of suppressing diffusion of oxygen cannot be obtained, and amorphous SiO 2 ₂ This is because a layer is generated. Among oxides having a rock salt structure, in particular, when a metal oxide film having a rock salt structure of SrO, MgO, CaO, and BaO is used, the effect of suppressing oxygen diffusion is remarkable, and transistor characteristics can be significantly improved. It is. When it is desired to apply tensile stress to Si, it is preferable to use BaO which is a metal oxide having a rock salt structure having a larger lattice constant than Si.
[0157]
When compressive stress is to be applied to Si, it is desirable to use SrO, MgO, and CaO, which are rock-salt metal oxides having a smaller lattice constant than Si. However, since the change of the lattice constant in the Si layer is mainly determined by the crystalline metal oxide having a large thickness, for example, the SrO having a smaller lattice constant than Si is sandwiched between the metal oxides, and the lattice constant of the SrO is smaller than that of Si. Big Pr ₂ O ₃ In the structure in which Si is stacked, Si in the channel region receives a tensile stress, so that the metal oxide having the rock salt structure and the crystalline metal oxide can be arbitrarily combined. In the case of the eleventh embodiment, a crystalline metal oxide having a different lattice spacing from Si embedded in a substrate and a crystalline metal oxide having a different lattice spacing from Si contained in a gate insulating film are provided. It is not necessary to sandwich a metal oxide having a rock salt structure on both the interface with the channel layer, and the effect can be obtained with either one.
[0158]
【The invention's effect】
As described above, according to the present invention, the transistor characteristics can be significantly improved.
[Brief description of the drawings]
FIG. 1 is a sectional view showing the configuration of a field-effect transistor according to a first embodiment of the present invention.
FIG. 2 is a sectional view of a manufacturing process of the method for manufacturing the field-effect transistor according to the first embodiment.
FIG. 3 is a sectional view of the manufacturing process of the method for manufacturing the field-effect transistor according to the first embodiment.
FIG. 4 shows Pr of the field-effect transistor according to the first embodiment. ₂ O ₃ / SiO ₂ FIG. 2 is a schematic view showing a cross section of an / Si interface.
FIG. 5 shows Pr of the field-effect transistor according to the first embodiment. ₂ O ₃ Layer, SiO ₂ FIG. 5 is a graph showing changes in lattice constants at the / Si interface and the channel layer.
FIG. 6 is a characteristic diagram showing a relationship between a gate voltage Vg and a drain current Id by the field-effect transistors according to the first embodiment and the comparative example.
FIG. 7 is a schematic view showing a cross section of a Ce oxide / Si interface of a field-effect transistor according to a third embodiment of the present invention.
FIG. 8 is a diagram showing measurement positions of Ce oxide / Si interfaces and change values of lattice constants according to a third embodiment.
FIG. 9 is a view showing the relationship between the composition ratio of metal and oxygen and the lattice constant of the Ce oxide of the field-effect transistor according to the third embodiment.
FIG. 10 is a schematic diagram showing that Ce in the field-effect transistor according to the third embodiment loses oxygen to cause oxygen deficiency and increases the average lattice constant of the Ce oxide;
FIG. 11 is a characteristic diagram showing a relationship between a composition ratio of a metal of Ce oxide and oxygen, and a gate voltage and a drain current of the field-effect transistors according to the third embodiment and a comparative example.
FIG. 12 is a sectional view showing a configuration of a field-effect transistor according to a fifth embodiment of the present invention.
FIG. 13 is a sectional view showing the manufacturing process of the field-effect transistor according to the fifth embodiment.
FIG. 14 is a sectional view showing the manufacturing process of the field-effect transistor according to the fifth embodiment.
FIG. 15 shows a Si / SiO according to a fifth embodiment. ₂ / La ₂ O ₃ / SiO ₂ / Si / SiO ₂ FIG. 2 is a schematic diagram showing a cross section of an interface.
FIG. 16 shows a Si / SiO according to a fifth embodiment. ₂ / La ₂ O ₃ / SiO ₂ / Si / SiO ₂ The figure which shows the measurement position of an interface, and the change value of a lattice constant.
FIG. 17 is a cross-sectional view illustrating a structure of a field-effect transistor having a strained SOI structure.
FIG. 18 is a characteristic diagram showing a relationship between a gate voltage and a drain current of SOI field effect transistors according to the fifth embodiment and a comparative example.
FIG. 19 is a characteristic diagram showing a relationship between a gate voltage and a drain current of the SOI field effect transistor according to the sixth embodiment and a comparative example.
FIG. 20 is a sectional view showing the configuration of the field-effect transistor according to the seventh embodiment;
FIG. 21 is a sectional view showing the manufacturing process of the field-effect transistor according to the seventh embodiment.
FIG. 22 is a sectional view showing the manufacturing process of the field-effect transistor according to the seventh embodiment.
FIG. 23 is a sectional view showing the manufacturing process of the field-effect transistor according to the seventh embodiment.
FIG. 24 shows the Si / SiO of the field-effect transistor according to the seventh embodiment. ₂ / Y ₂ O ₃ / SiO ₂ / Si / SiO ₂ FIG. 2 is a schematic diagram showing a cross section of an interface.
FIG. 25 shows the Si / SiO of the field-effect transistor according to the seventh embodiment. ₂ / Y ₂ O ₃ / SiO ₂ / Si / SiO ₂ The figure which shows the measurement position of an interface, and the change value of a lattice constant.
FIG. 26 is a characteristic diagram showing a relationship between a gate voltage and a drain current of the SOI field effect transistor according to the seventh embodiment and a comparative example.
FIG. 27 is a sectional view showing the manufacturing process of the method for manufacturing the field effect transistor according to the eighth embodiment of the present invention.
FIG. 28 is a sectional view showing the manufacturing process of the method for manufacturing the field effect transistor according to the eighth embodiment of the present invention.
FIG. 29 is a sectional view showing the manufacturing process of the method for manufacturing the field effect transistor according to the ninth embodiment of the present invention.
FIG. 30 is a sectional view showing the manufacturing process of the method for manufacturing the field effect transistor according to the ninth embodiment of the present invention.
FIG. 31 is a sectional view showing the manufacturing process of the method for manufacturing the field effect transistor according to the tenth embodiment of the present invention.
FIG. 32 is a sectional view showing the manufacturing process of the method for manufacturing the field effect transistor according to the tenth embodiment of the present invention.
FIG. 33 is a sectional view showing the manufacturing process of the method for manufacturing the field effect transistor according to the eleventh embodiment of the present invention.
FIG. 34 is a sectional view showing the manufacturing process of the method for manufacturing the field effect transistor according to the eleventh embodiment of the present invention.
FIG. 35 is a characteristic diagram showing a relationship between a drain voltage and a delay time of a field-effect transistor manufactured according to the eleventh embodiment and a transistor according to a comparative example.
[Explanation of symbols]
1 Silicon substrate
2 Device isolation area
3 insulating film
3a Insulating film
3b SiO ₂ film
3c SiO ₂ film
5 Channel region (channel layer)
7 Gate insulating film
7a insulating film
7b SiO ₂ film
9 Gate electrode
11a Source area
11b Drain region
13 Insulating film
15a Source electrode
15b drain electrode
15c Gate connection

Claims (17)

A semiconductor region formed on the substrate, a channel region of the first conductivity type formed on the semiconductor region, and a metal oxide layer formed on the channel region and made of crystalline material having a different lattice spacing from the substrate are included. A gate insulating film, a gate electrode formed on the gate insulating film, and a second conductivity type source / drain region formed in the semiconductor region on both sides of the gate electrode; A field effect transistor characterized in that the lattice spacing is modulated. A semiconductor region formed in the substrate, a first conductivity type channel region formed in the semiconductor region, and a metal oxide formed between the substrate and the channel region and made of crystalline material having a different lattice spacing from the substrate. An insulating film including at least a layer; a gate insulating film formed on the channel region; a gate electrode formed on the gate insulating film; and a second conductive film formed on the semiconductor region on both sides of the gate electrode. A field-effect transistor, comprising: a source / drain region of a mold type, wherein a lattice spacing of at least a channel region of the substrate is modulated. 3. The field effect transistor according to claim 1, wherein the metal oxide layer is made of a rare earth oxide containing at least one kind of rare earth element. 4. The field effect transistor according to claim 1, wherein the metal oxide layer contains at least one metal element of Ce, Dy, Y, Gd, La, and Pr. 5. The field effect transistor according to claim 1, wherein the metal oxide layer has a composition ratio of metal and oxygen smaller than a stoichiometric ratio. The field effect transistor according to claim 5, wherein the lattice spacing of the metal oxide layer is different from the lattice spacing when the composition ratio of metal and oxygen is stoichiometric. The field effect transistor according to claim 1, wherein a crystalline rock salt structure metal oxide is provided between the metal oxide layer and the channel region. The field effect transistor according to claim 7, wherein the rock salt structure metal oxide contains one or more metal elements of Mg, Ca, Sr, and Ba. A semiconductor region formed in the substrate, a first conductivity type channel region formed in the semiconductor region, and a first crystalline region formed between the substrate and the channel region and having a different lattice spacing from the substrate. A first insulating film including at least a metal oxide layer, a gate insulating film formed on the channel region and including at least a second metal oxide layer made of crystalline material having a different lattice spacing from the substrate; A gate electrode formed on the film; and a source / drain region of the second conductivity type formed in the semiconductor region on both sides of the gate electrode. At least a lattice spacing of the channel region of the substrate is modulated. A field-effect transistor. The field effect transistor according to claim 9, wherein at least one of the first and second metal oxide layers is made of a rare earth oxide containing at least one kind of rare earth element. 11. The method according to claim 9, wherein at least one of the first and second metal oxide layers contains at least one metal element of Ce, Dy, Y, Gd, La, and Pr. Field effect transistor. The field-effect transistor according to claim 9, wherein at least one of the first and second metal oxide layers has an oxygen composition ratio smaller than a stoichiometric ratio. 13. The field effect transistor according to claim 12, wherein the lattice spacing of at least one of the first and second metal oxide layers is different from the lattice spacing when the oxygen composition ratio is a stoichiometric ratio. 14. The field effect transistor according to claim 9, wherein a crystalline rock salt structure metal oxide layer is provided between the second metal oxide layer and the channel region. The field effect transistor according to claim 14, wherein the rock salt structure metal oxide contains one or more metal elements of Mg, Ca, Sr, and Ba. Forming an insulating film containing at least a crystalline metal oxide on a substrate, reducing the oxygen composition ratio in the metal oxide from the stoichiometric ratio; and forming a gate electrode and each of the gate electrode on the insulating film. Forming a source / drain region on the substrate on the side of the field-effect transistor. 17. The field effect transistor according to claim 16, wherein the step of reducing the oxygen composition ratio from the stoichiometric ratio includes performing at least one of heat treatment, laser irradiation, electron beam irradiation, and electromagnetic wave irradiation on the insulating film. Manufacturing method.

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